Edge Grandmaster / Time Hub (GNSS Holdover & PTP)
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An Edge Grandmaster / Time Hub builds a trustworthy local timescale by disciplining a high-stability oscillator with GNSS/external references, cleaning jitter, and distributing PTP/SyncE/1PPS/10MHz/ToD with provable logs. It is not a forwarding Boundary Clock—its job is time source quality, holdover behavior, controlled switchover, and evidence you can verify in the lab and in the field.
What a Time Hub is at the edge (and what it is not)
An Edge Grandmaster / Time Hub is a time-source appliance that turns GNSS (and/or external 1PPS/10MHz/ToD) into stable, distributable time at the edge. It disciplines an OCXO/CSAC, cleans jitter, generates trusted time-of-day, and exports PTP, SyncE/10MHz, 1PPS, and ToD while continuously logging time-quality evidence.
- Time source + holdover: steers a local oscillator to a reference, then maintains bounded drift when GNSS degrades or disappears.
- Jitter cleaning + distribution: shapes phase noise across the clock chain and fans out low-jitter references to ports and subsystems.
- Proves correctness: monitors time error, detects phase steps, and records events/alarms so time quality can be audited remotely.
- Does not solve switch queuing or TSN scheduling inside boundary-clock/transport switches.
- Does not replace the role of a boundary clock that propagates time through multi-hop packet forwarding.
Time Hub owns “time source + oscillator holdover”; boundary clocks and switches own “time propagation through packet forwarding.” A practical ownership check is simple: if PPS/ToD/PTP are self-consistent at the Time Hub outputs but downstream nodes disagree, the fault typically lies in the network propagation path (not inside the Time Hub).
- “GNSS is locked, so time must be perfect.” Lock is not a quality guarantee. The system still needs measurable limits on time error, phase steps during reference switching, and holdover drift.
- “PTP jitter is always the GM.” Without checking 1PPS/ToD/PTP consistency at the GM outputs, packet-domain symptoms are misleading.
- “A good oscillator fixes everything.” The oscillator helps only if the servo bandwidth and jitter-cleaning chain are designed to avoid injecting reference noise.
To be operationally useful at edge sites, a Time Hub should provide a small set of remotely verifiable signals and counters: (1) time error / offset estimates, (2) oscillator control word / frequency offset, (3) GNSS quality indicators, (4) PLL lock states, and (5) event logs for holdover entry/exit and phase-step detection. These signals allow time quality to be proven without physical access.
Diagram text sizes are kept ≥18px-equivalent for mobile readability; only standard block labels are shown.
Ports, references, outputs, and a verifiable three-chain model
A Time Hub architecture should be read as a measurable system, not a pretty diagram. The most useful framing is to split the box into three chains that can be independently validated: reference chain (GNSS/external reference quality), oscillator chain (local stability and steering), and distribution chain (jitter cleaning + fanout + port consistency). Each chain has a small set of test points that tell whether the chain is healthy.
- Purpose: decide whether GNSS/external reference is trustworthy enough to steer the oscillator.
- Core outputs: lock state, reference quality score, detected phase steps or anomalies.
- What can go wrong: “locked but noisy” GNSS, multipath-induced wander, intermittent 1PPS integrity.
- Purpose: provide short-term stability and bounded drift when the reference is degraded or absent.
- Core observables: frequency offset estimate, control word/DAC value, temperature, aging trend.
- What can go wrong: servo hunting, too-wide loop injecting reference noise, poor thermal behavior.
- Purpose: shape phase noise via jitter-cleaning PLL and distribute stable clocks to outputs and timestamp domain.
- Core observables: PLL lock, additive jitter budget, per-port offset consistency (PPS/ToD/PTP).
- What can go wrong: fanout additive jitter, supply-noise coupling, port delay mismatches causing fixed offsets.
| Test Point | Where it sits | What to measure | What it proves |
|---|---|---|---|
| TP-A1 (Time) | Reference chain output (post-qualification) | 1PPS phase vs internal time counter, phase-step detection | Reference integrity and whether steering should be allowed |
| TP-B1 (Freq) | Oscillator chain (control loop telemetry) | Frequency offset estimate, control word/DAC value, temperature | Holdover health and whether the servo is stable (not hunting) |
| TP-C1 (Noise) | Jitter-cleaner PLL output | Integrated jitter / phase noise (L(f) / jitter integration) | Whether distribution is improving or degrading time quality |
| TP-C2 (Port) | Outputs (PTP/SyncE/1PPS/ToD) | PPS/ToD/PTP self-consistency, fixed offsets across ports | Trusted export and whether calibration/port delay is controlled |
| TP-D (Evidence) | Event log / alarms | Holdover entry/exit, phase-step events, lock transitions | Remote auditability and field forensics |
The key architectural deliverable is a clean separation of responsibilities: reference chain decides confidence, oscillator chain carries stability, and distribution chain preserves and replicates it. When these three chains are observable, field incidents become diagnosable without on-site instrumentation.
The figure is intentionally block-diagram heavy with minimal text to stay readable on mobile screens.
GNSS, external 1PPS/10MHz/ToD, and reference qualification
At edge sites, a “locked” reference is not the same as a trustworthy reference. A Time Hub needs a reference qualification layer that scores GNSS and external inputs, applies hysteresis to avoid flapping, and controls phase steps during switchover so exported time stays bounded and auditable.
Multi-constellation and dual-frequency GNSS help not by “more satellites” as a marketing line, but by changing failure modes that dominate edge deployments:
- Obstruction tolerance: when one sky view is blocked, usable satellites remain, reducing lock-drop frequency and unnecessary holdover entries.
- Multipath resilience (lower wander): dual-frequency reduces slow, low-frequency position/time wander that can drive the disciplining loop to chase noise.
- Faster convergence after reboot/outage: edge nodes reboot more often than core facilities; recovery time directly affects “time-available” windows and alarm policy.
External 1PPS, 10MHz, and ToD inputs serve three edge-useful roles:
- Backup reference: a stable upstream can keep the oscillator steered when GNSS becomes intermittent.
- Hierarchy / cascading: a site can follow a local “time tree” where one hub provides reference to others.
- Cross-validation: GNSS and external reference can be compared continuously; disagreement is a strong signal for qualification and event logging.
Qualification converts raw “lock” signals into an operational decision. A robust implementation combines three categories of features into a quality score and uses enter/exit thresholds (hysteresis) to prevent rapid toggling:
- GNSS features: lock status, satellite health indicators, SNR trend, detected anomalies (e.g., sudden phase jumps), short-term time-error noise level.
- External features: 1PPS integrity (missing/extra pulses), 10MHz stability, ToD second-boundary continuity.
- Consistency features: GNSS↔External phase delta stability; slow drift vs sudden step; sustained disagreement beyond a window.
A phase step happens when the active reference changes faster than the oscillator/time counter can be brought into alignment. Three practical causes dominate:
- Pre-existing offset: GNSS and external references are not phase-aligned (fixed offset or slow drift), so switching “reveals” the difference.
- Alignment strategy: an abrupt step forces immediate alignment; a controlled slew ramps phase/frequency to avoid discontinuities.
- Path delay mismatch: different input paths (or port calibration differences) shift the effective phase unless the same delay model is applied.
An engineering-grade objective is written as a bounded event rather than a vague promise: define a maximum allowed phase step at switchover (e.g., tens of nanoseconds in a single chassis context), enforce it with a slew limiter, and record every event with timestamp and magnitude so field behavior is provable.
- Time-domain: measure 1PPS phase difference before/after switch with a time-interval counter; repeat switches and report max + percentile.
- Continuity: validate ToD second boundary does not jump backward; confirm time counter monotonicity across events.
- Evidence: log reference quality score, switch reason, holdover entry/exit, and measured phase-step magnitude.
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OCXO vs CSAC: paying for holdover (and what to measure)
Oscillator selection is not a spec-sheet contest. It is a decision about holdover drift control under realistic edge outages. The right choice is the one whose time-scale behavior (short-term noise, mid-term wander, long-term drift) matches the required holdover window and the site’s thermal and operational constraints.
Holdover is the period where exported time is maintained by the local oscillator when the active reference is degraded or unavailable. The engineering target is expressed as bounded time error growth over a defined window (minutes to hours), with telemetry that supports remote verification. Without this, “GNSS outage” becomes an unpredictable service event.
- Phase noise / integrated jitter: influences short-window time-error noise and how clean the distribution chain can be.
- Allan deviation (ADEV): predicts stability across time scales and is the best bridge between oscillator physics and holdover behavior.
- Temperature sensitivity: directly shapes drift in real enclosures; thermal dynamics often dominate beyond the first seconds.
- Aging: drives long-term frequency offset trends; it matters when recalibration opportunities are rare.
- Warm-up / stabilization: defines “time-available after power-up,” critical for edge reboot events.
OCXO commonly wins on cost and integration simplicity but is more sensitive to enclosure thermal dynamics and aging behavior. CSAC typically offers stronger long-window stability per watt within a compact module, which can materially improve holdover in unattended edge sites—at the expense of higher cost and integration requirements. The correct answer depends on the required holdover window and the allowable drift budget.
ADEV is most useful when read as a “time-scale map.” Three windows explain most observed behavior:
- τ ≈ 1 s: short-term noise dominance (phase noise / loop disturbances) → drives fast jitter and short-window offset variation.
- τ ≈ 10 s: mid-term wander (thermal control dynamics, reference noise coupling) → drives slow oscillations and servo “hunting” risk.
- τ ≈ 100 s: longer-term drift (temperature trend + aging emergence) → drives minutes-scale holdover error growth.
The longer the required holdover window, the more the selection should weight the longer-τ region and enclosure thermal behavior.
| Metric | Why it matters for exported time | How to validate (lab or field) |
|---|---|---|
| ADEV (τ=1s/10s/100s) | Predicts stability at different time scales; maps to holdover error growth and susceptibility to wander. | Log time error and frequency offset over time; correlate holdover drift with temperature and control word trend. |
| Phase noise / jitter | Sets the floor for short-window time noise and affects how much jitter cleaning must do downstream. | Measure phase noise or integrated jitter at key outputs (10MHz / recovered clock). Use a consistent integration band. |
| Warm-up time | Determines how quickly the hub can export stable time after power-up or reboot. | Power-cycle tests: track time error convergence to a stable prove-able state; record worst-case across temperatures. |
| Temperature sensitivity | Dominates drift in compact edge enclosures; thermal ramps drive minutes-scale offset changes. | Temperature sweep or controlled thermal ramp; log time error, frequency offset, and enclosure temperature together. |
| Aging trend | Sets long-term recalibration needs; impacts multi-week behavior and “baseline offset” drift. | Long-duration telemetry: observe frequency offset trend; apply periodic reference comparison and record corrections. |
The diagram avoids dense text and keeps labels large (≥18px) to remain readable on mobile devices.
How GNSS steers the oscillator without hunting
Disciplining is a control loop that converts phase/time error into a bounded oscillator correction. The loop must be tuned so it converges quickly enough for operations, but does not inject GNSS measurement noise or fall into hunting that creates periodic time-error oscillations.
A practical GNSSDO-style disciplining loop can be read as a signal chain with clear test points: phase detector/TDC produces a phase error, a loop filter shapes the response, a DAC/EFC applies correction to an OCXO/CSAC, and a monitor logs time error and control effort. When these observables are missing, tuning becomes guesswork.
- TP1: time/phase error (e.g., 1PPS vs internal time counter) — proves convergence and steady-state noise.
- TP2: control word / DAC value — exposes loop effort, saturation, and slow thermal/aging trends.
- TP3: oscillator output (10MHz/clock domain) — validates what the distribution chain receives.
Bandwidth is the dominant trade-off knob. A wider loop responds faster to reference changes, but is more likely to pull GNSS measurement noise into the output. A narrower loop protects short-term stability by leaning on the oscillator, but may converge slowly and correct long-term drift later than operations prefer.
- Too wide: steady-state time error becomes “hairy” (high-frequency noise), and periodic oscillations can appear if phase margin is weak.
- Too narrow: recovery after cold start or reference restoration is slow, and holdover exit takes longer to return to a tight error band.
| Criterion | What to look for | What it implies |
|---|---|---|
| Convergence time | After boot or switchover, time error enters a stable band and stays there (no repeated re-entry events). | Loop strength is sufficient; reference qualification and gating are not forcing frequent resets. |
| Steady-state time error RMS | RMS/percentiles stabilize; high-frequency noise does not dominate the error trace. | Bandwidth is not injecting reference measurement noise into exported time. |
| Overshoot / ringing | Step-like disturbances do not produce large overshoot; error does not ring with a persistent period. | Phase margin is adequate; loop filter is not under-damped. |
| Control effort sanity | Control word changes smoothly; does not hit rails repeatedly; no sawtooth “fight” behavior. | DAC/EFC range and integral action are well-bounded; no integrator wind-up. |
| Observed symptom | Likely cause | Parameter direction |
|---|---|---|
| Time error oscillates with a 10–30 s period | Loop too wide or filter too light; insufficient phase margin; noisy reference coupled into loop. | Narrow bandwidth, strengthen low-pass filtering, add slew limiting; verify qualification gating. |
| Time error looks “hairy” but mean stays near zero | GNSS measurement noise is injected; bandwidth too wide for the site’s GNSS quality. | Narrow bandwidth, raise reference quality threshold, increase measurement averaging. |
| Recovery after outage is slow | Bandwidth too narrow or integral action too weak; conservative gating keeps steer disabled too long. | Slightly widen bandwidth, strengthen integral carefully; keep overshoot/oscillation under watch. |
| Control word repeatedly hits limits | Insufficient EFC range, wind-up, or reference instability forcing corrections beyond capability. | Limit integral, improve qualification, review EFC range/temperature stability; log saturation events. |
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What gets cleaned, what leaks through, and how to prove it
A jitter-cleaning PLL does not “remove all jitter.” It reshapes noise: in-band the output follows the input reference, and out-of-band the output follows the PLL’s VCO/oscillator. The clock tree (mux/fanout/buffers) then adds additive jitter and can couple supply noise into phase noise unless isolation and power integrity are designed and verified.
- In-band: output tracks the input reference (good when the input is clean, risky when the input is noisy in that band).
- Out-of-band: output tracks the PLL’s VCO/clock source (beneficial if the local source is cleaner than the input at high offsets).
- Implication: PLL bandwidth selection decides what portion of input jitter is passed vs rejected.
Even with a good cleaner, distribution can dominate the final result at multi-port edge hubs:
- Additive jitter accumulation: each fanout stage adds noise; cascaded buffers can set the jitter floor at the ports.
- Mux/switchover disturbance: clock muxing and redundancy switching can introduce short transients if not carefully bounded and logged.
- Supply-noise coupling: buffer and PLL sensitive nodes convert rail ripple into phase modulation, especially under changing loads/thermal states.
- Crosstalk/isolation: adjacent clock nets and poor return paths can inject deterministic spurs and widen integrated jitter.
The fastest way to prove “cleaning” vs “leakage” is a consistent three-point measurement plan:
- TP-IN: at the PLL input (reference-in)
- TP-OUT: at the PLL output (cleaned clock)
- TP-PORT: at a representative output after fanout/mux (port-out)
Compare phase-noise shape and integrated jitter across the same integration band. If TP-OUT improves but TP-PORT worsens, the clock tree is the culprit (additive jitter or coupling). If TP-IN is already noisy and the PLL bandwidth overlaps that region, “cleaning” will appear limited by design.
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Where timestamps are made trustworthy (inside the grandmaster)
A “hardware timestamp” is trustworthy only when the timestamp point is bound to a stable time counter, aligned to the 1PPS second boundary, and continuously checked for consistency and monotonicity. Without these proofs, the timestamp source is a label, not evidence.
A grandmaster can create timestamps at different points of its internal packet-processing chain. The key is not the name of the block, but how much internal uncertainty remains between the timestamp point and the physical egress/ingress boundary.
- MAC timestamp: integrated and convenient; relies on a well-defined internal path to keep repeatability.
- PHY timestamp: closer to the line side; reduces uncertainty from internal buffering paths.
- Dedicated timestamp unit (TSU): separates time capture from general logic and makes the evidence chain easier to audit.
Trustworthy timing requires that ToD (time-of-day), PTP time, and 1PPS describe the same second boundary. A robust grandmaster uses 1PPS as the boundary anchor, a high-resolution time counter for sub-second time, and performs a second-boundary consistency check so “seconds” never drift apart silently.
- 1PPS alignment: defines the second tick; used to validate counter rollover/epoch behavior.
- Time counter: provides fine time within the second; must remain stable and measurable.
- Second-boundary check: ToD second update and 1PPS boundary must match within a small window and be logged when violated.
| Proof item | What must stay bounded | What to log |
|---|---|---|
| PPS / ToD / PTP consistency | Differences between the three time representations remain within a defined threshold and do not drift. | Max/95th deltas, consecutive violations, source selection state. |
| Time-counter monotonicity | The counter never goes backward; jumps beyond a guard window are detected as abnormal events. | Jump magnitude, direction, timestamp source, recovery mode indicator. |
| Calibration / delay compensation | Known fixed delays (port/cable) do not masquerade as “time error.” Only minimal compensation is needed and auditable. | Calibration enabled/disabled, applied offset value, change history. |
- TP-PPS: observe 1PPS vs internal counter boundary behavior (rollover, alignment).
- TP-PTP: compare hardware timestamp time to the same internal time counter at capture time.
- TP-ToD: verify ToD seconds transition matches the 1PPS boundary and never “double-ticks” or skips silently.
Diagram uses block elements and short labels only; all text is ≥18px for mobile readability.
Staying sane when GNSS dies: bounded drift and smooth recovery
Holdover is an operational mode with a drift budget, not a boolean “GNSS lost” flag. A resilient grandmaster defines entry/exit gates, limits error growth during reference loss, and returns via slew to avoid a phase hit. Redundancy is only useful when alarms, evidence, and switchover behavior are explicitly defined.
- Entry gate: reference quality below threshold for a sustained window, loss-of-lock, or anomaly/jump detection triggers a mode change.
- Drift budget: define maximum allowed time-error growth rate and absolute error envelope over time.
- During holdover: monitor time-error trend, frequency offset, temperature, and control word drift to explain behavior remotely.
When reference returns, the grandmaster may have accumulated an offset. Forcing a hard step can break continuity for consumers. A controlled slew limits the phase/frequency correction rate and provides an auditable recovery path: recovery mode, slew rate, and completion condition should be visible in telemetry and event logs.
| Redundancy item | What it protects | Required alarms/evidence |
|---|---|---|
| Dual GNSS | Reduces single-receiver or antenna-path failures; enables cross-check for trust scoring. | GNSS A/B delta alarms, lock state, quality score history, switchover reason. |
| Dual oscillator | Improves availability when one oscillator degrades; supports controlled handover. | Osc health, control range margin, holdover drift comparison, switch events. |
| Dual power (status only) | Maintains time services during partial power faults; prevents silent brownout timing errors. | Power-good inputs, undervoltage events, timestamp continuity flags. |
| Dual management | Ensures telemetry and logs remain reachable during link outages; supports remote audit. | OOB/in-band reachability, log export success, missing-telemetry counters. |
Writing switchover as a state machine prevents ambiguous behavior. Each state should have explicit entry conditions, key observables, and alarm severity so field behavior is predictable and auditable.
State labels are short and large (≥18px). The diagram stays readable on mobile and avoids dense text.
What must be logged to prove time quality
Time quality is only defensible when telemetry forms an evidence chain: output behavior (time error), root-cause indicators (reference/oscillator/control), and event ordering (what happened first). A single “offset” number is not proof.
- Time Quality (effects): time error/offset, RMS/p95/max over a fixed window, phase step events (magnitude + direction).
- Frequency & Control (causes): freq offset/drift, OCXO/CSAC control word (and percent-to-rail), disciplining mode/state.
- Reference Health (inputs): GNSS lock state, quality indicators (e.g., C/N0, SV count), reacquire counters.
- Clock Chain Health (path): PLL lock (jitter cleaner/clock tree), key-point temperature and temperature rate.
Event logs must support root-cause reconstruction: which signal degraded first, how drift evolved, and whether recovery stayed smooth. This requires both ordering (monotonic event sequencing) and context (state/source before and after).
- Ordering: monotonically increasing event sequence plus a monotonic timestamp alongside ToD.
- Correlation: state_before/state_after, source_before/source_after, and a compact cause code.
- Quantification: phase step magnitude, recovery mode (slew/step), and predicted drift budget at entry to holdover.
| Field / metric | Purpose | Alarm level | Suggested rate | Notes |
|---|---|---|---|---|
| time_error_ns + RMS/p95/max | Time quality | Warn → Alarm (trend) / Critical (max) | 1s (stats per 1–10 min window) | Fix the window length and keep it consistent. |
| freq_offset_ppb / drift trend | Root cause | Warn (trend) / Alarm (rapid change) | 1s | Correlate with holdover and temperature. |
| phase_step_ns (event) | Continuity | Alarm (step) / Critical (large step) | Event-driven | Log magnitude + direction + cause + state. |
| gnss_lock, reacquire_count | Input health | Warn (flaky) / Alarm (lost) | 1–5s | Track “first loss” time for traceability. |
| gnss_quality (C/N0, SV count) | Input trust | Warn (degrade) / Alarm (persist) | 1–5s | Use sustained thresholds (avoid flapping). |
| control_word + percent-to-rail | Osc margin | Warn (near rail) / Alarm (railed) | 1s | Near-rail indicates limited correction headroom. |
| pll_lock (cleaner/tree) | Path health | Alarm (unlock) | 1–5s | Unlock events must be logged with context. |
| temp_c + temp_rate | Env correlation | Warn (fast rate) / Alarm (over temp) | 5–10s | Temperature rate explains drift bursts. |
| state + source | Mode trace | Alarm (holdover) / Critical (unstable) | 1s + event-driven transitions | State changes are evidence anchors. |
| event_seq, tod_utc, mono_ms | Ordering | Critical if ordering breaks | Event-driven | Required to reconstruct causality. |
Large labels only (≥18px). Pipeline focuses on evidence: ordering, context snapshots, and exportability.
How to test a Time Hub like an engineer
Validation must be layered: lab (measure intrinsic stability), system (check observable consistency), and field (drills that stress holdover and recovery). Acceptance should be expressed as ns RMS, max phase step, and holdover drift (ns@T).
- Phase noise / jitter: measure oscillator and post-cleaner behavior using consistent integration bandwidth.
- ADEV (stability vs τ): capture short/medium/long τ regions to understand dominant noise regimes.
- Time error & PPS alignment: verify 1PPS boundary alignment and second-boundary consistency over fixed windows.
- Thermal drift: temperature chamber sweep, record temp rate vs time-error drift to build a correlation map.
- GNSS obscuration test: controlled signal degradation/occlusion to verify state transitions, alarms, and holdover entry behavior.
System testing focuses on what downstream devices can observe, not on their internal forwarding or timestamp models. The goal is consistency: when the time hub changes state or produces a controlled disturbance, downstream observed offset should change in a predictable, correlated way.
- Correlation window: align time hub event logs with downstream offset/alarms over the same time window.
- Controlled disturbance: trigger a known transition (degraded/holdover/recovery-slew) and verify downstream visibility.
- Consistency metrics: compare p95/max observed offset and step-event coincidence with time hub evidence logs.
- GNSS outage drill: verify holdover entry delay, alarm level, and drift stays inside the declared budget.
- Switchover drill: test redundant source selection and ensure reasons/magnitudes are logged.
- Recovery drill: confirm recovery uses slew (no phase hit) and produces a clean completion event.
- Log audit: pick a random interval and reconstruct “what happened first” using event_seq + context snapshots.
| Acceptance item | How to express it | What evidence to keep |
|---|---|---|
| Steady-state time quality | RMS(ns) + p95(ns) + max(ns) over a fixed window | Time-error series + aggregated stats + instrument settings |
| Continuity | Max phase step (ns) + step count per day | Event logs with magnitude, direction, cause, and state transitions |
| Holdover capability | Holdover drift budget = ns @ T (e.g., 10 min / 1 h / 6 h) | Outage drill traces + drift trend + temperature and control-word context |
| Thermal resilience | Worst-case drift under temp sweep + recovery behavior | Chamber profile + time error + temp rate + alarms |
Quick drift intuition for acceptance budgeting: 1 ppm ≈ 1000 ns/s. So drift_ns ≈ ppm × T_seconds × 1e3; for ppb, drift_ns ≈ ppb × T_seconds.
Three layers are separated to prevent scope creep: system tests emphasize observable correlation only.
H2-11 · IC / BOM selection checklist (criteria + part numbers)
The checklist below stays inside the grandmaster/time-hub box: reference intake → oscillator/discipline → jitter cleaning & distribution → trusted timestamp I/O. RF antenna array/anti-jam front-end design and boundary-clock forwarding behavior are intentionally excluded.
| Block | Hard criteria (measurable) | Example part numbers (not exhaustive) | Common pitfalls |
|---|---|---|---|
| GNSS timing receiver | multi-band/constellation; timing outputs (1PPS + freq); lock/SNR metrics; phase-step control on switchover; security features; interfaces (UART/SPI/I²C) |
u-blox ZED-F9T u-blox LEA-M8F Septentrio mosaic-T |
using nav-grade RX; weak lock evidence; uncontrolled phase step |
| OCXO / CSAC | Allan deviation at τ (short/mid); aging/day; warm-up; power; temp range; holdover target (ns over N hours) |
Rakon ROD2522S2H / ROD5242T1 (OCXO) Microchip CSAC-SA45S (e.g., 090-02984-003 / 090-02984-007) |
ignoring warm-up/aging; τ-mismatch vs KPI; thermal coupling |
| Jitter cleaner / DPLL | hitless/controlled switching; programmable loop BW; output phase noise/jitter; lock detect & alarms; 1PPS sync option |
ADI AD9545 Skyworks/SiLabs Si5345 TI LMK05318 ADI AD9528 (clock gen + PLL) |
wrong loop BW; leak-through band ignored; missing lock observability |
| Fanout / buffer / mux | additive jitter; skew; isolation; output standards (LVDS/LVPECL/LVCMOS); supply noise sensitivity |
ADI ADCLK948 TI CDCLVC1102 / CDCLVC11xx Si5338 |
“too many copies” without isolation; supply ripple converts to phase noise |
| HW timestamp NIC/PHY | IEEE 1588/802.1AS hardware timestamp; ToD/PPS alignment hooks; driver maturity; deterministic latency path |
Intel I210 Intel I225/I226 Marvell 88E1512 (PHY) Microchip LAN7430 |
timestamp in software path; unclear ToD alignment; asymmetry compensation ignored |
| TPM / secure boot | TPM 2.0 compliance; SPI/I²C; lifecycle/availability; measured boot chain; anti-rollback policy support |
Infineon SLB9670VQ2.0 Nuvoton NPCT75x |
“secure boot” without measurable attestation; weak key storage policy |
1) GNSS timing receiver (module/IC)
- u-blox ZED-F9T — multi-band timing module (commonly used for 5G timing receivers).
- u-blox LEA-M8F — GNSS-based time/frequency reference module (FTS use case).
- Septentrio mosaic-T — timing GNSS receiver module aimed at resilient timing infrastructure.
- Timing I/O: 1PPS quality (jitter, determinism), frequency outputs (10 MHz or programmable), ToD/epoch interface.
- Evidence: lock status, SNR/CN0, constellation health, holdover/discipline state reporting.
- Switchover behavior: documented phase-step control (how big can the step be; how it is bounded).
- Interfaces: host link (UART/SPI/I²C), GPIO for PPS/alarms; configuration persistence.
- Security options: receiver-side integrity features and spoofing indicators (kept at “capability” level).
- Nav-grade receiver substitution: stable positioning does not imply deterministic timing outputs; PPS may wander or step.
- No qualification gate: directly feeding GNSS into the servo without a “trust score” creates phase hits during marginal lock.
2) OCXO vs CSAC (holdover spend decision)
- Holdover OCXO: Rakon ROD2522S2H / ROD5242T1 (telecom holdover-focused OCXO families).
- CSAC: Microchip CSAC-SA45S ordering examples: 090-02984-003, 090-02984-007 (frequency options vary by ordering code).
- ADEV at τ buckets: choose τ windows that match outage/steering dynamics (short τ affects packet time stability; longer τ affects holdover drift).
- Aging & retrace: aging/day (or month), plus recovery behavior after temperature swings.
- Warm-up: time to “usable stability” and time to “final stability”; align with edge reboot expectations.
- Power/thermal: power draw vs enclosure thermal headroom; thermal gradients translate to frequency error.
- Environment: operating range and vibration sensitivity (edge racks are not always benign).
- τ-mismatch: buying “low phase noise” but failing mid/long τ stability → holdover drift dominates.
- Ignoring warm-up: cold-start drift can look like servo instability; root cause is oscillator settle time.
3) Jitter-cleaner PLL / DPLL (servo-friendly, observable switching)
- ADI AD9545 — dual digital PLL + 1PPS synchronizer, targeted at IEEE1588v2/SyncE class applications.
- Skyworks/SiLabs Si5345 — high-performance jitter attenuator with DSPLL and multi-output generation.
- TI LMK05318 — network synchronizer/jitter cleaner class device aimed at Ethernet-based timing.
- ADI AD9528 — clock generator with PLL stages (often used when multi-output clocking + jitter cleaning are needed).
- Switching behavior: hitless/controlled switching, phase continuity options, and bounded phase step.
- Loop bandwidth control: programmable BW to place the “clean/track” crossover where system needs it.
- Lock evidence: per-input validity, lock state, holdover state, alarms for phase/freq excursions.
- Output formats & count: 10/25/122.88/156.25/312.5 MHz style outputs as required by downstream clock tree.
- Telemetry hooks: readable phase error, frequency offset, loop status, temperature (if available).
- Leak-through band ignored: “jitter cleaned” in one band, but noise leaks at another band → output still fails time KPI.
- No observability: lock pin only (binary) without detailed metrics → field triage becomes guesswork.
4) Clock fanout / buffer / mux (distribution without self-inflicted noise)
- ADI ADCLK948 — high-speed fanout buffer class device (low-jitter distribution focus).
- TI CDCLVC1102 / CDCLVC11xx — low-jitter LVCMOS fan-out buffer family.
- SiLabs Si5338 — programmable clock generator usable as fanout/translation in some trees.
- Additive jitter: quantify what the buffer adds (it can only add noise, not remove it).
- Skew & determinism: output-to-output skew and temperature drift of skew (important for multi-port alignment).
- Isolation strategy: mux/isolators to prevent one noisy domain from polluting the master clock domain.
- Output standards: LVDS/LVPECL/LVCMOS compatibility with PHY/NIC/PLL input requirements.
- Supply sensitivity: PSRR and layout tolerance; supply noise easily turns into phase noise here.
- “More outputs” without partitioning: one buffer fans out everything, then crosstalk and supply bounce dominate.
- Format mismatch: casual level translation introduces edge degradation and jitter; treat as a spec item.
5) Hardware timestamp engine (NIC / PHY / MAC)
- Intel I210 — Ethernet controller family with hardware-based IEEE 1588/802.1AS timestamping.
- Intel I225 / I226 — controller family overview highlights IEEE 1588/802.1AS time-stamping capability.
- Marvell Alaska PHY 88E1512 — PHY family supporting SyncE and PTP time stamping.
- Microchip LAN7430 — PCIe-to-Ethernet bridge with integrated PHY/MAC supporting IEEE 1588 PTP.
- True HW timestamp: confirm ingress/egress timestamp insertion is in silicon, not the driver stack.
- ToD/PPS alignment hooks: ability to align the time counter to 1PPS and detect second-boundary consistency.
- Delay calibration support: explicit mechanisms for fixed delays / asymmetry (kept minimal; no network forwarding model).
- Telemetry: counters/events that prove monotonicity, jump detection, and timestamp validity.
- Software timestamp fallback: throughput looks fine, but timing collapses under CPU load.
- Unproven ToD chain: PTP clock and ToD/PPS disagree silently; requires explicit cross-check logic.
6) Secure root for “trustworthy time” (TPM / measured boot)
- Infineon OPTIGA TPM SLB9670VQ2.0 — TPM 2.0 device class with SPI interface options.
- Nuvoton SafeKeeper NPCT75x — TPM 2.0 family options for embedded platforms.
- Measured boot: boot chain produces attestable measurements; firmware rollback control is explicit.
- Key custody: time/identity keys never leave secure boundary unwrapped; policy is enforceable.
- Lifecycle: availability, temperature grade, and manufacturing provisioning plan.
- Security checkbox: “secure boot supported” but no measurable attestation output in the deployed product.
- Weak provisioning plan: keys and policies are handled manually; repeatability and audit trail degrade.
H2-12 · FAQs (Edge Grandmaster / Time Hub)
Focus: time source + holdover + jitter-cleaning + trustworthy timestamps + evidence logs. Network forwarding internals (Boundary Clock / switch queueing) are intentionally excluded.