Frequency & Phase for Active Filters and Signal Conditioning
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Frequency & Phase is about making filters “usable,” not just “correct”: phase margin, Q sensitivity, and group delay decide ringing, settling, and channel timing. This page turns those specs into practical guardbands and verification steps so amplitude targets still hold on real boards and across builds.
Scope & boundary: what “Frequency & Phase” owns
This page turns magnitude/phase plots into design targets, guardbands, and verification steps. It focuses on time-domain behavior and multi-build consistency—without expanding into topology derivations or unrelated performance domains.
What this page delivers (4 outputs)
1) Stability targets
Translate GBW and phase margin into limits for ringing, overshoot, and settling—plus a verification template (step + sweep).
2) Consistency targets
Quantify how Q moves with tolerance and temperature, and define guardbands so peaks/notches do not collapse across builds.
3) Time-domain integrity
Use group delay and phase linearity to protect pulse/step fidelity, envelope timing, and multi-channel phase alignment.
4) Measurement & production hooks
Provide reliable measurement workflows (probe/fixture-aware) and a minimal pass/fail schema for lab bring-up and production sampling.
Out of scope (link out only; no deep dives here)
- Noise theory and full noise budgeting (handled by the Noise page).
- Distortion mechanisms and THD/SFDR optimization (handled by Linearity & Distortion).
- Full transfer-function derivations and component-ratio synthesis for each topology (handled by each Topology subpage).
- DSP equalization algorithms beyond pass/fail requirements (handled by the all-pass/equalizer subpage).
Boundary table: question → where to go
| If the question is about… | Go to… |
|---|---|
| en/in, 1/f corner, integrated noise vs source impedance | Noise |
| THD/SFDR vs swing, load distortion, output drive linearity | Linearity & Distortion |
| Sallen-Key / MFB / SVF / biquad synthesis and component ratios | Topology subpages |
| ADC/DAC pairing details (fc:fs tradeoffs, image/recon specifics) | Anti-alias / Reconstruction |
Cross-topic content should stay at the “one-sentence mapping + link” level to prevent overlap between sibling pages.
Spec map: how to read datasheets and set targets
Specs become useful only when tied to observable symptoms and verification methods. Use the fields below to translate “system behavior” into frequency/phase targets that survive tolerance, temperature, and real fixtures.
A) Spec dictionary (ordered by design decisions)
Step 1 — Define frequency intent
- fc / f0: set the transition point for bandwidth, alias/settle tradeoffs.
- Stopband target: set image/adjacent rejection that controls leakage into the passband.
- Order / stage plan: decide how steepness and phase behavior are distributed across stages.
Step 2 — Define stability intent
- GBW: must support the chosen fc/f0 and Q without phase lag dominating the loop.
- Phase margin (PM): sets the ringing/overshoot envelope and recovery time.
- Closed-loop BW (under the actual gain/load): prevents “datasheet-good, board-bad” behavior.
Step 3 — Define time-domain intent
- Group delay (τg) ripple: controls pulse smear, step tailing, and envelope timing error.
- Phase ripple: captures “phase non-ideality” even when magnitude meets limits.
- Settling & overshoot: the user-visible time response that must be explicitly bounded.
Step 4 — Define multi-build / multi-channel intent
- Q vs tolerance: limits peaking/notch depth drift across RC spread and temperature.
- Channel-to-channel phase mismatch (Δφch): protects beamforming, imaging, synchronous sampling, and coherent demod.
B) Where targets come from (system behavior → spec fields)
Overshoot / ringing constraints
If the waveform must not ring beyond a limit, convert the constraint into a phase margin target and verify with a step test under the real load and probe setup.
Settling / latency constraints
If the system must settle within a time window, set limits on τg ripple and allocate phase lag across stages so the cumulative delay stays within budget.
Coherent multi-channel constraints
If channels must align, express the requirement as Δφch (phase mismatch) versus frequency across the passband, then validate with a two-channel sweep using a shared reference.
Production consistency constraints
If the response must remain stable across builds, set guardbands for Q sensitivity and define tolerance classes and temperature points for verification sampling.
Each spec field must have an associated measurement method and a pass/fail criterion; otherwise it is not a controllable requirement.
C) What to ask vendors for (missing datasheet conditions)
Loop data (amplifier behavior)
- AOL vs frequency (or a usable macro-model).
- Phase margin conditions (gain, load, output swing, supply, temperature).
- Closed-loop BW under the intended gain and common operating loads.
Load & stability envelope
- Stability versus capacitive load and recommended isolation resistance ranges.
- Output drive limits versus frequency for realistic signal amplitudes.
- For FDAs: VOCM loop notes that affect phase and settling.
Tolerance & drift behavior
- Recommended RC tolerance classes for high-Q and deep-notch designs.
- Temperature drift expectations and any matching guidance.
- Any calibration hook support (trim, digital steps, EEPROM parameters).
D) Target fields template (copy into a design review)
Filter intent:
– fc/f0 = ________ Order/stages = ________ Stopband target = ________
Stability intent:
– GBW guardband = ________ Phase margin target = ________
– Conditions: gain = ___ load = ___ Cload = ___ swing = ___ temp = ___
Time-domain intent:
– Overshoot max = ________ Settling to ___% within ________
– Group delay ripple (τg) max = ________ Phase ripple max = ________
Consistency intent:
– Q sensitivity guardband = ________ RC tolerance class = ________
– Channel phase mismatch (Δφch) max @ passband = ________
Verification:
– Sweep method = ________ Step test setup = ________
– Fixture/probe notes (de-embed) = ________
Filling this template forces every requirement to be measurable and prevents “spec drift” between design, layout, and validation.
From Bode to time-domain: why phase dominates “usable performance”
Magnitude response alone does not guarantee usable behavior. Phase margin, Q, and group delay determine whether steps, pulses, and envelopes meet settling and alignment requirements under real loads and tolerances.
A) Common failures when magnitude looks correct
Step input → ringing / overshoot
A flat passband can still ring if phase margin is insufficient. The time window for control loops, sampling, and limit detection becomes the true constraint.
Pulse input → tailing / smear
Pulse fidelity depends on phase linearity. Group-delay ripple spreads energy over time even when amplitude specs are met.
Envelope signals → shape distortion
Non-flat group delay shifts and distorts envelopes, breaking timing-based decisions (gating, thresholds, coherent demod) even without visible oscillation.
B) Three mappings that separate root causes
PM ↓ → ringing and slow recovery ↑
Likely symptom: multi-cycle ringing after a step, decay is slow, settling window is missed.
Quick check: change probe/fixture loading or add output isolation—large behavior change indicates margin-limited dynamics.
Interpretation: stability margin has priority; reduce lag sources before pursuing higher selectivity.
Quick check: change probe/fixture loading or add output isolation—large behavior change indicates margin-limited dynamics.
Interpretation: stability margin has priority; reduce lag sources before pursuing higher selectivity.
Q ↑ → peaking/overshoot ↑ (tolerance sensitivity ↑)
Likely symptom: peaking near the corner and larger overshoot, but behavior remains repeatable under controlled loading.
Quick check: swap to tighter-matched RC parts or test at temperature extremes—spread grows when Q is tolerance-limited.
Interpretation: this is a design-choice + consistency risk; guardband and matching are the control knobs.
Quick check: swap to tighter-matched RC parts or test at temperature extremes—spread grows when Q is tolerance-limited.
Interpretation: this is a design-choice + consistency risk; guardband and matching are the control knobs.
τg non-flat → waveform distortion / pulse tailing
Likely symptom: pulse smears or envelope shifts without obvious high-frequency oscillation.
Quick check: compare phase slope (or group delay) across the passband; ripple correlates with waveform tailing.
Interpretation: time-domain integrity dominates; allocate selectivity across stages or use phase equalization when required.
Quick check: compare phase slope (or group delay) across the passband; ripple correlates with waveform tailing.
Interpretation: time-domain integrity dominates; allocate selectivity across stages or use phase equalization when required.
C) Engineering priority rules (what to protect first)
Waveform fidelity is primary
Protect τg flatness and adequate phase margin first. Distribute selectivity across stages rather than forcing a single high-Q stage.
Selectivity is primary
Protect stability margin first, then allocate corner peaking. Use phase-equalization only when time-domain requirements are explicit.
Production consistency is primary
Protect Q vs tolerance and channel phase alignment across temperature. Favor matching networks and measurable guardbands over “typical-only” tuning.
D) Pass/fail language (turn intuition into measurable limits)
- Step response: overshoot < X%, ringing decays below Y% within T under real load and probe conditions.
- Group delay: τg ripple < R% across the passband (R set by waveform and latency budgets).
- Channel alignment: Δφch < A° across the passband (A set by coherence/error budgets).
- Stability: no sustained oscillation; ringing cycle count and decay rate remain within the defined observation window.
GBW in active filters: minimum rules, error budget, and hidden poles
GBW is not a “pass/fail” number. Treat it as a stability and accuracy budget: finite loop gain shifts fc and Q, adds phase lag, and reduces usable settling margin under tolerance, loading, and parasitics.
A) Causal chain (how finite GBW shows up on the bench)
Finite loop gain → parameter drift
As frequency approaches the amplifier’s unity gain region, closed-loop behavior deviates from the ideal model. The filter exhibits fc shift,
Q shift, and additional phase lag.
Drift → usable bandwidth shrinks
Even when the transfer function “looks correct” at small signal, the time-domain window is consumed by ringing and slow recovery. The usable region is set by the
worst-case load, not the typical curve.
Drift grows with hidden poles
Extra poles from ESD/clamps, input capacitance, output load capacitance, VOCM loops, and PCB parasitics add phase lag. The effective margin can collapse without
any change in the nominal design equations.
B) Guardband tiers (choose by risk, not by “just enough”)
Conservative tier
Use when Q is high, deep notches are required, temperature range is wide, load is variable,
or field calibration is limited. Design for margin under worst-case conditions and verify with stressed fixtures.
Balanced tier
Use when Q is moderate, RC matching is controlled, and the load envelope is known. Maintain explicit stability/settling limits, and allocate selectivity across stages
rather than forcing a single stage to absorb all requirements.
Aggressive tier
Use only when Q is low, the load is fixed, and adjustment/calibration hooks exist. The design still needs a measurable phase-margin and settling guardband under the
actual probe/fixture setup.
Decision rule: if phase margin and settling are primary requirements, treat GBW as a margin budget, not a bandwidth checkbox.
C) Error budget (split into measurable outcomes)
1) Frequency-domain drift
Verify fc and Q against targets with a sweep under the real load. Watch for corner shifts and peaking changes that imply insufficient loop gain.
2) Phase lag growth
Track phase slope across the passband. If phase becomes more lagging than expected, usable margin is being consumed by hidden poles and insufficient GBW.
3) Time-domain degradation
Validate overshoot, ringing cycles, and settling time with a step test. “Rings only on the board” usually indicates phase-margin collapse due to loading/parasitics.
D) Hidden pole sources (what to audit before blaming the topology)
Input capacitance / ESD / clamps
Adds extra RC poles at sensitive nodes. Quick isolation: compare behavior with/without protection networks or with lower-capacitance alternatives.
Output impedance + capacitive load
Creates a load pole that consumes phase margin. Quick isolation: add or tune an output isolation resistor and re-measure settling and peaking.
FDA VOCM loop dynamics
Common-mode control can introduce additional dynamics and slow recovery. Quick isolation: observe VOCM-related steps and evaluate symmetry/loading conditions.
PCB parasitics and return paths
Trace inductance and broken returns create unintended poles/zeros. Quick isolation: reduce loop area, shorten sensitive nodes, and re-check phase/settling.
E) Boundary note (topology pages own synthesis; this page owns GBW margin)
This section does not derive Sallen-Key/MFB transfer functions. It only flags which implementations tend to consume more loop gain and phase margin, then links out to the corresponding topology subpages for synthesis details.
Phase margin & stability: how filters oscillate in real boards
Stability problems are rarely visible on the datasheet curve alone. The real loop is shaped by probe/fixture loading, output capacitance, return paths, and common-mode control dynamics. The goal is to debug instability as a repeatable workflow.
A) Engineering definition (what phase margin means on a board)
Phase margin is measured at the gain crossover
Phase margin is the remaining phase distance to −180° at the gain crossover where the loop magnitude reaches unity.
When loading or parasitics shift the crossover frequency, the effective phase margin can collapse without any schematic change.
“Works on the bench” is not the criterion
A stable waveform under one probe or fixture does not prove margin. Stability must be verified under the worst-case load and
the actual measurement setup used in validation and production.
B) Common triggers (bench OK → board oscillates) and fast isolation
Capacitive load (Cload) + output impedance
Symptom: ringing increases or oscillation appears when connecting an ADC input, cable, or probe.
Quick check: change Cload or add a temporary output isolation resistor; large behavior shifts imply margin is load-limited.
Action: tune isolation (value + placement) while watching settling and bandwidth tradeoffs.
Quick check: change Cload or add a temporary output isolation resistor; large behavior shifts imply margin is load-limited.
Action: tune isolation (value + placement) while watching settling and bandwidth tradeoffs.
Probe / fixture loading
Symptom: oscillation depends on the test setup (ground clip vs spring, cable routing, fixture variants).
Quick check: compare short-ground probing vs long ground leads; strong sensitivity indicates hidden poles/zeros from the measurement chain.
Action: include fixture loading in the stability budget and verification plan.
Quick check: compare short-ground probing vs long ground leads; strong sensitivity indicates hidden poles/zeros from the measurement chain.
Action: include fixture loading in the stability budget and verification plan.
Missing / misplaced output isolation
Symptom: small load changes switch behavior from “quiet” to “rings hard”.
Quick check: insert isolation at the driver output; improved decay confirms output–load interaction as the trigger.
Action: place isolation close to the driver, keep the sensitive node short, re-check across load corners.
Quick check: insert isolation at the driver output; improved decay confirms output–load interaction as the trigger.
Action: place isolation close to the driver, keep the sensitive node short, re-check across load corners.
Return-path breaks and loop area growth
Symptom: the same schematic behaves differently on different boards or different test points.
Quick check: compare near/far measurement points; worsening near a sensitive return break suggests parasitic inductance dominates.
Action: shrink loop area on sensitive nodes and enforce continuous returns before tuning component values.
Quick check: compare near/far measurement points; worsening near a sensitive return break suggests parasitic inductance dominates.
Action: shrink loop area on sensitive nodes and enforce continuous returns before tuning component values.
Common-mode loop dynamics (FDA VOCM)
Symptom: differential output “looks fine” but common-mode recovery is slow or rings, contaminating settling.
Quick check: observe response to a common-mode step or change VOCM network/loading; sensitivity suggests VOCM loop interaction.
Action: validate common-mode behavior explicitly under the real differential load.
Quick check: observe response to a common-mode step or change VOCM network/loading; sensitivity suggests VOCM loop interaction.
Action: validate common-mode behavior explicitly under the real differential load.
C) “Unstable” vs “high-Q”: fast separation using step and sweep
High-Q behavior (controlled by design + tolerance)
- Sweep shows predictable peaking near the corner; behavior is repeatable under the same load.
- Step overshoot may increase, but decay remains consistent and does not “switch states” with small fixture changes.
- Spread grows mainly with component ratio errors and temperature drift.
Margin-limited instability (uncontrolled by small-signal equations)
- Small probe/load changes produce large differences (stable ↔ rings ↔ oscillates).
- Step response shows many ringing cycles, slow decay, or sustained oscillation.
- Sweep can show sharp anomalies near crossover that shift with fixture conditions.
Practical rule: if a small fixture change dramatically alters ringing, treat the issue as phase-margin collapse before adjusting Q targets.
D) Recovery time: stable can still be unusable when margin is small
Margin consumes the settling window
A loop may remain stable yet ring long enough to violate sampling windows, gating logic, or multi-channel alignment. Time-domain budgets should be set in
cycles, decay, and settling-to-ε under worst-case load.
E) Pass/fail templates (copyable stability criteria)
- No sustained oscillation under worst-case load and the production-representative fixture.
- Ringing cycles ≤ N within observation window T after a defined step amplitude.
- Decay below Y% of final value within T (measured at the same node/fixture across builds).
- Sweep sanity: no sharp crossover anomaly that shifts strongly with probe/fixture changes.
Q vs tolerance: sensitivity, drift, and “why my notch depth collapses”
High Q and deep notches are ratio-driven outcomes. Small ratio errors, temperature gradients, and aging effects can spread peaking and collapse notch depth. The goal is to turn tolerance into controllable design and production knobs.
A) Three layers of tolerance impact (what spreads, and why)
1) Absolute RC error → fc drifts
Absolute value errors shift corner/center frequency. The response can remain “clean” yet miss the intended frequency placement.
2) Ratio error → Q / peaking / notch depth spreads
Ratio accuracy dominates Q and cancellation depth. Deep notches depend on tight amplitude/phase matching; small mismatch leaves large residual leakage.
3) Tempco / aging / gradients → long-term drift
Even if a unit passes at room temperature, gradients and aging expand channel mismatch and depth loss across temperature and time.
B) Why notch depth collapses (the ratio-driven nature of cancellation)
- Notch depth is created by cancellation, not by absolute component accuracy alone.
- Ratio error shifts the cancellation point and creates residual amplitude/phase mismatch, leaving measurable leakage at the notch frequency.
- Multi-stage chains can amplify small mismatch into large depth spread, especially for narrow notches and high-Q stages.
C) Passive controls (win first without calibration)
Use stable dielectrics when temperature is a spec
Prefer low-drift capacitor types and controlled tempco resistors when fc/phase alignment must hold across temperature.
Ratio accuracy benefits from matched networks
Matched resistor/capacitor arrays reduce ratio spread and preserve notch depth and Q consistency across builds.
Thermal coupling matters for multi-channel alignment
Place ratio-critical components close together with symmetric routing to minimize gradients that create channel-to-channel drift in depth and phase.
D) When trim / self-cal becomes the right tool
Trigger conditions (use calibration as a gate, not a default)
- Notch depth or phase alignment must hold across wide temperature and passive matching cannot guarantee yield.
- Injection measurement or loopback is available, and parameters can be stored (EEPROM or digital registers).
- Field re-calibration or temperature-point re-trim is part of the service plan.
Keep the boundary clear
This section lists which frequency/phase parameters to trim and how to define pass criteria. Production data schemas and binning belong to the
production reporting page.
E) What to calibrate (frequency/phase items only) and how to accept
Calibrate these items
- fc: place the corner/center frequency at the intended target.
- Q / depth: control peaking or notch depth spread across builds.
- Phase / τg: enforce channel alignment or waveform integrity across the passband.
Pass criteria templates (fill X/Y/A/R from system budgets)
- Notch depth: ≥ D dB at fnotch across temperature corners.
- Frequency placement: |fc error| ≤ E% across temperature corners.
- Channel phase: Δφch ≤ A° across the passband.
- Group delay: τg ripple ≤ R% across the passband.
Group delay & phase linearity: when “flat magnitude” is not enough
A flat magnitude response can still distort waveforms. If different frequency components arrive at different times, pulse shape, envelope fidelity, and time-of-flight accuracy degrade even when the amplitude plot looks “perfect”.
A) Group delay intuition (phase slope becomes timing error)
Group delay is the timing view of phase
Group delay describes how fast phase changes with frequency. When group delay is flat, frequency components align in time and
the waveform keeps its shape. When group delay ripples, the waveform develops pre-/post-ringing, tails, or envelope warping.
Phase linearity is a time-domain budget
Phase linearity should be treated like a latency and shape budget: it determines how much time-skew is injected across the passband,
not only how “smooth” the phase curve looks.
B) When group delay is a KPI (common engineering triggers)
Pulse / step measurements
Shape fidelity is the goal. Group-delay ripple creates tails and ringing that look like “sensor physics” but are filter timing artifacts.
Envelope detection / thresholds
Ripple moves energy in time, shifting peaks and corrupting fast envelope decisions, especially near cutoffs or narrowband shaping.
ToF / ultrasound / correlation peaks
Timing alignment and peak location depend on phase consistency across the band. Small ripple can bias distance/arrival estimates.
Low-latency control loops
Delay acts like additional phase lag. If latency is budgeted, group delay must be constrained as a first-class requirement.
Practical rule: when waveform shape, peak timing, or latency is a spec, passband group-delay ripple must be specified—not only magnitude ripple.
C) Prototype tendencies (conclusion-only guidance)
Waveform-first
Bessel-type responses tend to produce flatter group delay and preserve transient shape, at the cost of weaker selectivity.
Balanced
Butterworth-type responses are often a practical middle ground: moderate selectivity with moderate group-delay variation.
Selectivity-first
Chebyshev/Elliptic-type responses prioritize steep transitions and strong stopband control, often with larger group-delay ripple.
Decision framing: choose by waveform fidelity versus selectivity. If both are required, consider phase equalization rather than relying on magnitude shaping alone.
D) Spec templates (measurable, acceptance-ready)
Group delay ripple (passband)
Define the passband and limit ripple: max(τg) − min(τg) ≤ R (ns or % of nominal) with fixed fixture and measurement method.
Phase deviation from a best-fit line
Limit phase nonlinearity across the same band: deviation ≤ P degrees, using consistent frequency points and reference definition.
Time-domain residual (shape-based)
Constrain tail/ringing energy: within window T, residual ≤ Y% of peak (defined stimulus and windowing).
E) When to add phase equalization (all-pass) — and how to accept it
Use it when magnitude is done but timing fails
If amplitude meets requirements but group-delay ripple or phase nonlinearity breaks waveform/peak-timing metrics, a phase equalizer can flatten timing
without redesigning the main magnitude shaping stages.
Acceptance checklist
- Group-delay ripple and phase deviation meet the same passband targets after equalization.
- No unacceptable noise/distortion or stability regression under real loading.
- Calibration and tolerance plan keeps equalization stable across temperature and production spread.
Cascaded stages & multi-channel phase matching: practical rules
In cascaded chains, phase and group delay accumulate stage by stage. In multi-channel systems, small mismatch sources compound into visible alignment errors. The focus here is practical control: how to partition stages and preserve channel consistency.
A) What cascades do to phase and delay (the accumulation reality)
Each stage contributes timing
Phase rotation and group delay are stage contributions that add across cascades. A single stage that looks acceptable can become problematic once multiple
stages stack delay ripple in the same critical band.
Verification must be staged
Cascaded systems are easier to debug when each stage has defined measurement nodes and acceptance checks, rather than only end-to-end validation.
B) Why split high order into biquads (engineering reasons)
- Implementation control: stage-by-stage tuning and replacement without redesigning the whole chain.
- Debug control: each biquad can be validated for stability, Q spread, and timing contribution.
- Tolerance control: ratio-sensitive components can be grouped and matched per stage.
C) Multi-channel phase matching: dominant sources and controls
Lot / component spread
Use matched networks and stage-level ratio grouping to reduce channel-to-channel drift in Q and timing. Avoid uncontrolled substitutions in ratio-critical parts.
Thermal gradients
Layout symmetry and thermal coupling reduce phase drift caused by temperature differences. Place matched sets close together and away from localized hot spots.
Parasitic asymmetry
Unequal routing, returns, and loading create timing mismatches even with identical values. Mirror critical nodes and keep channel geometry consistent.
D) Matching sets and measurement nodes (make phase controllable)
Match by stage, not only by channel
Treat each stage as a ratio-critical module. Keep its key components in a single matched set and replicate that set across channels using the same value family and layout style.
Add consistent observation points
Define stage outputs as standard test nodes. Stage-level checks isolate whether mismatch is introduced early, amplified in later stages, or created by the load interface.
E) Partitioning strategy (where to place phase-sensitive stages)
If alignment is an ADC-front requirement
Place the most phase-sensitive shaping close to the final load interface so later routing, connectors, and loading do not reintroduce mismatched poles and delay ripple.
If early stages must protect dynamic range
Apply required anti-alias or interference-limiting early, then reserve phase-linear shaping and equalization near the end where consistency can be controlled.
Guiding principle
Put the most alignment-critical stages where the environment is most repeatable: same load, same returns, same thermal conditions, and symmetric geometry.
Fully-differential phase pitfalls: VOCM loops and CM→DM coupling
Differential chains can fail phase and stability targets without obvious magnitude problems. The usual culprits are the VOCM/CMFB loop dynamics and common-mode to differential-mode conversion caused by asymmetry in components, routing, returns, and measurement.
A) Differential phase errors: three dominant families
Loop-related (VOCM / CMFB dynamics)
The common-mode control loop has its own poles/zeros and phase margin. Output common-mode loading can inject extra lag and slow recovery,
degrading usable phase behavior even when differential magnitude looks acceptable.
Symmetry-related (unbalanced impedances)
Small R/C, parasitic-C, or routing differences convert common-mode energy into differential error. The result is frequency-dependent phase mismatch and
group-delay skew between sides or channels.
Measurement-related (asymmetric probing)
Differential phase is extremely sensitive to probe capacitance, ground inductance, fixture delay, and unequal channel paths. A “bad” phase plot may be
the measurement setup, not the DUT.
B) VOCM/CMFB loop: why “common-mode control” changes phase and recovery
Output common-mode stability is a real loop
A VOCM/CMFB loop is not a DC setting only. It must remain stable under the actual output common-mode impedance created by filters, loads, and parasitics.
Extra loading can add poles that reduce phase margin and increase settling time after disturbances.
What it looks like on the bench
- Common-mode steps cause long recovery even when DC range is OK.
- Phase mismatch grows with frequency and changes with loading or probing.
- “Stable” amplitude plots hide timing errors that break alignment requirements.
Engineering stance: validate common-mode loop behavior as part of phase verification, not as a secondary detail.
C) CM→DM conversion paths (what to check first)
1) Asymmetric RC or parasitic-C
Even if nominal values match, unequal parasitic capacitance or different return-to-ground geometry converts common-mode content into differential error.
Quick check: swap L/R components or probe channels and observe whether the error “moves” with the swap.
2) Return discontinuity and loop geometry
Split planes, return detours, and unequal loop area create frequency-dependent imbalance. Quick check: measure phase mismatch before and after adding
short, symmetric return paths near the sensitive nodes.
3) Asymmetric load and protection
ESD/TVS placement, clamp paths, or unequal ADC input networks can add different poles per side. Quick check: isolate the load (high-Z) and see whether
mismatch collapses, then reintroduce load with controlled symmetry.
4) Asymmetric probing and fixtures
Probe capacitance and fixture delay often dominate high-frequency phase plots. Quick check: use matched probes/cables and compare channel-to-channel
delay with a known-through baseline before blaming the DUT.
D) Distinguish “high Q” from “lost phase margin” in differential chains
High Q (intended)
Peaking is consistent across both sides and does not “move” with probing or swapping. The waveform changes are stable and repeatable under controlled loading.
Lost margin / CM→DM artifacts (unintended)
Phase mismatch changes with cable/probe, load, or common-mode conditions. Common-mode steps trigger long recovery or ringing that varies across channels.
E) Acceptance templates (phase matching + CM disturbance recovery)
Channel phase mismatch vs frequency
Specify Δφ(f) across the passband: Δφ ≤ Y° for 0…BW with defined fixture, probes, and reference alignment.
Group delay mismatch
Constrain timing skew: Δτg ≤ Z (ns or % of nominal) over 0…BW using the same estimation method and frequency grid.
Common-mode disturbance recovery
Apply a defined common-mode step (or CM injection) and require the differential output to return within ±E in T.
Record the same test under worst-case load and probing.
Measurement & verification: how to measure phase and group delay without lying
Phase and group delay measurements are only as good as the reference path. Probes, cables, fixtures, and impedance assumptions can dominate the result. A repeatable workflow must define baseline, de-embedding, and acceptance criteria under controlled conditions.
A) First decision: measure the DUT, or the DUT + interface
Interface is part of the timing
For phase and group delay, the fixture and probing often contribute as much as the filter. The verification plan must explicitly decide whether the
goal is “DUT intrinsic” or “system-level including load and routing”.
Baseline first
Always capture a through/baseline measurement using the same cables, probes, and fixture geometry. Treat that baseline as the reference for subtraction
or de-embedding.
B) Sweep phase measurement: three practical tool routes
VNA / network analyzer
Best for accurate phase and mature calibration. Requires defined terminations, fixture control, and consistent calibration method.
Audio analyzer (low frequency)
Strong for audio/instrument bands. Phase integrity still depends on fixture symmetry and well-defined source/load impedance.
Dual-channel FFT (transfer function)
Fast and accessible for channel-to-channel phase comparison. Must control synchronization, reference path delay, windowing, and averaging for repeatability.
C) Group delay workflows (actionable, non-academic)
Method 1: phase slope extraction
- Measure phase vs frequency with a fixed reference path.
- Unwrap phase consistently and select the passband window.
- Compute slope via fitting or local differences to obtain τg.
Method 2: chirp / MLS-based estimation (flow-level)
- Stimulate with a broadband known sequence (chirp or MLS).
- Capture response, derive impulse response or transfer function.
- Extract phase and τg with consistent windowing and bandwidth limits.
D) Reference, fixture delay, and de-embedding (avoid fake phase)
Match the reference path
Use equal-length cables, identical probes, and symmetric connections. A reference delay mismatch becomes a linear phase term that looks like DUT delay.
Baseline subtraction (through)
Measure a known-through baseline using the same fixture and subtract it from DUT results. This isolates fixture delay and the probe-induced phase bias.
E) Measurement traps checklist (and quick sanity checks)
Probe adds capacitance
Quick check: switch probe type or add a known isolation resistor and see whether phase and delay curves shift significantly at high frequency.
Ground lead inductance
Quick check: shorten the ground connection and observe whether the phase ripple collapses. If it does, the setup is dominating the result.
Source / load impedance drift
Quick check: repeat measurements at a second known termination. If the curve changes disproportionately, the DUT is being measured under a new pole/zero environment.
Windowing / synchronization artifacts
Quick check: change averaging and window settings. If phase noise changes but mean phase slope shifts, the estimation method is contributing bias.
F) Pass criteria templates (conditions must be explicit)
Phase margin guardband
Require PM ≥ guardband under worst-case load and probing. Guardband is chosen by system risk tier and recovery/settling tolerance.
Group delay ripple
Require τg ripple < X% across 0…BW. X is set by allowable waveform distortion and peak-timing error budget.
Channel phase mismatch
Require Δφ < Y° @ BW with defined reference alignment, frequency grid, fixture symmetry, and averaging settings.
Every pass/fail statement must include: fixture geometry, probes/cables, terminations, frequency points, averaging/window settings, and the baseline method.
Engineering checklist: design review + test plan + guardbands
This checklist turns frequency/phase requirements into reviewable fields, repeatable verification steps, and defensible guardbands. It is intentionally phase-centric: fc/Q/phase margin/group delay/phase matching.
A) Targets & budgets (required fields)
- fc / f0: target + tolerance window (±%) + passband definition (0…BW).
- Q / peaking: target Q (or peak limit in dB) + allowed drift across tolerance/temperature.
- Phase margin (PM): minimum PM guardband + explicit load condition (R, C, ADC input network, cable).
- Group delay ripple: τg ripple limit over 0…BW + extraction method (phase-slope or chirp/MLS).
- Channel phase mismatch: Δφ limit at BW (and/or curve limit over 0…BW) + reference alignment method.
- Latency budget (if relevant): max acceptable delay for control/ToF/transients.
Every field above must include measurement conditions (fixture, probes/cables, terminations, frequency grid, averaging/window settings).
B) Parts & tolerance control (phase repeatability)
Capacitor dielectric and stability
- Use NP0/C0G for frequency/phase-critical poles and matching nodes.
- Keep high-K ceramics away from timing-critical locations unless behavior is characterized.
- Place paired components in the same thermal zone to reduce drift-induced mismatch.
Ratio matching and arrays
- Use resistor arrays for ratio-critical Q and phase matching (shared substrate improves tracking).
- Use capacitor arrays or matched footprints for L/R symmetry.
- Separate “absolute tolerance” (fc drift) from “ratio tolerance” (Q/phase mismatch).
Serviceable trim hooks (optional)
- Reserve small “padding” positions to nudge fc/Q without rerouting.
- Reserve jumpers to change isolation/termination and test alternate stability states.
- When using programmable coefficients, record versions and calibration conditions.
C) Stability protection (prevent margin collapse on real boards)
Output isolation and capacitive load boundary
- Define maximum stable capacitive load (includes probe/fixture capacitance).
- Use an isolation resistor (Riso) whenever the load looks capacitive or cable-driven.
- Verify stability with the worst-case load and the intended probing method.
Differential measurement discipline
- Use matched probes/cables for differential phase work.
- Capture a through baseline with the same fixture to control reference delay.
- Document fixture geometry and terminations in every phase/τg report.
FDA VOCM/CMFB awareness (differential chains)
- Treat VOCM dynamics as part of stability: common-mode loading can add hidden poles.
- Include a common-mode disturbance recovery check in the verification plan.
- Keep symmetry in components and returns to minimize CM→DM conversion.
D) Layout review checklist (phase integrity)
- Symmetry: matched lengths, vias, and reference layers on +/− paths and across channels.
- Return continuity: avoid plane splits and return detours under sensitive loops.
- Smallest loops: keep high-impedance and filter nodes compact; minimize loop area.
- Decoupling symmetry: mirror placement and return paths for critical rails and VOCM networks.
- Protection symmetry: ESD/TVS/clamp placement and returns must be symmetric for differential paths.
- Thermal tracking: place matched R/C in the same thermal environment; avoid heat gradients across pairs.
E) Verification plan (repeatable, production-friendly)
Bench: sweep + step
- Sweep: magnitude, phase, τg, and channel Δφ over 0…BW.
- Step: overshoot/ringing/settling time tied to PM guardband targets.
- Baseline: through measurement with identical fixture/probing for reference alignment.
Temperature + sampling
- Temp: cold/room/hot at minimum; record fc, Q, τg ripple, and Δφ drift.
- Lot sampling: define per-batch sample size and acceptance windows.
- Change control: record component revisions and calibration/firmware versions.
Required record fields
- Fixture geometry, probes/cables, terminations, and test bandwidth.
- Frequency grid, averaging/window settings, reference alignment method.
- Load condition (R/C/ADC input), supply rails, VOCM setting, temperature.
F) Rework strategy (plan the knobs before prototypes)
Analog knobs
- Padding footprints for small C/R changes to trim fc and Q.
- Jumper-selectable isolation/termination options for stability tuning.
- Probe-friendly test pads placed symmetrically for differential work.
Digital knobs (if applicable)
- EEPROM-stored coefficients with versioned calibration conditions.
- Loopback/through modes to validate reference alignment quickly.
- Configuration change recovery checks included in the test plan.
Applications & IC selection notes (phase-centric)
Application guidance is limited to frequency/phase concerns: phase margin, group delay behavior, phase matching, and latency. Noise and distortion details belong to their own pages.
A) Application patterns (what phase must guarantee)
Audio / measurement
- Prioritize waveform fidelity when transient shape matters: constrain τg ripple over 0…BW.
- Use all-pass/phase equalization only when magnitude meets spec but timing does not.
- Acceptance: τg ripple + phase linearity window + repeatable alignment vs temperature.
ADC anti-alias / DAC reconstruction
- Pick fc:fs coherently with latency and passband phase goals, not magnitude alone.
- Verify with the real load (ADC/DAC interface network) because it can move poles and reduce margin.
- Acceptance: PM under worst-case load + τg ripple over passband + channel Δφ for multi-channel systems.
Comms baseband (variable bandwidth)
- Across BW settings, require repeatable phase and group delay behavior, not only a tunable cutoff.
- For Gm-C/SC solutions, validate phase/τg repeatability across temperature and configuration changes.
- Acceptance: Δφ and τg drift across configurations + recovery time after reconfiguration.
Control loops (phase-lag budget)
- Any filter delay consumes loop phase margin. The allowable delay must be defined as a requirement field.
- Confirm margin using step and frequency response under the real actuator/load condition.
- Acceptance: PM guardband at crossover + bounded ringing/settling template under worst-case conditions.
B) IC selection notes (phase-centric fields)
What to request or confirm in datasheets
- GBW and phase margin conditions: load, gain, output swing, and temperature conditions used for PM claims.
- AOL vs frequency: to anticipate Q/fc shift and added phase lag near the passband.
- Load stability: capacitive load behavior and recommended isolation strategy.
- Differential outputs: VOCM/CMFB dynamics and sensitivity to output common-mode loading.
- Input/output capacitance sensitivity: hidden poles from parasitics and protection networks.
- Repeatability: configuration change recovery and drift across temperature/lot (for tunables/programmables).
Reference examples (part numbers; starting points only)
These examples are provided to speed up datasheet lookup and lab validation. Selection must be driven by the checklist above (conditions + guardbands).
Fully-differential amplifiers (VOCM-driven ADC interfaces)
TI THS4551, TI THS4552, TI THS4561
ADI ADA4940-1, ADI ADA4945-1
ADI (Linear Tech) LTC6363, ADI (Linear Tech) LTC6409
ADI ADA4940-1, ADI ADA4945-1
ADI (Linear Tech) LTC6363, ADI (Linear Tech) LTC6409
Single-ended op-amps often used in active filters (GBW/phase behavior must be verified)
TI OPA1656, TI OPA1642, TI OPA1612
ADI ADA4625-1, ADI ADA4898-1
ADI ADA4625-1, ADI ADA4898-1
Tunable / integrated low-pass filters (phase repeatability across settings)
ADI (Linear Tech) LTC6603, ADI (Linear Tech) LTC6602-2
ADI (Linear Tech) LTC1564
ADI (Linear Tech) LTC1564
Switched-capacitor / clock-set filters (verify phase and clock feedthrough impact)
ADI (Linear Tech) LTC1068, ADI (Linear Tech) LTC1064
Maxim MAX7400, Maxim MAX291
Maxim MAX7400, Maxim MAX291
Programmable gain blocks (gain changes can change phase/margin)
TI PGA281, TI PGA280
ADI AD8250, ADI AD8251
ADI AD8250, ADI AD8251
Practical rule: evaluate phase/τg/Δφ under the real load and probing method before committing any reference part number.
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FAQs (Frequency & Phase)
Troubleshooting is strictly phase-centric: phase margin, GBW/AOL limits, Q sensitivity, group delay behavior, channel phase matching, and measurement pitfalls. Answers follow a fixed 4-line structure: Likely cause / Quick check / Fix / Pass criteria.
Note: Part numbers shown are reference starting points to speed datasheet lookup (examples only). Validation must follow the checklist: real load + probing method + baseline/de-embedding + temperature/lot repeatability.
