Crystal Oscillators (XO) are the fixed-frequency reference clocks used in most systems: reliable, cost-effective, and low phase noise when measured under the right load, power, and layout conditions.
This page explains how to choose, verify, and board-integrate an XO so frequency accuracy, jitter/phase-noise, startup, and EMI behavior stay within spec from bench to production.
XO (Crystal Oscillator) — What it is and where it fits
A crystal oscillator (XO) is a packaged clock source that combines a quartz resonator and a sustaining oscillator circuit to produce a
fixed-frequency output with predictable startup behavior and strong production repeatability.
It is commonly used as a general reference clock for MCU/SoC/FPGA and “everyday” digital timing where cost and integration matter.
System role
Reference → (optional cleaning) → distribution → endpoints
In a clock tree, the XO typically sits at the source layer and feeds either endpoints directly
(MCU/SoC/FPGA/PHY) or an optional jitter-cleaning / synthesis stage when the downstream jitter budget is tighter.
The XO is the reference; it is not a jitter cleaner and it is not a disciplined/holdover timing source.
Use an XO when
Fixed-frequency system reference is needed with low BOM and predictable startup.
Production repeatability and low bring-up risk matter more than ultimate temperature stability.
Clock integrity can be achieved with good power/layout practices at the board level.
Do not rely on an XO alone when
ppm-class stability across temperature and fast thermal recovery are mandatory (TCXO-class need).
Holdover and long-term timing stability are primary requirements (OCXO / disciplined source need).
Downstream endpoints have ultra-tight random-jitter limits (converter/SerDes grade clocking may need cleaning).
PLL fractional spur theory, CDR/DDS deep design, full timing holdover architecture.
TCXO compensation loops and OCXO oven control mechanics (only navigated via links).
The XO is the reference source. Optional cleaning and downstream distribution exist to meet endpoint jitter/skew needs, but are treated as separate topics to avoid overlap.
XO vs crystal + external oscillator (Pierce) — choose the integration level
Decision framing
Treat “clock source” as a production & risk decision, not only BOM cost
There are three practical integration choices for a crystal-based clock source:
(1) XO module, (2) crystal + MCU internal oscillator,
or (3) crystal + external Pierce oscillator.
The best choice is usually determined by bring-up risk, layout sensitivity, and production repeatability—not by nominal BOM alone.
Practical drivers
Six questions that decide the integration level
Bring-up tolerance: Is “sometimes fails to start” acceptable, or must first-boot success be near 100%?
Layout control: Can the crystal loop be kept short, quiet, and on a continuous reference plane (no slots, no noisy edges)?
Production repeatability: Is there a plan to test startup time and frequency offset across lots/temperature/voltage?
EMI constraints: Will fast CMOS edges require controlled routing, series damping, or level translation?
Power modes: Are enable/standby behavior and startup time deterministic requirements?
Service cost: Is field return / rework cost far higher than the delta cost of using an XO module?
Rule of thumb (engineering cost)
If layout noise is hard to control, startup must be deterministic, and production repeatability matters,
an XO module usually minimizes total engineering cost.
If BOM is extremely constrained and layout/test control is strong, a crystal-based approach can be justified.
Side-by-side comparison
Focus on risk, layout sensitivity, and production
Dimension
XO module
Crystal + MCU internal osc
Crystal + external Pierce
Bring-up risk
Low (packaged, characterized)
High (loop is board-sensitive)
Medium (depends on implementation)
Layout sensitivity
Medium (power & routing still matter)
High (parasitics/ESD/noise coupling)
High (loop stability & parasitics)
Production repeatability
High (fewer board variables)
Medium/Low (needs strong test plan)
Medium (still loop-dependent)
Debug effort
Low
High (measurement can perturb the loop)
High (component/loop sensitivity)
BOM / flexibility
Medium cost, simple integration
Lowest BOM, highest board dependence
Low/medium BOM, design effort required
Quick checks (bring-up reality)
Startup distribution: log the 1st-boot start time across multiple boards and power ramps; look for long tails and intermittent failures.
Frequency sanity: measure frequency using a timebase with known accuracy and sufficient gate time; avoid probing that adds capacitance to sensitive nodes.
Coupling symptoms: spurs that move with digital activity often indicate supply or routing coupling; isolate by changing load, routing, or local decoupling.
The integration choice is an engineering risk decision. XO minimizes loop sensitivity; crystal-based solutions can win on BOM but require stricter layout discipline and stronger test coverage.
How an XO works (crystal resonance + sustaining loop)
Concept model
Equivalent crystal + sustaining loop explains start, frequency, and aging behaviors
Crystal equivalent (engineering meaning)
Rs: effective loss. Higher loss reduces start-up margin and increases sensitivity to noise and parasitics.
Lm/Cm: motional resonance (high-Q behavior). Defines how sharply the crystal “selects” frequency.
C0: shunt capacitance. Drives sensitivity to load and board parasitics (frequency pulling).
Key point: the operating point depends on the effective load (CL + stray C), so layout and probing can shift frequency and margin.
Sustaining loop (what makes it run)
Start-up: loop gain and phase must satisfy oscillation conditions (margin matters, not only “typical”).
Amplitude control: limiter/AGC stabilizes amplitude; it prevents runaway and defines drive level.
Output buffer: shapes the clock edge; it can translate supply noise into spurs or jitter if power integrity is weak.
Key point: “no start / slow start” is usually margin; “frequency error” is usually load/parasitics; “spurs/jitter” is often supply/routing injection.
Engineering hooks
Translate the model into checks, fixes, and pass criteria
Start-up failures / slow start (margin problem)
Likely causes
Insufficient loop margin at cold/hot corners or at low VDD.
Excessive effective load (CL + stray C) or leakage (contamination/ESD/flux).
Supply noise or ground return discontinuities injecting phase perturbations.
Quick checks
Measure start time distribution across boards and power ramps; watch for long tails and intermittent non-starts.
Reduce probing capacitance (short ground spring, proper termination); confirm frequency/behavior does not shift with the probe.
Temporarily reduce nearby digital activity; if start reliability improves, coupling is likely.
Fix actions
Improve local power integrity: short decoupling loop, quiet reference plane, avoid plane splits near the XO.
Reduce leakage risks: clean residues, avoid high-impedance sensitive nodes near contaminants, review ESD structures near pins.
Pass criteria
Start-up is deterministic across boards and temperature corners: no intermittent non-start events and no long-tail start times beyond the system boot budget.
Drive level (too high vs too low)
Over-drive risk
Accelerated aging or permanent frequency shift over time.
Higher sensitivity to stress and temperature gradients.
Under-drive risk
Hard start, slow start, and increased sensitivity to supply/routing noise.
More jitter-like behavior when margin is low and the loop is easily perturbed.
Practical implementation hook
Treat drive level as a selection and validation parameter. If the application is sensitive to long-term drift,
prioritize datasheet drive limits and validate frequency stability under realistic supply noise and load conditions.
The crystal model explains sensitivity to load and parasitics. The sustaining loop explains start-up margin and how supply/routing noise can become spurs or jitter at the output.
Key specifications that actually matter for XO
Rule
Any clock specification without test conditions is not comparable. Always state the measurement setup
(load, supply, temperature, and for jitter the integration window).
Determines initial timing margin and baud-rate/clock-domain tolerances. It sets the starting point before temperature drift and aging are added.
How to verify
Use a timebase with known accuracy; ensure enough gate time to reduce counter quantization error.
Declare load and measurement point; avoid probing that adds significant capacitance.
Spec
Temperature stability
ppm over the operating range
Why it matters
Defines worst-case frequency offset after environmental changes. It impacts long-run timing margin, calibration intervals, and interoperability tolerances.
How to verify
Perform a temperature sweep and record frequency vs temperature; note hysteresis and settling time.
Control airflow and gradients; mechanical stress and gradients can dominate apparent drift.
Spec
Aging (long-term drift)
ppm per year (conditions apply)
Why it matters
Governs margin over product lifetime. Aging must be budgeted even when initial accuracy is good, especially for long service intervals.
How to verify
Treat datasheet aging as a budget term and apply guardband; do not assume it can be “calibrated away” forever.
When lifetime margin is critical, add field monitoring hooks (periodic frequency check against a reference).
The offset curve reveals where noise energy sits (close-in vs far-out). This determines sensitivity to filtering/cleaning stages and how spurs present in real systems.
How to verify
Check PN at multiple offsets (1/10/100 Hz, 1/10/100 kHz) rather than a single point.
Confirm narrow spurs move with board activity or supply ripple to identify injection paths.
Spec
RMS jitter (integration window)
f1..f2 must be stated
Why it matters
RMS jitter is a computed number derived from phase-noise integration. The same XO can report different jitter values if the integration window changes.
How to verify
Always record f1..f2, instrument bandwidth, and filtering configuration.
Compare like-for-like conditions: same load, same supply, same measurement chain, same window.
Output swing, termination, and edge rate affect interface margin and EMI. Incorrect loading can distort duty cycle and increase coupling.
How to verify
Verify waveform with correct termination and a probing method that does not add large capacitance.
Document the load condition used for rise/fall and duty-cycle measurements.
Spec
Supply sensitivity & control behavior
VDD noise, startup, enable
Why it matters
Supply noise and enable sequencing influence start-up reliability and spur/jitter behavior. A “good XO” can look poor on a noisy board.
How to verify
Record start time and failure rate across VDD ramps and temperature corners.
Correlate spur/jitter changes with supply ripple and nearby digital activity to locate injection paths.
Use the mapping to translate datasheet numbers into system risk. Treat jitter as a windowed metric and treat frequency error as the sum of initial + temperature + aging budgets.
Phase noise & jitter for XO — the only model needed on this page
Rule
RMS jitter is a windowed metric. Any jitter number is only meaningful with a stated
integration window (f1..f2) and test conditions (VDD, load, measurement chain).
Minimal model
PN curve + integration window → RMS jitter
Phase noise (PN) is specified as an offset curve (e.g., 10 Hz, 100 Hz, 1 kHz, 10 kHz, 100 kHz).
RMS jitter is computed by integrating that curve over a stated offset range f1..f2.
Changing f1..f2 changes the result, even when the XO is identical.
Practical reading
Close-in vs far-out (XO-side intuition)
Close-in PN
Represents noise energy near the carrier. It often shows up as slow phase wander and can be sensitive to low-frequency supply/ground perturbations.
Far-out PN
Contributes strongly to wideband RMS jitter. It is commonly impacted by broadband noise injection (power integrity, routing coupling, edge-shaping).
Scope boundary
This page focuses on the XO output contribution and measurement conditions. System-wide PLL/cleaner transfer functions belong in the jitter overview page.
Spur playbook
Identify a spur and trace its source
Common sources
Supply coupling: DC/DC ripple, LDO noise, poor local decoupling loops.
Digital activity: bus toggling, DDR harmonics, periodic interrupts, GPIO bursts.
Layout/return issues: shared return paths, plane splits, long stubs near the XO.
How to confirm “spur”
Narrow and repeatable: line stays narrow with stable frequency/offset location.
Correlation test: change the suspected source frequency (switching rate / traffic pattern) and check whether the spur follows.
Isolation test: reduce the coupling path (quiet supply, short routing, shielding/guard return) and check whether the spur drops.
Quick check & pass criteria (XO-side)
Quick check
Re-run jitter/PN with an explicitly stated window (f1..f2) and a repeatable load/termination.
Then toggle the suspected aggressor (DC/DC, interface traffic) to see whether a narrow line follows.
Pass criteria
Reported RMS jitter is stable across repeated runs with identical conditions, and no dominant narrow spur remains after supply/routing isolation actions.
RMS jitter is obtained by integrating phase-noise over a stated offset window. If the integration window changes, the computed jitter changes.
Report f1..f2 and test conditions for any meaningful comparison.
Load capacitance, frequency pulling, and why measured frequency looks “wrong”
Key idea
An XO has an internal resonator and load network, but the effective load seen at the pins
still includes external contributors (receiver input capacitance, routing parasitics, protection parts, and probe capacitance).
These can cause apparent frequency shift and “board-to-board” variation.
Symptom patterns
Common “wrong frequency” observations
Frequency shifts when the probe or fixture changes (touching the node moves the number).
Different boards show consistent offset in one direction, even with identical XOs.
Adding ESD/protection or longer routing changes the observed frequency or duty cycle.
Frequency appears “unstable” only during high digital activity or near a noisy supply condition.
Most likely causes
External contributors that change the effective load
Protection parts: ESD diodes and clamps add capacitance and nonlinearity.
Probe capacitance (Cprobe): measurement chain becomes part of the load.
Clarify the datasheet condition
Always compare against the XO’s stated output load/termination condition. A “wrong” board measurement is often a different load condition, not a defective XO.
Debug flow: verify → fix → pass
Quick verify
Change probing method (lower C probe, short ground spring, correct termination) and confirm the frequency reading is stable.
Measure at multiple points (near XO pin vs after long routing) to reveal load/routing dominance.
Temporarily isolate or reduce the downstream load (disable a buffer branch / remove a heavy receiver) and observe direction of change.
Compare with/without nearby protection devices (or swap to lower-capacitance options) if feasible.
Fix actions
Buffer/isolate the XO from large Cin and long traces when multiple endpoints are needed.
Control routing: short, minimal stubs, avoid aggressive coupling to fast digital buses.
Select protection wisely: avoid high-capacitance ESD parts on sensitive clock nodes.
Standardize measurement: document the exact probe, termination, and node used for frequency verification.
Pass criteria
Under a documented load and measurement method, the observed frequency is repeatable (probe-insensitive) and the board-to-board distribution
fits the system ppm budget after accounting for initial accuracy and environmental drift.
The internal resonator sets the nominal frequency, but external capacitance and parasitics at the pins change the effective load and measurement conditions.
Probe capacitance is often the biggest hidden contributor.
Power, enable/startup behavior, and output loading
Goal
Prevent unstable bring-up by controlling VDD quality, EN sequencing, and
output loading so the XO starts once, settles once, and stays repeatable under a documented test method.
Startup & settle
Treat startup time and stabilization time as separate checks
Start-up time: time from valid VDD/EN to a sustained clock waveform at the pins.
Stabilization time: time for frequency/phase-noise behavior to settle to the steady-state range under the actual load.
Warm-up note: early seconds after power-up may show larger frequency drift and higher sensitivity to supply/ground disturbances.
Practical implication
Frequency checks, calibration snapshots, and “clock-good” decisions should reference a defined stabilization interval rather than the first visible cycles.
Enable / standby
Avoid re-start loops caused by glitches and undefined GPIO states
Failure patterns
EN rises while VDD is still ramping; the device crosses internal thresholds multiple times.
EN is driven by an MCU pin with unknown default state during reset.
Standby toggling causes a short “clock burst” or long recovery before stable operation.
Verification actions
Capture VDD + EN + CLK on the same trigger to detect repeat-start signatures.
Temporarily drive EN from a clean source (hard pull + known delay) to isolate MCU sequencing effects.
Document the allowed EN behavior: minimum pulse width, monotonic rise, and deglitch strategy.
Output loading
Load and termination directly affect edges, EMI, and measured jitter
LVCMOS outputs
Heavy capacitive loading and long traces slow edges and increase ringing/overshoot.
More endpoints usually require buffer/fanout rather than direct multi-drop routing.
Edge degradation can appear as worse jitter on the instrument, even if the XO core is unchanged.
LVDS / differential outputs
Use the recommended termination and keep the differential pair short and symmetric.
Incorrect termination can create reflections that look like duty distortion or narrow spurs.
Maintain a continuous reference plane to protect return currents and reduce coupling.
Bring-up checklist
A repeatable procedure for first board power-on
Steps
Verify VDD ramp is monotonic and local decoupling is installed at the XO pins.
Verify EN is glitch-free and asserted only after VDD is within the valid range.
Confirm CLK starts once and reaches sustained oscillation (no burst/drop loops).
Re-check using a defined probe + termination to avoid probe-dominated results.
Change downstream load (disconnect a branch / add a buffer path) to confirm the output is not edge-limited by loading.
Pass criteria
Repeated cold starts show consistent behavior (no repeated start/stop signatures).
CLK becomes stable within the documented stabilization interval under the intended load.
Probe changes do not significantly alter the measurement result (probe-insensitive reading).
Adding one endpoint does not create large ringing, duty collapse, or dominant spurs.
Bring-up debug should capture VDD, EN, and CLK together. Loading and probing change the observed waveform and can dominate the measured result if not standardized.
PCB layout & EMI: placement, return paths, and isolation that actually work
Scope
This section covers XO-local placement, decoupling, routing, and return paths.
System-level EMI strategy belongs to the dedicated EMI page.
Placement
Place by “usage”: endpoint clock vs shared reference source
Endpoint clock (MCU/SoC/PHY)
Prefer proximity to the endpoint to minimize trace length, coupling area, and return-path complexity.
Shared reference source (feeds a clock tree)
Prefer proximity to the clock-tree entry (fanout/cleaner input) to avoid a long, sensitive “pre-tree” segment.
Power & return
Optimize the local loop, not just “more capacitance”
Decoupling: place the smallest/highest-frequency capacitor as close as possible to the XO VDD/GND pins to minimize loop area.
Isolation (R / ferrite): useful when supply noise injection is dominant, but excessive impedance can hurt startup margin.
Return path: keep reference plane continuous; avoid plane splits/slots under the XO and its clock trace.
Keep the clock trace short and avoid stubs and nearby high-edge-rate buses.
Maintain a continuous reference plane; do not cross split planes or slots.
Minimize coupling to DC/DC hot loops and dense switching regions (DDR/SerDes).
Guard ring / shielding note
Guard structures help when they enforce a controlled return and reduce near-field coupling.
Overuse or placing copper too close can add parasitic capacitance and shift frequency behavior, especially on high-impedance nodes.
Do / Don’t
XO-local layout checklist
Do
Keep the XO and its first trace segment away from DC/DC hot loops and fast digital edges.
Place the smallest decoupling capacitor right at the XO pins to minimize the loop.
Route on a continuous reference plane and keep return currents local and uninterrupted.
Use buffering/fanout when multiple endpoints are required.
Don’t
Do not cross plane splits/slots under the XO or its clock route.
Do not run the clock trace parallel to a high-speed bus for long distances.
Do not place high-capacitance “shield” copper too close to sensitive nodes without verifying impact.
Do not rely on probing at a distant node as “the truth” without standardizing the measurement method.
The most reliable improvements come from reducing local loop area, keeping the reference plane continuous, and keeping the first clock segment short and away from fast/noisy regions.
Reliability: aging, drive level limits, shock/vibration, and long-term drift
Scope
Explain why frequency can drift over life and environment, and provide executable ways to budget guardband,
monitor drift, and avoid self-inflicted damage (over-drive, stress, thermal gradients).
MEMS shock immunity belongs to the MEMS oscillator page (one-line compare + internal link there).
Aging
Drift accumulates over days/months/years — guardband is mandatory
Risk
Long-term frequency error grows as the resonator and package relax and age, and the drift can be nonlinear
(often larger early in life and slower later). A design that barely meets ppm margin on day one can fail after field time.
Trigger conditions
Long operating time (calendar time + powered time).
Frequent temperature cycling and mechanical stress exposure.
Operation near drive level limits (self-heating and stress).
Monitor
Track frequency offset vs time under a fixed condition (VDD, load, temperature window).
Capture slope (ppm/day or ppm/month) rather than a single-point reading.
Record events: temperature excursions, shock events, firmware changes affecting load/EN sequence.
Standardize measurement conditions; treat probe/load changes as configuration changes.
If a system reference exists (GNSS/PTP/SyncE), plan periodic field trimming or sanity checks.
Drive level
Over-drive is a reliability issue, not a “performance tweak”
Risk
Excessive crystal drive can accelerate aging, increase drift after thermal cycling, and increase sensitivity to shock/vibration.
Insufficient drive can increase start failures or increase susceptibility to noise.
Trigger conditions
Operating near maximum output swing into heavy load.
Incorrect termination or multi-drop routing causing reflections and repeated edge stress.
Supply noise modulating the output stage, creating extra energy at the resonator.
Monitor
Frequency step after shock/thermal cycle or drift slope change.
Waveform integrity at the intended node (avoid “no-load” illusions).
Design actions
Keep output loading within recommended limits; buffer fanout when needed.
Control overshoot/ringing with routing discipline and correct termination (where applicable).
Keep VDD clean locally to avoid amplitude/drive modulation.
Stress & gradients
Mechanical shock and thermal gradients can create step-like frequency changes
Risk
Stress on the package and PCB can shift the resonator’s effective operating point.
Nearby hot components can create gradients that vary with workload, creating “frequency vs activity” behavior.
Trigger conditions
Drop/shock events; vibration exposure in transport or operation.
Placement near heat sources (DC/DC, RF PA, high-current inductors).
Large temperature gradients during workload transitions.
Monitor
Step changes after known shock/thermal events (not just slow drift).
Correlation of offset with board temperature sensors and workload states.
Design actions
Place XO in a mechanically and thermally quiet area; avoid hot loops and magnetics.
Minimize warpage stress near the XO footprint; avoid routing patterns that concentrate strain.
Validate under thermal cycling and representative vibration profiles, not only room temperature.
Quick verification actions (field-realistic)
Aging slope check
Measure frequency offset at fixed conditions (documented VDD/load/probe) over a defined interval and compute a slope.
Use slope distribution to set guardband rather than relying on a single snapshot.
Shock/thermal step check
Record a baseline offset, apply a controlled thermal excursion or vibration exposure, then re-measure under the same conditions.
Track both step change and slope change.
Pass criteria
Drift remains within the allocated guardband over the intended life and stress profile, and stress events do not create step changes
that exceed the system’s timing margin.
Reliability planning requires budgeting slow aging drift plus step changes caused by temperature excursions and mechanical stress.
Monitor slope and event-correlated steps under a standardized measurement setup.
Verification & production test hooks (plus the engineering checklist)
Goal
Prevent “bench looks fine, production fails” by defining must-test items, avoiding
measurement traps, and standardizing data fields + limits + binning.
This section stays XO-specific; full production system architecture is out of scope.
Must-test
Minimum set for XO acceptance (declare conditions)
Frequency offset — measured under declared VDD, temperature, output load/termination, and probe method.
Start-up time — from valid VDD/EN to sustained clock; record stabilization window if needed.
Output integrity — amplitude/logic levels, duty cycle, edge quality at the intended node.
Jitter/PN (only when required) — must include integration window and instrument BW.
No split/slot crossing; stub/length policy satisfied
Bring-up
Capture VDD / EN / CLK together
Single-trigger scope; repeat cold start N times
No restart loops; stable within defined settle window
Bench
Frequency offset with declared conditions
Two gate times; two probe methods if near limit
Pass margin recorded; setup-insensitive reading
Temp
Thermal excursion / cycling check
Baseline → excursion → re-measure same conditions
No unacceptable step; drift stays within guardband
Production
ATE recipe + binning + traceability fields
Lock fixture/node/gate time/reference timebase
Repeatability achieved; data supports root-cause analysis
A stable production flow requires fixed measurement conditions, repeatability checks, and traceable metadata.
Add jitter/PN tests only when an endpoint requirement justifies the cost and complexity.
Reliability: aging, drive level limits, shock/vibration, and long-term drift
Scope
Explain why frequency drifts over life and environment, and provide executable ways to budget
guardband, monitor drift, and avoid over-drive and stress.
MEMS shock immunity belongs to the MEMS oscillator page (one-line compare + internal link).
Aging
Drift accumulates over time — guardband is mandatory
Risk
Long-term frequency error grows as the resonator/package relax and age. Drift can be nonlinear
(often larger early in life). A design that barely meets ppm margin on day one can fail after field time.
Trigger conditions
Calendar time and powered time both contribute.
Frequent temperature cycling and mechanical stress exposure.
Operation near drive level limits (self-heating and stress).
Monitor
Track frequency offset vs time under fixed conditions (VDD, load, temperature window).
Capture a slope (ppm/day or ppm/month), not only a single reading.
Record events: thermal excursions, shock, firmware changes affecting load/EN.
Standardize measurement node/probe/termination to avoid setup-dominated drift.
When an external reference exists, plan periodic field sanity checks or trimming.
Drive level
Over-drive is a reliability issue, not a “performance tweak”
Risk
Excessive drive can accelerate aging and increase drift sensitivity after thermal cycling or vibration.
Too little drive can increase start failures and noise sensitivity.
Trigger conditions
Overloading the output (multi-drop, heavy capacitance, wrong termination).
Reflections creating repeated stress on edges.
Supply noise modulating the output stage energy.
Design actions
Keep output loading within recommended limits; buffer for fanout.
Control ringing via routing discipline and correct termination when applicable.
Local VDD cleanup to avoid amplitude/drive modulation.
Stress & gradients
Shock and thermal gradients can create step-like frequency changes
What to watch
Step change after a known shock/thermal event (not just slow drift).
Correlation to workload (hot areas near the XO shift with activity).
Repeatability across assemblies (stress/placement differences).
Mitigation
Place XO away from heat sources (DC/DC, inductors, RF PA regions).
Reduce local board warpage stress around the XO footprint.
Validate with thermal cycling and representative vibration profiles.
Reliability planning requires budgeting slow aging drift plus step changes from temperature excursions and mechanical stress.
Verification & production test hooks (plus the engineering checklist)
Goal
Prevent “bench looks fine, production fails” by standardizing must-test items, avoiding measurement traps, and locking the data fields
needed for limits, binning, and root-cause feedback.
Must-test
Minimum acceptance set (declare conditions)
Hard fail: outside absolute limits (spec/contract).
Soft fail / review: near edge; re-test with alternate probe/fixture + longer gate time.
Pass with margin tag: store remaining margin for analytics and sourcing decisions.
Checklist
Copyable engineering checklist (no wide tables)
LayoutXO quiet zone + short first segment
Quick verify
Review placement vs DC/DC/DDR; avoid long parallel runs; no plane splits under XO/trace.
Pass criteria
No split/slot crossing; stub policy met; keep-out honored.
Bring-upCapture VDD/EN/CLK together
Quick verify
Single-trigger scope capture; repeat cold starts; look for restart loops or burst/drop behavior.
Pass criteria
Consistent start behavior; stable within the defined settle window.
BenchFrequency offset with declared conditions
Quick verify
Measure using two gate times; if near limit, repeat with alternate probe/node to detect setup dominance.
Pass criteria
Setup-insensitive reading; pass margin recorded for analytics.
TempThermal excursion / cycling check
Quick verify
Baseline → excursion → re-measure at same VDD/load/node; track step change + slope change.
Pass criteria
No unacceptable step; drift stays inside allocated guardband.
ProductionATE recipe + traceability locked
Quick verify
Lock fixture, node, probe method, gate time, and counter timebase calibration; enforce metadata logging.
Pass criteria
Repeatability achieved; data supports root-cause analysis and supplier feedback.
Mobile-safe: checklist is card-based (no wide tables, no horizontal scrolling required).
Mobile-safe: the diagram is clipped inside its card; no fixed pixel width/height is used.
Applications (XO usage patterns only)
Scope
This section is a usage-pattern library: what an XO can cover, what it cannot,
and which “next page” to use when jitter/stability/synchronization requirements exceed XO capability.
Protocol and endpoint clock specs (JESD/PCIe/ADC sampling/PTP/SyncE) stay on their dedicated pages.
Pattern A
MCU / SoC main clock (fixed-frequency reference)
Need
Predictable start-up + stable output level
Low BOM risk and consistent production behavior
EMI managed by routing discipline and correct loading
Is XO enough?
Typically Yes. Focus on enable/start timing, supply cleanliness near the XO, and output loading (avoid heavy capacitive loads and stubs).
Example material numbers (XO)
Examples to speed datasheet lookup; verify frequency/voltage/output/package/suffix options.
Abracon ASFL1 (family; multiple frequencies/3.3 V HCMOS/TTL options)
NDK NZ2520SDA / NZ2520SD (family; low phase-noise XO options)
TXC 7C Series (family; SMD crystal oscillators, CMOS output options)
Next stop
If the endpoint is jitter-critical or requires synchronization/holdover, jump to: Clock Cleaners / Interface-Focused Clocks / Timing & Synchronization (internal links).
Pattern B
General reference for FPGA / PHY (non-strict clocking)
Need
Stable frequency reference; moderate jitter tolerance
Controlled distribution (buffer/fanout preferred over multi-drop)
Known output standard and termination discipline
Is XO enough?
Often Yes when the endpoint is not jitter-limited. Use a buffer for fanout and keep the first trace segment short and clean.
Example material numbers (XO)
Abracon ASFL1 (5032 class XO family; common for platform references)
Epson SG-210STF (2520 class XO family; compact reference)
TXC 7C Series (5032 class XO family; CMOS output options)
Next stop
If margin collapses due to jitter/spurs or multi-output skew becomes critical: Clock Distribution & Fanout / Jitter Attenuators (internal links).
Pattern C
Clock-tree root: XO → (optional cleaner) → fanout → endpoints
Need
Production-consistent reference node
Defined “handoff points” between noisy domains and clock domains
Fanout budget and a place to add cleaning if needed
Is XO enough?
XO can be a solid root reference, but a cleaner decision is required when endpoints are jitter-limited or when deterministic synchronization is needed.
Example material numbers (XO)
Abracon ASFL1 (root reference family; many platform-friendly variants)
Epson SG-210STF (compact root reference family)
NDK NZ2520SDA (low PN family when close-in noise matters at the root)
Next stop
Cleaner decision and fanout planning belong to: Jitter Attenuators / Fanout Buffers / Glitch-Free Mux (internal links).
Pattern D
Shock/vibration and harsh mechanics (handoff only)
If mechanical shock/vibration dominates failure modes, consider switching to the MEMS oscillator page.
Material-number examples for MEMS belong there (internal link), because the trade space differs from crystal XO.
XO is a strong fit for general references and MCU clocks; jitter-critical or holdover-critical endpoints should jump to the dedicated clock-cleaning or timing pages.
IC selection logic (what to ask vendors + decision flow)
Prime rule
Compare parts only under declared conditions.
For phase-noise and jitter: request the offset points and the RMS jitter integration window (f1..f2).
Without those, “jitter numbers” are not comparable.
A) RFQ fields
What to ask vendors (structured, verifiable)
1) Electrical interface
Frequency (MHz) + allowed initial tolerance (ppm)
VDD range + current (start / steady / standby)
Output standard (LVCMOS/LVDS/…) + duty cycle limits
RMS jitter integration window f1..f2 and measurement bandwidth
Known spurs (typical spur patterns) and test setup notes
3) Stability & reliability
Operating temperature range + stability over temperature
Aging rate and lifetime notes (declare time base and conditions)
Drive/overload limits and recommended operating conditions
Package / height / MSL / reliability qualifications (if required)
4) Startup / enable behavior
Start-up time and any settle/warm-up time requirement
Enable/standby truth table and glitch behavior
Supply ramp constraints (if any)
5) Supply chain / compatibility
Second-source strategy and pin/function compatibility constraints
Lot traceability fields and PCN policy
Recommended footprint and land pattern references
B) Example RFQ lines
“Copy & edit” examples (material-number anchored)
These examples anchor the request to a known family. Replace frequency/voltage/output/suffix per the target build.
Example 1 (general MCU clock)
Request: XO family SG-210STF, [FREQ] MHz, CMOS/LVCMOS output, [VDD] V, [Temp] °C range, duty/edge specs, and declared load node.
Example 2 (platform reference)
Request: XO family ASFL1, [FREQ] MHz, 3.3 V HCMOS/TTL compatible output, start-up time, and aging/stability under declared conditions.
Example 3 (lower PN root reference)
Request: XO family NZ2520SDA (or NZ2520SD), [FREQ] MHz, PN at declared offsets + RMS jitter integrated over f1..f2, plus spur notes.
Example 4 (alternate vendor family anchor)
Request: TXC 7C Series XO, [FREQ] MHz, [VDD] V, CMOS output, declared load/termination, and start-up/enable behavior.
C) Decision flow
If/then path (prevents wrong comparisons)
Step 1 — Use-case mode
If the endpoint is a general MCU/SoC or a non-strict reference, proceed with XO selection.
If the endpoint is jitter-limited or requires deterministic synchronization/holdover → jump to the relevant dedicated page (internal links).
Step 2 — Output standard & loading
If LVCMOS multi-drop is required, add a buffer/fanout device rather than overloading the XO output.
Declare load/termination in the RFQ and verify at the intended measurement node.
Step 3 — PN/jitter comparability
If PN offsets and jitter integration window (f1..f2) are not declared, do not compare “jitter” specs.
Require the vendor to provide the declared window and measurement bandwidth.
Step 4 — Stability & aging budget
If (initial + temperature + aging + board-induced shift) exceeds the system tolerance budget, XO is not sufficient for this role.
Otherwise, record guardband and proceed.
Step 5 — Startup/enable risks
If deterministic start-up is required, lock start-up/settle time and enable behavior into the acceptance plan.
Reject parts that need undefined warm-up for the target sequence.
Step 6 — Verification plan
Lock measurement node + probe method + gate time and record lot/conditions.
Production limits and binning must reference the same declared conditions.
The flow forces declared conditions for PN/jitter and prevents “wrong-but-pretty” comparisons.
Note: Material numbers above are examples for datasheet anchoring.
Always verify package, voltage, frequency code, suffix options, qualification grade, and supply availability.
Each FAQ is a field-usable troubleshooting block. Keep measurement conditions explicit:
Node (XO pin vs endpoint), Load,
Temp, VDD,
and instrument method (counter/phase-noise/scope).
Why does the XO fail to start on some boards but not others?
Likely cause
Power ramp/enable timing differs across boards, supply impedance is higher at the XO, or the output is overloaded during start-up (too much capacitance / wrong termination / long stubs).
Quick check
Compare VDD ramp and EN edge on a “good” vs “bad” board at the XO pins (not at the regulator).
Measure CLK build-up at the XO pin with a low-capacitance method (avoid long ground leads).
Fix
Add tight local decoupling at XO VDD (small capacitor closest + a bulk nearby) and keep the return path continuous.
Reduce start-up load: shorten the first trace segment, avoid multi-drop, add a series resistor (starter range: 22–47 Ω) near the driver, or insert a clock buffer (example anchor: TI CDCLVC1102).
Pass criteria
Conditions: VDD=__ V, Temp=__ °C, Node=XO pin, Load=__ (C/termination).
Target: Start-up success rate ≥ 99.9% over N=__ power cycles; start-up time ≤ datasheet max (or ≤ __ ms system limit).
Symptom: no “silent” start-up failures; CLK amplitude and duty cycle remain within spec at the declared node.
Why is the frequency off even though the XO is “factory calibrated”?
Likely cause
Factory calibration applies to declared conditions (VDD, temperature, load, measurement node). Board-level loading, measurement method, or thermal gradient shifts the apparent frequency.
Quick check
Measure at the same node definition across boards: XO pin vs endpoint pin. Record gate time (counter) and reference timebase.
Repeat after temperature soak (avoid measuring during warm-up or while nearby hot parts change).
Fix
Align conditions to the datasheet declaration: VDD, load/termination, and node. Add a dedicated test point near XO if needed.
Reduce board-induced shift: shorten stubs, avoid routing over plane splits, keep the XO away from strong thermal gradients.
Pass criteria
Conditions: VDD=__ V, Temp=25 °C (or __ °C), Node=__, Load=__.
Target: |Δf| ≤ (system ppm budget) with a declared gate time ≥ __ ms; drift after soak ≤ __ ppm.
Symptom: frequency aligns across boards when measured under identical conditions.
Why does touching the trace/probe change the measured frequency?
Likely cause
Probe capacitance and human-body coupling alter the local impedance and return path, changing edge shape and introducing measurement artifacts (and sometimes real loading).
Quick check
Compare 10× passive probe vs active probe; use a spring ground (no long ground lead).
Measure at XO pin and at the endpoint. If the effect exists only at the endpoint, it is mostly routing/measurement coupling.
Fix
Add a defined measurement node (small pad + solid ground nearby). Keep the trace short and referenced to a continuous plane.
Use a series resistor near the source (starter range: 22–47 Ω) to reduce ringing and sensitivity to small capacitive perturbations.
Pass criteria
Conditions: Node=XO pin (preferred), Probe method declared, VDD=__ V.
Target: Touch/probe change causes |Δf| ≤ __ ppm and no visible duty-cycle shift beyond __% at the declared node.
Symptom: readings are stable across repeat measurements and probe swaps.
Why did jitter/PN get worse after moving XO farther from the SoC?
Likely cause
Longer routing increases susceptibility to coupling and return discontinuities. Edge degradation and reflections can inflate time-domain jitter at the endpoint (even if the XO itself is unchanged).
Quick check
Measure jitter/edge at XO pin vs endpoint pin. If the endpoint is worse, routing/termination dominates.
Check for plane splits, long parallel aggressors, and stubs. Correlate jitter spikes with nearby digital activity.
Fix
Shorten and simplify the first segment; keep a continuous reference plane and avoid crossing splits/slots.
Control ringing: series resistor near the driver; if fanout is needed, add a dedicated buffer (example anchor: TI CDCLVC1102).
Pass criteria
Conditions: jitter window f1..f2=__..__ Hz, Node=endpoint pin, VDD=__ V, Load=__.
Target: Jrms(endpoint) ≤ Jrms_budget (e.g., ≤ __ ps in the declared window); no endpoint-only jitter inflation vs XO pin beyond __%.
Symptom: jitter/PN readings become insensitive to routing location changes within the same layout rule set.
Why does enabling spread-spectrum elsewhere “show up” on my XO clock?
Likely cause
The “SSC” feature modulates another clock, but its energy couples through shared supplies, ground impedance, or near-field coupling into the XO clock trace or measurement setup.
Quick check
Toggle SSC on/off and confirm the observed spur/sidebands follow the SSC settings (rate/depth).
Measure XO VDD noise spectrum near the XO pins and correlate with the clock spur movement.
Fix
Improve isolation: local decoupling at XO, short return, keep-out around the clock line, and avoid parallel routing near the SSC clock.
If necessary, move the XO clock route to an inner layer with solid reference and add source-side damping (22–47 Ω).
Pass criteria
Conditions: Node=endpoint pin, Instrument=__ (spectrum/phase-noise), SSC state declared.
Target: SSC-correlated spur/sideband ≤ __ dBc (or below system mask); XO clock jitter change ≤ __ ps in the declared window.
Symptom: SSC activity elsewhere no longer measurably modulates the XO clock at the declared node.
Why is duty cycle out of spec at my load?
Likely cause
Duty cycle is load- and threshold-dependent. Heavy capacitive loading, wrong termination, ringing, or measurement bandwidth/threshold mismatch can push duty outside spec at the endpoint.
Quick check
Measure duty at XO pin vs endpoint with the same threshold definition and bandwidth limit.
Inspect ringing/overshoot; duty errors often correlate with edge distortion and reflections.
Fix
Define and meet the datasheet load. If multi-drop exists, use a fanout buffer rather than directly loading the XO.
Add source-side damping (22–47 Ω) and remove long stubs; keep a clean return path under the clock trace.
Pass criteria
Conditions: Node=endpoint pin, Threshold method=__ (50% Vpp or fixed Vth), Load=__.
Target: duty cycle within datasheet limits at the declared load (e.g., 45–55% if that is the declared spec).
Symptom: duty remains stable across probe swaps and across boards built to the same layout rules.
Why does the clock look fine no-load but collapses when connected?
Likely cause
The real load (input capacitance, termination, multi-drop) exceeds what the XO output stage is designed to drive, causing swing loss, edge slowdown, and sometimes oscillation/ringing at the endpoint.
Quick check
Measure swing and rise/fall at the XO pin and at the endpoint. A large delta indicates routing/load domination.
Temporarily remove the downstream connection or reduce load to confirm the failure mechanism.
Fix
Meet the intended load model: remove unnecessary stubs, correct termination, and avoid multi-drop from the XO pin.
Add a buffer/fanout (example anchor: TI CDCLVC1102) for multiple endpoints; add source-side damping for single-point routes.
Pass criteria
Conditions: Node=endpoint pin, Load declared, VDD=__ V.
Target: swing ≥ datasheet min at the declared node; rise/fall within endpoint requirements; no excessive overshoot/undershoot beyond __% VDD.
Symptom: waveform does not collapse when the endpoint is connected; behavior is consistent across boards.
Why does frequency drift more after reflow or mechanical stress?
Likely cause
Package/board stress changes crystal mechanical conditions and parasitics. Reflow profile, board warp, mounting torque, or proximity to heat sources can increase drift and board-to-board variation.
Quick check
Compare Δf before/after reflow on the same unit; repeat after temperature soak to separate warm-up from stress drift.
Apply controlled mechanical perturbation (board flex within safety) and check correlation of Δf vs stress.
Fix
Follow the recommended land pattern; avoid placing the XO near board edges, mounting holes, or high-CTE mismatch zones.
Reduce thermal gradients: keep distance from hot regulators/inductors; avoid airflow hotspots.
Pass criteria
Conditions: Temp=__ °C stabilized, Node=XO pin, VDD=__ V.
Target: post-reflow shift ≤ __ ppm; stress-induced shift within the board-shift budget (≤ __ ppm).
Symptom: drift becomes repeatable and bounded across production lots using the same assembly profile.
Why does adding a ferrite bead reduce EMI but worsen jitter?
Likely cause
The bead increases supply impedance at the XO across certain frequencies. If local decoupling is not tuned/placed correctly, VDD noise at the XO can increase, degrading PN/jitter even as radiated EMI improves.
Quick check
Measure XO-pin VDD noise before/after the bead change; correlate with jitter/PN changes.
Check bead placement vs decoupling: bead must feed a local capacitor network very close to the XO pins.
Fix
Place a small high-frequency capacitor directly at XO VDD pins and a bulk capacitor nearby; keep the loop area minimal.
If bead resonance is suspected, try a small series resistor (starter: 1–4.7 Ω) or a different bead impedance profile (example anchor family: Murata BLM18).
Pass criteria
Conditions: VDD=__ V, Node=XO pin and endpoint pin, jitter window f1..f2 declared.
Target: EMI metric improves (per compliance/scan) while Jrms does not exceed budget (≤ __ ps) and spur mask remains ≤ __ dBc.
Symptom: EMI benefit is retained without jitter regression.
Why do I see a narrow spur that moves with a digital clock on the board?
Likely cause
Deterministic coupling from an aggressor clock (harmonics/edges) into the XO supply, ground, or clock trace. The spur “moves” because it tracks the aggressor frequency plan.
Quick check
Change the aggressor clock frequency/divider and confirm the spur follows.
Use near-field probing along the XO clock route and near the XO supply to localize the coupling hotspot.
Fix
Increase spacing and avoid long parallel runs; route on an inner layer with solid reference.
Strengthen isolation: local XO decoupling, clean return path, and source-side damping on the XO clock.
Pass criteria
Conditions: Instrument=spectrum/PN, Node=endpoint pin, aggressor state declared.
Target: coupling-related spur ≤ __ dBc (or below system spur mask) under worst-case aggressor activity.
Symptom: spur no longer tracks aggressor clock plan changes at a visible level.
What is a practical guardband for aging and temperature?
Likely cause
Many designs budget only “initial accuracy” and ignore long-term and board-induced shifts. A practical guardband must include temperature stability, aging over the product life, and board stress/thermal gradients.
Quick check
Build a ppm budget sheet with declared conditions:
Total ppm budget = initial + temp stability + aging(Life) + board shift + margin
Fix
Request aging as a rate under declared conditions (e.g., per year) and multiply by life years. Add a board-shift allowance based on reflow/stress characterization.
Write the total budget (and conditions) into RFQ, validation, and production limits; do not accept “typical-only” data without declared conditions.
Pass criteria
Conditions: life=__ years, Temp range=__..__ °C, VDD=__ V, Node=__.
Target: Total ppm budget ≤ system tolerance with margin ≥ __% (recommended starter: 20–30% margin if no field data).
Symptom: worst-case spec closure is documented and traceable to declared vendor conditions.
How do I specify the jitter integration window to vendors/tests?
Likely cause
RMS jitter depends on the integration window and whether deterministic spurs are included/excluded. Without a declared window, “jitter” values are not comparable across vendors or tests.
Quick check
Ask for the window explicitly: f1..f2, measurement bandwidth, and whether spurs are included.
Recompute or re-measure the same part under two different windows; large differences confirm window dependence.
Fix
Use a copy/paste declaration template in RFQ and validation:
Jrms definition: integrate phase noise from f1=__ Hz to f2=__ Hz, instrument BW=__, include spurs: (Yes/No), report node=__ and load=__.
Keep the same definition for vendor reports, bench validation, and production tests.
Pass criteria
Conditions: f1..f2 and spur policy declared, Node and Load declared.
Target: vendor jitter report and in-house measurement match within ≤ __% (or ≤ __ ps) under the same definition.
Symptom: “jitter” is comparable across suppliers and stable across test setups that follow the same declaration.
Example anchors mentioned above (for datasheet lookup only): XO families such as Epson SG-210STF, Abracon ASFL1, NDK NZ2520SDA/NZ2520SD;
buffer example TI CDCLVC1102; ferrite bead family example Murata BLM18.
Verify frequency/voltage/package/suffix and qualification grade per the target build.
