123 Main Street, New York, NY 10001

Submit Your BOM

Fractional-N and Integer-N PLL Design: Phase Noise & Spurs

Fractional-N and Integer-N PLL Design: Phase Noise & Spurs

← Back to:Reference Oscillators & Timing

Fractional-N / Integer-N PLL is a frequency-synthesis engine where loop bandwidth and divider strategy shape the trade-off between fine frequency steps and phase-noise / spur purity. This page provides a practical, measurable workflow to budget noise, hunt spurs, and choose settings/components that meet a real system mask.

Definition & boundary: what a PLL solves (and what it doesn’t)

A PLL is a feedback system that forces an output clock to follow a reference in phase and frequency while enabling frequency synthesis. It is not a universal “noise eraser”: the output spectrum is a controlled blend of reference-originated noise, VCO-originated noise, and implementation artifacts (spurs, coupling, nonlinearity).

Page boundary contract

Covers
  • Integer-N vs Fractional-N PLL synthesis & tracking behavior.
  • Phase-noise transfer view, RMS-jitter window discipline, and spur mechanisms.
  • Loop bandwidth / phase margin trade-offs, lock dynamics, bring-up checks.
Does NOT cover
  • Clock cleaners / jitter attenuators deep design (only one-line context).
  • CDR / DDS fundamentals, protocol tutorials (JESD204, PCIe, PTP/SyncE).
  • Reference oscillator deep dive (XO/TCXO/OCXO/MEMS) beyond “input quality”.
For who

RF / clocking / converter / FPGA engineers who must translate specs into knobs, measurements, and pass criteria.

Minimal model (Ref → PLL → Out)

Use one stable vocabulary across the page. A PLL is best treated as a set of knobs that shape noise transfer, spur formation, and lock behavior.

Key variables (reused everywhere)
Frequency plan
fREF, fPFD, N, α (fraction)
Dynamics
Loop BW, phase margin, lock/settle
Sensitivity
KVCO, tuning-line noise
Artifacts
Spurs, coupling, nonlinearity
Synthesis statement (no derivation)
fOUT ≈ (N + α) · fPFD Integer-N: α = 0 Fractional-N: α ≠ 0

The core tension (why this page exists)

Integer-N
Cleaner spur profile and simpler predictability, but frequency resolution is constrained by the chosen fPFD and divider plan.
Fractional-N
Fine frequency steps and flexible ratios, but spur behavior becomes channel-dependent and tightly coupled to ΣΔ settings, dither, and real-world nonlinearity.
Practical rule
Always bind claims to conditions: jitter needs an integration window, spurs need an offset/mask definition, and lock time needs a Δf and mode context.
Outcome of this page
Requirements are translated into knobs, then into measurable checks, then into pass criteria for bring-up and production.
Diagram: PLL in a clock chain (minimal, reusable model)
PLL in a clock chain Block diagram showing Reference feeding PLL blocks (PFD/CP, Loop Filter, VCO, Divider) and producing Clock Output. Key knobs labeled: fREF, fPFD, N, KVCO, BW, PM, plus Integer-N and Fractional-N badges. Reference Oscillators & Timing Integer-N Fractional-N REF XO PFD/CP LOOP FILTER VCO DIVIDER N / (N+α) OUT fREF fPFD BW PM K VCO LD
Minimal reusable PLL model for this page: frequency plan (fREF, fPFD, N/α) sets resolution and spur structure; loop BW/PM shapes noise transfer and settling; KVCO amplifies tuning-line sensitivity.

Architecture: blocks, knobs, and what each knob buys you

A PLL is best engineered as a controlled trade space: each knob changes where noise comes from, where spurs land, and how fast the loop settles. The goal is not to “maximize a single spec”, but to satisfy the required jitter window and spur mask with repeatable bring-up checks.

Group 1 — Frequency plan knobs

fREF fPFD
  • Affects: step size, in-band noise share, reference-spur structure.
  • Symptom: spurs that move exactly with fPFD or fREF.
  • Quick check: sweep fPFD (or equivalent divider plan) and track spur movement.
N α
  • Affects: achievable frequencies and channel-dependent spur patterns.
  • Symptom: fractional spurs that appear only at specific channels.
  • Quick check: sweep output frequency in small steps and map “spur hot spots”.

Group 2 — Loop dynamics knobs

BW PM
  • Affects: in-band vs out-of-band noise dominance and settling behavior.
  • Symptom: “jitter improves but spurs worsen” (or vice versa) when BW changes.
  • Quick check: sweep BW and compare integrated jitter for the same window.
Icp LF order
  • Affects: loop gain, stability margin, reference-spur sensitivity (via CP behavior).
  • Symptom: “lock is stable, but close-in PN is worse than expected”.
  • Quick check: compare PN/spur while stepping Icp and verifying no PM collapse.

Group 3 — Sensitivity & coupling knobs

K VCO Tune line
  • Affects: FM sensitivity to supply/ground noise and control-line pickup.
  • Symptom: spurs that correlate with rails, digital activity, or nearby clocks.
  • Quick check: correlate spur amplitude with rail ripple and activity patterns.
Partition Returns
  • Affects: coupling spurs and “mystery” phase-noise degradation on real boards.
  • Symptom: measured results differ drastically between benches/fixtures.
  • Quick check: compare PN/spurs across grounding and routing variants.

Group 4 — Fractional-only knobs (spur ↔ noise-floor trade)

ΣΔ Dither Modulus
  • Affects: whether energy appears as discrete spurs or spreads into a higher noise floor.
  • Symptom: spur reduces after dither, but integrated jitter rises for the same window.
  • Quick check: compare (spur mask pass/fail) and (RMS jitter) under the same integration limits.
Measurement discipline (must be explicit)
  • Jitter must specify integration window and band edges.
  • Spurs must specify offset, RBW/VBW, and mask definition.
  • Lock/settling must specify Δf step and mode transitions.
Sweep grammar (repeatable bring-up pattern)
Sweep A
change fPFD / plan → track spur movement
Sweep B
change BW/PM → compare jitter (same window)
Sweep C
change ΣΔ/dither → spur-to-floor conversion
Sweep D
change partition/rails → coupling spur correlation
Diagram: Knobs-to-metrics map (what each knob buys, and what to check)
Knobs-to-metrics map Left column lists PLL knobs (fREF, fPFD, N/alpha, BW, PM, KVCO, Sigma-Delta, Dither). Right column lists output metrics (Close-in PN, Far-out PN, RMS jitter window, Ref spurs, Frac spurs, Lock time). Arrows show primary influences and trade-offs. KNOBS METRICS fREF fPFD N α BW PM K VCO / Tune sensitivity ΣΔ Dither Close-in PN Far-out PN RMS jitter window Ref spurs Frac spurs / floor Lock time / settle Noise Spur Lock
Use this map as the page’s “language”: each knob is evaluated by the metric it moves and the check that confirms it—always under a defined jitter window and spur mask.

Phase noise & jitter fundamentals (only as needed): a transfer view

Budgeting a PLL is most reliable when treated as noise transfer, not as isolated datasheet numbers. Output noise is shaped by the loop: reference-originated noise is passed mainly through a low-pass-like path, VCO-originated noise is passed mainly through a high-pass-like path, and implementation terms add on top (spurs and floor).

Three-sentence rule

  1. Output noise = Ref (low-pass-like) + VCO (high-pass-like) + other additive terms.
  2. Loop BW moves the crossover and changes which source dominates which region.
  3. RMS jitter is only meaningful with an explicit integration window and measurement settings.
Boundary note

Jitter cleaners / attenuators specialize in isolating reference noise with narrow tracking profiles; this page only uses the same transfer vocabulary for synthesis PLL budgeting.

5-step budget workflow (repeatable)

1 Define requirement in measurement terms
Specify RMS jitter integration bounds (and/or PN mask offsets). Without a window, results are not comparable.
2 Split the spectrum into regions
Treat in-band (inside loop influence) and out-of-band (VCO-dominant) as different design regimes.
3 Choose initial loop BW & stability target
Use BW to move the crossover: tighter tracking reduces VCO dominance; narrower BW reduces reference injection. Maintain adequate phase margin.
4 Bucket contributions
Separate Ref path, VCO path, and additive terms (PFD/CP, divider, coupling). Identify the dominant bucket before optimization.
5 Verify with aligned measurements
Compare “before/after” using identical windows, RBW/VBW discipline, and the same spur mask definition.

In-band vs out-of-band (dominance logic)

  • In-band: loop tracks the reference more strongly; reference quality and PFD/CP behavior often determine close-in performance.
  • Out-of-band: loop cannot correct VCO fast noise; VCO intrinsic PN and tuning sensitivity dominate.
  • Crossover control: increasing BW moves the crossover right; decreasing BW moves it left.
Quick check (trend first)

Sweep loop BW while holding the same jitter window; dominance should shift predictably near the crossover.

RMS jitter window discipline (avoid false comparisons)

Why different windows give different answers

Jitter is an integral over phase-noise density across frequency; changing bounds changes which region contributes most.

Three common traps
  • “RMS jitter” reported without bounds → not comparable.
  • RBW/VBW or smoothing changed → spur amplitude and floor appear to move.
  • A single PN offset point looks good → integrated jitter can still fail the window.
Pass/fail phrasing (recommended)

“RMS jitter ≤ target, integrated from fL to fH, with stated RBW/VBW and spur mask definition.”

Diagram: Noise transfer overlay (Ref low-pass + VCO high-pass)
Noise transfer overlay Curves show reference contribution shaped like a low-pass, VCO contribution shaped like a high-pass, and their sum. A vertical line marks loop bandwidth crossover between in-band and out-of-band dominance. Offset frequency Phase noise / density BW In-band Out-of-band Ref path VCO path Sum Crossover
Loop BW sets the crossover between reference-following behavior and VCO-dominant behavior; integrated jitter changes with the measurement window and the crossover position.

Integer-N PLL: why it’s clean, and where it hurts

Integer-N operation (α = 0) is often “clean” because modulation mechanisms are reduced and spur structure is more predictable. The cost is paid in frequency planning: resolution and reachable ratios depend heavily on the chosen fPFD and integer divider plan.

Best-fit scenarios

  • Spur mask is the primary driver and predictability is preferred over ultra-fine step size.
  • Output channels are fixed or tolerate coarser steps (frequency plan fits integer ratios).
  • Reference quality is strong enough to be tracked in-band without violating jitter window requirements.

Pain points (the cost)

Step size constraint
Frequency resolution is tied to fPFD and integer ratios; fine steps can force a lower fPFD or a different plan.
Reference planning pressure
The “best” fPFD for noise may conflict with reachable channel frequencies and divider limits.
Divider/PFD-related noise exposure
Divider and PFD/CP behavior can become dominant buckets in certain plans, especially near sensitive offsets.

Fast design recipe (Integer-N bring-up)

  1. Lock the spec language: jitter window bounds + spur mask offsets/settings.
  2. Pick fPFD by planning first: ensure all required channels are reachable with integer ratios.
  3. Initialize BW and phase margin: choose dominance (Ref vs VCO) using the transfer view; keep stability margin intact.
  4. Predict spur locations: ±fPFD and ±fREF families; check overlap with sensitive bands.
  5. Sweep grammar to locate sources: change fPFD/plan → spurs should move; change BW/Icp → amplitude should change.
  6. Validate under the same window: compare integrated jitter and mask pass/fail without changing measurement assumptions.

Deep dive (what usually dominates failures)

Reference spur anatomy
  • Paths: PFD/CP switching leakage, mismatch, finite isolation of loop filter, rail/return coupling.
  • Signature: discrete tones at ±k·fPFD and/or ±k·fREF families.
  • Quick check: change fPFD (or equivalent plan) and confirm spur positions move accordingly.
Divider noise folding (planning-sensitive)
  • Effect: divider/PFD timing uncertainty can become a measurable bucket at certain N plans.
  • Symptom: close-in region deviates from expectations without obvious VCO limitations.
  • Quick check: compare nearby integer plans that keep fOUT close; observe whether noise changes track the divider plan.
Diagram: Integer-N spur anatomy (spectrum + cause paths)
Integer-N spur anatomy Top panel shows simplified spectrum with carrier and spur families at offsets labeled ±fPFD and ±fREF. Bottom panel shows minimal PLL blocks and arrows from PFD/CP and supply/return coupling to spur artifacts at the output. SPECTRUM (simplified) Carrier ±fPFD ±fPFD ±fREF ±fREF Mask-driven CAUSE PATHS (minimal) PFD/CP leak / mismatch LOOP FILTER VCO tuning sens. DIV N OUT rail / return coupling
Integer-N spurs typically form predictable families tied to fPFD and fREF; bring-up should confirm spur movement under plan changes and amplitude sensitivity under loop/CP settings and coupling conditions.

Fractional-N PLL: fine steps, but spurs become a system problem

Fractional-N enables fine frequency steps and flexible channel plans, but it also introduces configuration-dependent spur structure. In practice, spur behavior becomes a system problem: it depends on frequency plan, fPFD, modulus, dithering, and analog nonlinearity and coupling that vary by channel.

Why Fractional-N is needed

  • Fine step size: channel raster demands steps smaller than an Integer-N plan can provide at the desired fPFD.
  • Flexible ratios: multi-band / multi-standard channels must be reachable without forcing a low-quality plan.
  • Platform SKUs: one hardware design must cover multiple output frequencies under a stable reference plan.

The cost (what changes in bring-up)

Fractional spurs (discrete tones)

Spur families depend on fPFD, modulus, dithering, and the exact fractional setting; channels can look completely different.

ΣΔ quantization noise shaping

Reducing discrete spur height often redistributes energy into the noise floor, affecting integrated jitter within the specified window.

Nonlinearity triggers (channel-sensitive)

Kvco sensitivity, CP behavior, leakage, supply ripple, and coupling can amplify certain tones only for specific channels and plans.

First three datasheet items to inspect

A Phase-noise plots

Use as a baseline for floor and close-in shape; confirm whether BW changes can shift dominance as expected.

B Spur tables / spur examples

Record test conditions (fPFD, dither mode, plan notes). Spur families are only comparable under stated conditions.

C PLL mode notes

Identify options that change spur behavior (fractional/integer boundary, dithering options, modulus constraints, lock detect behavior).

Why different channels look different (4 buckets)

Bucket 1: arithmetic structure

The fractional numerator/denominator pattern sets periodicity; spur families can rearrange even when fOUT changes slightly.

Quick check: compare equivalent plans (if available) and observe spur pattern reordering.
Bucket 2: fPFD / divider plan

Changing fPFD (or N plan) moves spur families; position movement is a strong classifier for spur origin.

Quick check: change fPFD and confirm spur offsets scale or shift predictably.
Bucket 3: analog nonlinearity

Kvco, CP mismatch/leakage, pushing/pulling, and ripple can amplify a particular tone in only a subset of channels.

Quick check: adjust BW / Icp and observe mainly amplitude change rather than offset movement.
Bucket 4: board coupling

Reference routing, digital IO activity, return paths, and load/termination can couple into the PLL and make spur visibility channel-specific.

Quick check: vary termination/load or supply filtering and observe spur sensitivity.

Bring-up sweep grammar (fast classification)

  1. Freeze measurement discipline: same jitter window, RBW/VBW, and mask.
  2. Sweep fPFD: classify families by spur offset movement.
  3. Toggle dither: observe “tone → spread” and any floor increase inside the same window.
  4. Sweep BW / Icp: observe mainly amplitude change (nonlinearity / coupling sensitivity).
  5. Sweep channels: record the worst channel and its trigger conditions for system acceptance.
  6. Bucket the root cause: Ref path / fractional arithmetic / nonlinearity / board coupling.
Diagram: Fractional spur map (concept)
Fractional spur map (concept) Conceptual spectrum map with different spur families: reference spurs, fractional spurs, and integer-boundary spurs. Includes knobs fPFD, modulus, and dither, plus a small channel A/B comparison to illustrate channel dependence. SPECTRUM MAP (concept) Offset Amplitude Carrier Ref spurs Frac spurs Integer-boundary CONFIGURATION KNOBS fPFD moves offsets Modulus sets pattern Dither spreads energy CHANNEL DEPENDENCE Channel A Channel B
Fractional spurs are plan-dependent and channel-dependent; classification is fastest when sweeping fPFD and dithering under a fixed jitter window and measurement settings.

ΣΔ modulator & dithering: why “spur vs noise floor” is a trade

ΣΔ modulation and dithering are best treated as engineering switches. Lowering discrete spur peaks can raise the broadband noise floor; the correct choice depends on whether the system is spur/mask-driven or integrated-jitter-driven within a specified window.

Three switches (make them explicit)

ΣΔ order

Changes how quantization energy is distributed; affects both spur texture and floor shape.

Dither (ON/OFF/strength)

Reduces discrete tones by spreading energy; can raise the floor and change integrated jitter in the window.

Modulus (denominator)

Sets periodicity and pattern complexity; strongly impacts spur structure and channel dependence.

Switch → metrics map (what moves)

Spurs
OFF tends to show taller discrete tones; changes in modulus/order can rearrange families by channel.
Noise floor
Dither and ΣΔ shaping can raise floor in some regions; always compare inside the same jitter window.
Lock / risk
Some modes increase sensitivity to nonlinearity and coupling; verify lock stability and repeatability during sweeps.
Verification discipline

Any ON/OFF conclusion must hold with identical window bounds and RBW/VBW; otherwise spur/floor comparisons are misleading.

When “spread the spur” is worth it

Spur/mask-driven systems

Dither is often beneficial when discrete tones violate a mask or fall into a sensitive band even if floor rises slightly.

Integrated-jitter-driven systems

Dither can be harmful if floor rise increases jitter inside the specified integration bounds; prioritize planning and spur relocation first.

Both sensitive

Use channel planning, fPFD, and modulus options to move spur families away from sensitive regions before relying on dither.

Practical ON/OFF comparison script

  1. Select the worst channel (largest spur or most sensitive overlap).
  2. Freeze measurement settings (window, RBW/VBW, mask, averaging).
  3. Measure dither OFF: record spur offsets and peak heights.
  4. Measure dither ON: check spur reduction and any floor rise.
  5. Compute jitter inside the same bounds: accept only if the system spec remains met.
Diagram: Dither OFF vs ON (spur vs floor)
Dither OFF vs ON: spur vs floor trade Two stacked spectrum panels compare dithering OFF and ON. OFF shows taller discrete spurs and lower floor. ON shows spurs reduced and spread with slightly higher floor. DITHER OFF vs DITHER ON Dither OFF Spurs ↑ Floor ↓ Dither ON Spurs ↓ Floor ↑ Offset Offset
Dither often reduces discrete spur peaks but can raise the noise floor; accept the trade only under the same jitter integration bounds and measurement settings used for the system requirement.

Loop bandwidth & stability: choosing BW, phase margin, and filter type

Loop bandwidth (BW) is best chosen by back-solving from system intent: tracking a reference (fast lock and close phase alignment) versus isolating reference noise (cleaner behavior). A stable plan ties BW, phase margin (PM), and loop-filter type to measurable symptoms and repeatable sweep actions across channels and plans.

BW selection: the four-question gate

  1. Tracking vs isolation: tight phase follow (tracker) or reference isolation (cleaner)?
  2. Reference noise quality: is the in-band reference close-in noise acceptable?
  3. VCO noise quality: does VCO noise dominate at mid/large offsets?
  4. Lock time requirement: how fast must lock/hop/settle complete?
Rule of thumb: push BW larger when tracking and lock time dominate; pull BW smaller when reference isolation or spur masking dominates.

Back-solve workflow: requirement → BW/PM/filter

  1. Classify the driver: spur/mask-driven or integrated-jitter-driven.
  2. Decide dominance: reference (in-band) vs VCO (out-of-band) noise.
  3. Pick a BW range consistent with dominance and with fPFD constraints.
  4. Apply lock/settle constraints: increase BW only if stability checks remain satisfied.
  5. Select filter type (2nd/3rd order) and set a PM target for robust repeatability across channels/plans.
Implementation note: any channel plan that changes fPFD, N, ICP, or Kvco must keep loop stability consistent; “works on one channel” is not acceptance.

Stability checklist (repeatable across plans)

Phase margin (PM) target

Use a PM target that tolerates Kvco and ICP variation and temperature drift; do not optimize for one “best-looking” channel only.

Quick check: change ICP or LF values slightly and confirm settling and spur behavior remain stable (no “mode cliffs”).
Zeros/poles placement

Ensure the chosen filter type keeps gain/phase behavior robust near the target BW; avoid parameter sets that are sensitive to component tolerance.

Quick check: step frequency/channel and compare settling traces under identical measurement conditions.
Nonlinearity and plan changes

CP leakage/mismatch, Kvco variation, and fPFD changes can shift effective loop gain; stability must survive the full channel plan.

Quick check: sweep fPFD and BW while holding the measurement window fixed; classify whether changes are “offset moves” or “amplitude moves”.

Loop filter type: 2nd vs 3rd order (engineering consequences)

2nd Simple and stable-first

Fewer knobs, easier to make robust across Kvco and ICP variation; may limit how aggressively settling and spur behavior can be shaped.

3rd More shaping power

Adds one more pole/zero degree of freedom; can improve settling behavior under certain plans, but increases sensitivity to tolerance and mode changes.

Acceptance rule: pick the simplest filter that meets worst-channel settling and spur/jitter requirements under full plan sweeps.

BW too large vs too small: observable symptoms

BW too large
  • Reference-related tones and artifacts become more visible near the carrier.
  • Output quality tracks reference quality strongly; “better ref” improves results more than “better VCO”.
  • Spur visibility changes noticeably with reference routing/isolation changes.
Quick check: reduce BW and confirm reference spur influence decreases while far-offset PN moves toward VCO behavior.
BW too small
  • Far-offset noise and frequency pulling look VCO-dominated.
  • Lock/settle time increases; channel hops may violate timing.
  • VCO supply and tuning-line ripple sensitivity becomes dominant.
Quick check: increase BW and verify improved lock/settle and reduced VCO dominance at mid offsets.
Stability red flag: “mode cliffs” (small BW/ICP changes cause large settling/spur changes) indicate marginal PM or strong nonlinearity/coupling.
Diagram: Tracker vs Cleaner BW decision
Tracker vs Cleaner BW decision Decision map comparing a tracker (large BW) and a cleaner (small BW). Includes a trade diamond and four decision capsules: tracking intent, reference noise, VCO noise, and lock time. LOOP BW DECISION: TRACKER vs CLEANER TRACKER Large BW Ref PLL Out Fast lock Tracks ref CLEANER Small BW Ref PLL Out Ref isolation Lower inj. trade FOUR-QUESTION GATE Tracking? Ref noise? VCO noise? Lock time?
BW is a system choice: tracker behavior favors fast lock and tight following, while cleaner behavior favors reference isolation. Always validate stability across the full channel plan.

Spur mechanisms playbook: root causes → quick checks → fixes

Spurs are diagnosable. The fastest classification uses two sweep axes: does the spur move with fPFD? and does it change with fractional settings (dither/modulus)? Each spur family below is presented as a three-line playbook: fingerprint, quick check, and fix action.

Type A: Reference spurs

Fingerprint

Symmetric tones appear at offsets tied to fPFD/reference-related families; visibility depends on reference routing and isolation.

Quick check

Sweep fPFD (plan change) and confirm spur offsets move proportionally.

Fix actions
  • Improve reference isolation and return continuity; reduce coupling into PFD/CP.
  • Adjust BW direction only after classification (do not “tune blind”).

Type B: Fractional spurs

Fingerprint

Spur pattern changes by channel; discrete families depend on fractional setting, modulus, and dithering.

Quick check

Toggle dither and confirm “tone → spread” behavior while holding jitter window and RBW/VBW fixed.

Fix actions
  • Use channel planning and fPFD choices to move families out of sensitive regions.
  • Choose dither only after confirming the integrated-jitter window remains within spec.

Type C: Supply / ground coupled spurs

Fingerprint

Spur amplitude tracks system state (load, switching modes, digital activity); sensitivity to filtering and return paths is high.

Quick check

Change PSU/load conditions or add temporary filtering and confirm spur amplitude changes without predictable offset movement with fPFD.

Fix actions
  • Isolate and filter the tuning line and charge-pump supply; enforce quiet returns.
  • Separate noisy digital returns from sensitive PLL/VCO control regions.

Type D: VCO pushing/pulling / AM-PM

Fingerprint

Spur amplitude correlates with tuning voltage ripple or VCO supply ripple; often more visible when VCO dominance increases.

Quick check

Change BW/ICP and improve VCO supply/tuning filtering; observe mainly spur amplitude changes (not fPFD-scaled offset moves).

Fix actions
  • Reduce ripple injection into tuning and VCO supply; strengthen local decoupling.
  • Validate worst-channel sensitivity under planned BW and channel plan sweeps.
Diagram: Spur root-cause tree
Spur root-cause tree Root-cause decision tree for observed spurs. First decision checks whether the spur moves with fPFD. Subsequent decisions check whether it changes with dither or modulus, and whether it changes with power or load state, leading to likely paths and fix actions. Observed spur Moves with fPFD? Likely path Reference Fix isolation / plan YES NO Changes with dither/mod? Likely path Fractional Fix plan / dither YES NO Changes with PSU/load? Likely path Supply/GND Fix filter / return YES Likely path VCO push Fix tune/VCO iso NO
Classify spurs by movement with fPFD, sensitivity to dither/modulus, and sensitivity to PSU/load state; then apply the matching fix bucket with minimal iterations.

Power, reference isolation, and PCB layout for low phase noise

A PLL usually fails on the PCB through a few repeatable coupling paths: ripple or interference on the VCO tuning node (FM), reference contamination (reference spur families), and supply/return noise injected into the charge pump or VCO. This section focuses only on actions that determine phase noise and spur outcome for a PLL clock chain.

Layout priorities (PLL-success essentials)

Must isolate (3 lines)
  • VCO tuning line (Vtune): ripple → FM → PN/spurs.
  • Reference input: contamination → reference spur families become visible.
  • VCO/CP supply: supply ripple → AM/FM conversion and spur growth.
Must be short/differential/controlled (2 paths)
  • Ref/clock-in routing into the PLL input buffer/PFD.
  • Clock output differential pair with correct termination and return.
Must avoid (3 failures)
  • Return current crossing a split/slot (broken return path).
  • Shared narrow return between PLL island and noisy digital currents.
  • Long control traces that pick up crosstalk into Vtune/CP nodes.

Why the tuning line dominates PN and spurs

The VCO converts tuning-voltage noise into frequency modulation. With high Kvco (Hz/V), even small ripple on Vtune can raise phase noise or create system-state-dependent spurs.

Quick checks
  • Probe Vtune ripple and compare against spur/PN changes with identical RBW/VBW settings.
  • Change load/PSU operating mode; if spur amplitude tracks state without moving with fPFD, injection is likely.
Fix actions (PLL-scoped)
  • Place the Vtune RC/LPF and any series isolation resistor close to the VCO control pin with a short return loop.
  • Use a low-noise supply strategy for VCO/CP (quiet LDO and local decoupling) and keep noisy rails out of the quiet island.

Reference isolation (layout-driven reference spur control)

  • Keep the reference route short and controlled; avoid passing near fast digital edges and switching rails.
  • Protect the reference return: do not force it to cross a split or share a thin neck with large digital currents.
  • Decouple the reference input buffer (or PLL input supply) locally to prevent supply-to-phase conversion.
Quick check

Sweep fPFD and confirm whether spur offsets move with fPFD-scaled families. If yes, prioritize reference path and PFD/CP coupling control.

LDO / filtering placement: where it matters (and where it doesn’t)

VCO supply

Use a quiet supply and short local decoupling loops near the VCO. Treat this as the highest priority “quiet island” rail.

Charge pump and loop filter rail

Prevent digital rail noise from modulating CP current or LF nodes; local isolation and decoupling reduce spur creation at the source.

Do not treat π filters as universal: only apply them at the quiet-island entry where isolation is required and where startup/voltage-drop side effects are acceptable.

Board-level pass criteria (layout success indicators)

  • No “mode cliff”: small BW/ICP/plan changes do not cause large settling or spur changes.
  • PSU/load state changes do not create large, uncontrolled spur growth on the clock output.
  • Vtune ripple remains below the allocated tuning-noise budget for the intended jitter/PN mask.
Diagram: Partitioned floorplan (quiet island + returns)
Partitioned floorplan for low PN PLL layout Floorplan partitions the PCB into Digital, PLL Core, VCO Quiet Island, and Clock IO. Highlights Vtune, Ref In, and Clk Out as critical routes with controlled returns. Shows quiet-island supply filters and recommended return paths, and marks three common failures: return crossing a split, shared narrow return, and crosstalk into Vtune. PARTITIONED FLOORPLAN: DIGITAL / PLL CORE / VCO QUIET ISLAND / CLOCK IO Digital PLL Core VCO Quiet Island Clock I/O CPU/FPGA DC/DC Noisy return currents PFD/CP Loop Filter VCO Vtune LPF Diff Out + Term Power filters VCO LDO CP ISO Ref In (controlled) Vtune Diff Digital return Star Avoid: split return Avoid: shared neck Avoid: Vtune pickup
Partitioning and return-path discipline are the fastest way to prevent tuning-line injection, reference contamination, and supply-coupled spurs that degrade phase noise.

Lock acquisition & dynamics: lock time, cycle slip, and mode switching

Lock speed, stability, and spectral cleanliness are linked. Faster acquisition often requires larger BW or fast-lock modes, which can increase spur risk or reduce stability margin. Robust systems treat lock as a two-stage process with measurable acceptance across the full channel plan and operating range.

What determines lock time

  • BW: larger BW usually reduces acquisition time but increases reference injection sensitivity.
  • fPFD and plan: comparison rate and divider plan affect dynamics and spur families.
  • VCO range / Kvco: insufficient range and high sensitivity create “mode cliffs”.
  • Calibration: auto-cal can shorten search but adds mode switching boundaries.
Measurement discipline: compare lock time and spectrum with identical trigger, window, and RBW/VBW to avoid false conclusions.

Cycle slip and long-tail settling

Symptoms
  • “Locked” status appears, but frequency/phase error continues to settle slowly.
  • Occasional abrupt jumps during settling that repeat on specific channels.
  • Strong sensitivity to small BW/ICP changes indicates marginal dynamics.
Quick checks
  • Capture the lock transient with a fixed time base and compare traces across channels/plans.
  • Sweep BW and verify whether the tail improves smoothly or exhibits “mode cliffs”.
Fix actions
  • Adopt a two-stage profile: acquire quickly, then settle with a stable PM/BW setting.
  • Eliminate parameter sets that only work on “easy channels”; validate worst-case plan corners.

Mode switching: where “fast” becomes noisy or fragile

  • Fast-lock to normal-switch can create a spectrum step (spur/PN discontinuity) if switching is not controlled.
  • Different channels may trigger different internal settings; the output can “change character” by plan.
  • Temperature-driven recalibration can reintroduce spur families if boundaries are not validated.
Quick check: correlate status/mode bits with spectrum snapshots before and after switching under identical measurement settings.

Dynamic strategies (PLL-internal only)

Fast-lock

Purpose: reduce acquisition time. Cost: higher spur risk and reduced stability margin during acquisition.

BW switching

Purpose: acquire with larger BW, then settle with smaller BW. Cost: switching transient and plan repeatability work.

Auto-cal

Purpose: reduce VCO-range uncertainty and stabilize plan corners. Cost: state-machine boundaries and temperature-edge behavior.

Dynamic pass criteria (measurable and repeatable)

  • Lock time meets the budget under the full channel plan and operating range.
  • Spectrum before/after switching does not violate spur/PN masks (no uncontrolled discontinuity).
  • After temperature drift and relock, the spectrum “character” remains consistent (no plan-specific surprises).
Diagram: Fast-lock profile concept (acquire → settle)
Fast-lock profile concept: acquire then settle Two-stage profile: Acquire uses a larger BW to reduce lock time, then Settle uses a smaller BW to reduce spur risk and stabilize spectrum. Includes three conceptual traces: frequency error, spur risk, and jitter floor, plus check capsules for verification. TWO-STAGE PROFILE: ACQUIRE (Large BW) → SETTLE (Small BW) Acquire Large BW Settle Small BW switch time Freq error ↓ Spur risk ↑ (acq) Jitter floor ↓ lock time ↓ during acquire spur risk ↑ during acquire settle stable small BW
Two-stage profiles reduce lock time while keeping final spectrum clean. Switching must be validated across the full plan to avoid mode cliffs and temperature-triggered surprises.

Engineering checklist: measurement, bring-up, and pass criteria hooks

This section is a reusable lab-and-production checklist. Each item is written as Measure / How / Pass. Thresholds marked as X must be filled from the system jitter/spur budget and the target mask.

A) Bring-up checklist (board must-do)

Ref integrity
Measure: fref, amplitude/common-mode, termination state
How: probe near the PLL ref pin/test point; verify termination/CM compliance
Pass: within datasheet limits; frequency error ≤ X ppm (system budget)
Plan correctness
Measure: fPFD and output frequency vs configuration
How: read back registers + cross-check with frequency measurement (no “register-only trust”)
Pass: fPFD and fout match plan; error ≤ X (Hz/ppm)
True lock vs “looks locked”
Measure: lock indicator + Vtune headroom + spectrum stability
How: confirm Vtune is not rail-hugging; capture spectrum before/after lock with fixed settings
Pass: Vtune has margin; no uncontrolled spectrum “character” changes (plan corners validated)
Supply & node health (PLL-scoped)
Measure: VCO/CP rail ripple and Vtune ripple
How: short ground probe technique near pins; record dominant ripple frequencies
Pass: ripple ≤ X (budget); state change does not cause large spur growth
Plan corners (minimum set)
Measure: lock + PN/spur snapshots at low/mid/high channels
How: pick ≥3 plan corners; save config + screenshot with identical RBW/VBW
Pass: no “mode cliff”; worst-case meets mask ≤ X

B) PN / jitter measurement checklist (chain + windows)

Input level & compression
Measure: analyzer input headroom / overload flags
How: insert attenuator; repeat with a second atten setting to detect compression artifacts
Pass: no compression; result structure stable across attenuation (Δ ≤ X)
Windows & reporting fields (must be explicit)
Measure: RMS jitter with stated integration window; PN offsets with stated RBW/VBW
How: lock the window (e.g., A–B Hz) and RBW/VBW; keep averaging consistent across runs
Pass: jitter(window A–B) ≤ X; repeatability within X
Noise floor separation
Measure: measurement chain floor vs DUT curve
How: baseline run (reference/short/known source); verify analyzer is not dominating the result
Pass: chain floor is lower than target by ≥ X dB over required offsets
Spur handling in jitter
Measure: jitter with spur included vs excluded (if allowed by spec)
How: document the policy and repeat both; use identical windows and settings
Pass: report matches system compliance rule; spur contribution is explainable and repeatable (≤ X)

C) Spur hunting checklist (sweep variables to assign ownership)

Sweep fPFD
Measure: spur offset family movement vs fPFD
How: change ref divider/multiplier; capture identical spectra
Pass: can classify “reference-related” vs “not” with confidence (ownership assigned)
Sweep fractional plan & modulus
Measure: channel-dependent spur map (offset + dBc vs channel)
How: sweep representative channels; log config snapshot for each capture
Pass: worst-case channel spur ≤ X dBc (mask) with repeatability
Toggle dither ON/OFF
Measure: spur height reduction vs noise floor rise
How: capture two spectra with identical settings and window policy
Pass: spur complies without pushing integrated jitter above X
Sweep BW / ICP
Measure: spur amplitude correlation with BW (in-band injection vs out-of-band)
How: step BW/ICP with small increments; watch for “cliff” behaviors
Pass: trend is smooth and predictable; final setting meets mask ≤ X
Stimulate supply / load state
Measure: spurs that follow PSU switching tones/harmonics
How: change DC/DC mode or load; compare spectra and node ripple measurements
Pass: spur ownership assigned to a supply/return path; mitigation reduces spur by ≥ X dB
Required spur log fields

For every observed spur: record offset, amplitude (dBc), whether it moves with fPFD / moves with fout / follows supply tones, and save the configuration snapshot (fPFD, N/frac, modulus, dither, BW/Icp).

Diagram: Measurement setup map (chain + injection points)
Measurement setup map for PLL PN/spur validation Instrument chain diagram: PLL output goes through optional attenuator and buffer/isolator, then splits to a phase noise analyzer and spectrum analyzer. Marks injection points: supply noise into the PLL board, probe ground loop risk, and Vtune sensitivity node. Shows reporting tags RBW/VBW and jitter window. MEASUREMENT SETUP MAP: CHAIN + INJECTION POINTS + REPORTING TAGS PLL Board PLL Out Vtune Supply In noise inj Attenuator Buffer/Isol. probe loop PN Analyzer Spectrum Analyzer Reporting tags (must log) RBW/VBW Jitter window Vtune is most sensitive Discipline to prevent false conclusions • Keep measurement settings identical across comparisons • Validate chain noise floor and input compression • Log window, RBW/VBW, plan snapshot, and spur policy
The same PLL can “measure differently” if the chain, input level, RBW/VBW, or jitter window changes. Make the setup and reporting tags part of the pass criteria.

Applications (kept tight): LO and system clocks — back-solve PLL choices from requirements

The goal here is only requirement translation: requirements → knobs → verification. It avoids system-level clock-tree design and stays scoped to PLL configuration and validation.

Use case A: LO synthesis (spur-sensitive)

Key requirements
  • Spur mask at critical offsets: spur ≤ X dBc
  • Phase noise at close-in and mid offsets meets budget
  • Channel plan consistency (no “bad channels” surprises)
Priority knobs
  • Prefer Integer mode when possible; otherwise control fractional spurs via modulus and dither
  • fPFD selection to position spur families and manage in-band injection
  • Loop BW to balance reference injection vs VCO dominance
Verification hooks
  • Channel sweep: build a spur map (offset, dBc) across plan corners
  • Change fPFD: confirm spur family movement is consistent
  • Dither ON/OFF: spur reduction vs noise-floor rise remains within budget

Use case B: System clocks (jitter-sensitive)

Key requirements
  • Integrated RMS jitter must specify window: (A–B) Hz
  • Jitter stability vs supply/load state and temperature
  • Repeatable compliance under identical reporting settings
Priority knobs
  • Loop BW chosen to minimize integrated jitter in the required window
  • Reference injection control (ref integrity + fPFD choices)
  • Vtune and VCO supply isolation to avoid ripple-to-FM conversion
Verification hooks
  • Lock the jitter window and RBW/VBW; compare apples-to-apples only
  • Change BW: confirm integrated jitter improves without introducing spur cliffs
  • Change supply state: verify jitter remains within budget ≤ X

Use case C: Multi-domain clocks (phase/skew repeatability)

Key requirements
  • Repeatable phase/skew after power cycles: skew ≤ X
  • Deterministic behavior across plan corners and temperature
  • No “phase cliff” when modes or channels change
Priority knobs
  • Phase step / output divider settings (if available) for deterministic alignment
  • Sync/reset sequencing to make start-up repeatable
  • Calibration boundaries: avoid temperature-triggered mode surprises
Verification hooks
  • Power-cycle statistics: collect skew distribution over N runs
  • Thermal relock test: confirm phase/skew returns to the same distribution
  • Channel sweep: check deterministic phase behavior across the plan
Diagram: Requirement → knob mapping (by use case)
Requirement-to-knob mapping by use case Three-column mapping: Use cases (LO synthesis, system clocks, multi-domain clocks) connect to PLL knobs (fPFD, BW, integer/fractional, dither, Kvco, Icp, sync/cal) which connect to metrics (spur mask, integrated jitter window, plan consistency, skew repeatability). Designed to back-solve PLL choices from requirements. USE CASE → KNOBS → METRICS (BACK-SOLVE THE PLL) Use case Priority knobs Key metrics LO synthesis spur-sensitive mask first System clocks jitter-sensitive windowed RMS Multi-domain phase/skew repeatability Integer/Frac dither fPFD BW BW / injection Vtune ref Icp Sync / Cal sync phase cal Spur mask offset families spur ≤ X dBc Integrated jitter window matters RMS ≤ X Skew/phase repeatability skew ≤ X
Use the mapping to choose the smallest set of knobs that move the right metric for the use case, then validate plan corners with fixed measurement settings.

IC selection logic: what to ask vendors & how to compare parts

This section turns “PLL performance” into comparable, vendor-ready fields. The goal is to prevent mismatched assumptions (integration window, spur masking, channel dependence) and make parts rankable by a consistent funnel: hard constraints → noise/spurs → integration/bring-up → cost/availability.

COVERS Comparable selection fields
  • Phase-noise/jitter reporting fields with explicit integration windows
  • Spur reporting fields including worst-case + channel dependence
  • PLL “capability knobs” that map to requirements and bring-up risk
NOT COVER Adjacent-topic deep dives
  • Dedicated jitter cleaners / timing cards architecture (kept on sibling pages)
  • CDR/DDS theory (kept off this page)
  • Generic EMI tutorials (only PLL-critical layout fields are listed)
FOR WHO Buy/compare with confidence
  • LO synthesizers (spur-sensitive masks)
  • System clocks (integrated jitter-sensitive budgets)
  • Teams needing predictable bring-up + debug hooks

A) Vendor ask-list (RFI fields) — make PLL claims comparable

Output PN / jitter (must specify window)
  • RMS jitter with bounds: fL to fH, include/ignore spurs flag.
  • PN plot offsets + conditions: carrier, output divider, mode (Int/Frac), Fpfd, loop BW.
  • Normalization: specify if values are “PLL-only” or include reference/buffer chain.
Compare rule
Reject any claim without explicit (fL,fH) and “spurs included?” label. Recompute jitter if windows differ.
Spur behavior (worst-case vs typical)
  • Spur table: max spur level across channel plan, not a single “hero” channel.
  • Channel dependence: “best/median/worst channel” or histogram across N values.
  • Spur mask support: ability to force integer mode, change modulus/dither, move Fpfd.
Compare rule
Rank by worst-case spur that violates the system mask; typical-only spur numbers are non-comparable.
PFD / N range / fractional capability
  • Max Fpfd in each mode (integer vs fractional) and any derating notes.
  • Fractional modulus, ΣΔ order, and dither controls (on/off, strength).
  • Integer-boundary mitigation features (multipliers, prescaler behavior, dividers).
Compare rule
Prefer parts that keep Fpfd high without exploding fractional spurs across the channel plan.
Loop filter / lock dynamics / calibration
  • External vs internal LF: component sensitivity, recommended ranges, stability limits.
  • Fast-lock, BW switching, and autocal options; specify lock-time conditions.
  • Cycle-slip reduction notes and “mode switching” settling guidance.
Compare rule
Lock time must be quoted with BW, calibration state, and temperature; otherwise values are not portable.
Outputs / supplies / debug hooks
  • Output standards: LVDS/LVPECL/LVCMOS/HCSL options, swing, termination needs.
  • Isolation pins: separate VCO/PLL rails, tuning pin filtering guidance, PSRR notes.
  • Debug: lock detect type, register readback, status flags, test modes, safe reset.
Compare rule
Prefer parts with observable states (status + dump) when bring-up time and field returns matter.
Practical vendor packet (copy/paste fields)
  • Target outputs: Fout list, output format, required power/swing
  • Reference: Fref, phase noise of ref (or part no.), allowable ref spur mask
  • Jitter budget: (fL,fH) + “spurs included?” flag + max RMS jitter
  • Spur mask: max spur level (dBc) within specified offsets and channel plan
  • Dynamic needs: max lock time, temperature range, frequency hop profile

B) Comparison funnel (ranking rule): hard constraints → soft trade-offs

Step 1 — Hard constraints (pass/fail)
  • Frequency coverage + divider plan matches Fout list
  • Output standard + swing + termination compatible
  • Supplies, package, temp grade, interface requirements
  • Reference range supports chosen Fpfd strategy
Step 2 — Noise/spurs (system mask)
  • RMS jitter meets budget for the same (fL,fH)
  • Worst-case spur meets mask across channel plan + corners
  • Fractional controls can “move” spurs away from sensitive offsets
Step 3 — Integration/bring-up risk
  • Loop filter flexibility and stable operating region
  • Lock dynamics support (fast-lock/cal) with predictable settling
  • Status/telemetry hooks reduce debug time (LD, readback, flags)
Step 4 — Cost & availability
  • Second-source options, lifecycle, PCN cadence
  • EVM/software maturity, register map stability
  • Board-level cost drivers (filters, clean rails, reference)
PLL IC Selection Funnel Trapezoid funnel showing ranking order: hard constraints first, then noise/spurs, then integration/bring-up, then cost/availability. Selection Funnel (rank order) Pass/Fail gates Hard constraints Freq range, outputs, rails Ref/PFD feasibility Package/temp grade 1) Hard constraints 2) Noise & spurs (system mask) 3) Integration & bring-up 4) Cost & availability Practical scoring rule Fail early on Step 1 Rank by worst-case mask Prefer strong debug hooks
The funnel enforces comparable claims: reject missing windows/masks, then rank by worst-case spur/jitter against the system budget.

C) Concrete material numbers (starting points only; verify suffix/package/stock)

The following part numbers are practical lookup anchors for datasheets/EVMs and not a recommendation. Final selection must be driven by the funnel above (system jitter window, spur mask, channel plan, and bring-up risk).

Wideband LO synthesizers (integrated VCO)
External-VCO PLLs (fractional-N / integer-N)
  • TI: LMX2492RTWR TI page
  • ADI: ADF4159 ADI page
  • Note: external VCO choices must be co-optimized (Kvco/pushing, tuning sensitivity, supply noise); compare PLLs only after locking VCO selection.
System clock generators (PLL-based, multi-output)
How to use the examples (fast)
  1. Pick 2–3 candidates that satisfy hard constraints (freq/outputs/rails/package/temp).
  2. Normalize the reporting window: force the same (fL,fH) and spur-inclusion convention.
  3. Evaluate worst-case spurs across the channel plan; reject typical-only spur claims.
  4. Prefer predictable bring-up: robust calibration + status readback + documented corner behavior.

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

FAQs: bring-up, spurs, phase noise, and measurement traps

Short, actionable troubleshooting for Integer-N / Fractional-N PLL only. Each answer is structured as Likely cause → Quick check → Fix → Pass criteria to keep results measurable and comparable.

Measurement baseline (use consistently)
  • Record mode (Integer/Fractional), Fref, Fpfd, loop BW, dither state, output frequency, and divider settings.
  • For jitter, always state the integration window (fL, fH) and whether discrete spurs are included.
  • Change only one knob per experiment (e.g., Fpfd or BW or dither) to keep root-cause attribution valid.
1) Why does a spur move exactly with Fpfd (or Fref) when channels are retuned?
Likely cause
Reference-related coupling (PFD/CP leakage, reference feedthrough, or divider boundary) creating spurs at ±k·Fpfd (or ±k·Fref).
Quick check
Hold output frequency constant and change Fpfd (via ref divider or prescaler). If spur offset tracks Fpfd linearly, the spur is reference/PFD-path dominated.
Fix
Increase isolation on ref/PFD inputs (termination, shielding, grounding), reduce CP leakage sensitivity (optimize loop filter node impedance), and move Fpfd away from sensitive offset bands if allowed.
Pass criteria
Worst-case spur at ±k·Fpfd within the specified offset band is ≤ X dBc across the channel plan and temperature corners (X set by the system mask).
2) Fractional mode meets jitter spec but fails spur mask—what knob first?
Likely cause
Fractional spurs are setting-dependent (modulus, ΣΔ behavior, Fpfd, dither). Jitter integrates wideband noise, while the mask is violated by discrete tones.
Quick check
Toggle dither (OFF→ON) and retest spur levels at the violating offsets. If the main spur collapses but the noise floor rises slightly, the spur is fractional-quantization dominated.
Fix
First try: dither ON (or stronger dither). Next: adjust Fpfd to move fractional spur families away from sensitive offsets; then refine modulus/step plan to avoid “bad channels”. Use integer mode where the mask is strict and step size allows.
Pass criteria
Across the channel plan, all discrete tones inside the mask bands are ≤ X dBc, while integrated jitter in the required window (fL,fH) remains ≤ Y.
3) Dither reduces the main spur but noise floor rises—when is that acceptable?
Likely cause
Dither spreads fractional quantization energy: discrete tones drop, but the integrated wideband noise floor increases.
Quick check
Measure two metrics in the same setup: (1) worst discrete spur inside the mask band; (2) integrated jitter over the system window (fL,fH), with the “include spurs” rule explicitly noted.
Fix
Enable dither if the system is spur-limited (spur mask violations dominate). Prefer dither OFF if the system is jitter-limited and discrete tones are already below mask (or not in-band of interest). If both matter, re-plan Fpfd/channels to reduce tones without excessive dithering.
Pass criteria
With dither ON, worst spur improves by ≥ Δ dB to meet the mask, while integrated jitter increases by ≤ δ% and still remains under the budget.
4) Integer-N looks clean but step size is too coarse—how to re-choose Fpfd safely?
Likely cause
Integer-N step size equals Fpfd (or a related gcd of the plan). Coarse steps result from a low Fpfd chosen for other constraints.
Quick check
Enumerate feasible Fpfd candidates from the reference path and divider limits. For each candidate, check: (a) step granularity, (b) expected reference spur offsets, (c) loop filter feasibility (BW/PM).
Fix
Increase Fpfd to achieve the desired step size while keeping reference spurs outside sensitive bands and maintaining stable loop BW/phase margin. If Fpfd cannot be increased safely, use fractional mode only for channels that require fine steps.
Pass criteria
Required frequency grid is met (step ≤ S), while worst-case reference-related spurs at ±k·Fpfd remain ≤ X dBc and loop remains stable (PM ≥ P°).
5) PN meets spec at room temp but worsens across temperature—VCO pushing or reference?
Likely cause
Temperature changes either (a) increase VCO sensitivity to supply/control-line noise (pushing/pulling), or (b) degrade reference quality (TCXO/OCXO behavior, supply sensitivity) that passes through the loop.
Quick check
Repeat PN at two loop BW settings: a “tracker” BW (higher) and a “cleaner” BW (lower). If close-in PN follows the reference more at high BW, it is reference-dominated; if far-out PN worsens regardless of BW, suspect VCO pushing/control-line noise.
Fix
For reference-dominated cases: improve ref supply isolation/termination and reduce loop BW. For VCO-dominated cases: harden VCO rail filtering, shorten/quiet the tuning line, and reduce tuning-line ripple in the sensitive bands.
Pass criteria
Over the temperature range, PN stays within spec at the key offsets (e.g., 10 Hz–1 kHz close-in and 100 kHz–10 MHz far-out), and integrated jitter in (fL,fH) remains ≤ Y.
6) Why does changing loop BW change both in-band noise and spur levels?
Likely cause
Loop BW reshapes the transfer: reference noise is low-pass, VCO noise is high-pass. BW also changes how strongly periodic error sources (PFD/CP ripple) appear at the output, altering spur magnitudes.
Quick check
Sweep BW across 2–3 settings while holding Fpfd and output frequency fixed. Track (a) integrated jitter in the same (fL,fH) window, and (b) a spur family at ±k·Fpfd.
Fix
Choose BW by dominance: reduce BW if reference/noise or reference spurs dominate; increase BW if VCO noise dominates and spur mask remains satisfied. Maintain phase margin (PM) and avoid loop-filter impedances that amplify CP ripple.
Pass criteria
Selected BW meets both: integrated jitter ≤ Y in (fL,fH) and worst-case spurs within the mask bands ≤ X dBc, with stable loop (PM ≥ P°).
7) Lock is stable, but close-in PN is worse than datasheet—what 3 layout/power checks first?
Likely cause
Board-level noise is being converted to phase noise (typically via the VCO rail or tuning line). Datasheet plots often assume an ideal reference, ideal supplies, and clean measurement fixtures.
Quick check
Check these three first: (1) VCO rail ripple (broadband + at switching frequencies), (2) tuning-line ripple/noise at the loop-filter node, (3) ref input integrity (termination, return path, isolation from digital clocks). Compare PN before/after temporarily powering the VCO rail from a cleaner lab supply (if safe).
Fix
Add/optimize local low-noise regulation and high-frequency decoupling at the VCO rail, shorten and shield the tuning node, isolate ref routing from high-slew digital nets, and avoid shared return paths that inject digital current into the PLL quiet area.
Pass criteria
Close-in PN improves by ≥ Δ dB at key offsets (e.g., 10 Hz–1 kHz) and meets the system requirement; tuning-line ripple in the sensitive band is ≤ X mVrms.
8) Why do spurs appear only at certain output frequencies (channel-dependent spurs)?
Likely cause
Fractional settings create discrete spur families that depend on N, modulus, ΣΔ state, and divider boundaries; some channels align spurs into sensitive offsets or excite nonlinearity.
Quick check
Build a channel sweep table: for each channel, log N/modulus/dither, worst spur level and offset. If spur “hot spots” repeat at specific fractional patterns, it is configuration/channel-plan related.
Fix
Re-plan channels to avoid known “bad” fractional patterns, shift Fpfd to move spur families, enable dither where spur masks are tight, or force integer mode for the most sensitive channels.
Pass criteria
For every channel in the plan, worst spur within mask bands is ≤ X dBc; no “hot spot” channel exceeds the mask at any corner condition.
9) Fast-lock reduces lock time but leaves long settling—how to verify mode switch artifacts?
Likely cause
Fast-lock or BW switching can leave residual charge/pulse artifacts on the loop filter node, causing a long tail in phase/frequency settling even after “lock” indicates stable.
Quick check
Trigger on the mode-switch event (fast-lock→normal). Monitor (a) tuning node voltage vs time, and (b) output spur/PN snapshots at fixed delays (t=1 ms, 10 ms, 100 ms). Long settling shows as slow tuning-node decay and/or time-varying spurs.
Fix
Reduce fast-lock aggressiveness (shorter duration or smaller BW jump), add controlled discharge/bleed per vendor guidance, and ensure loop filter component tolerances keep phase margin healthy in both modes.
Pass criteria
After mode switch, frequency/phase settles within T (ms) to within ±Δ (ppm or Hz), and spur/PN meet limits with no time-dependent drift.
10) Jitter numbers differ between instruments—what integration window mistake is most common?
Likely cause
Different (fL,fH) integration bounds, different spur-handling (include/remove), or different RBW/averaging leading to inconsistent spur energy and noise integration.
Quick check
Force both instruments to the same: (1) fL and fH, (2) spur inclusion policy, (3) comparable RBW/VBW and averaging. Re-run and compare the PN overlay at key offsets.
Fix
Standardize a single reporting template: jitter window, spur policy, RBW/VBW, averaging, and carrier power. Use that template for all vendor comparisons and lab reports.
Pass criteria
Under a matched template, jitter results agree within ±Z% (or ±Z fs) and PN overlays match within ±A dB across the key offset range.
11) Why does improving supply filtering help spurs but sometimes worsen lock behavior?
Likely cause
Added filtering can reduce supply-coupled spurs, but can also introduce supply droop/slow dynamics during lock acquisition or interact with load transients, degrading lock time or causing occasional unlock.
Quick check
Measure rail transient during lock: capture VCO rail and PLL core rail when enabling PLL and during frequency hops. If droop/undershoot correlates with unlock or long lock time, filtering/regulation dynamics are the culprit.
Fix
Use a low-noise regulator with adequate transient response, place HF decoupling at the IC pins, and avoid overly large series impedance that causes droop under dynamic load. Separate VCO rail filtering from noisy digital rails.
Pass criteria
Supply-coupled spurs drop below X dBc, while lock success rate is ≥ 99.9% and lock time stays ≤ T under worst-case hop and temperature.
12) How to tell reference coupling from VCO control-line noise in a quick lab test?
Likely cause
Reference coupling creates spurs that track Fpfd/Fref. Control-line noise creates FM on the VCO and often correlates with tuning-node ripple and supply switching frequencies.
Quick check
Test A: change Fpfd while holding output constant—reference-coupled spurs move with Fpfd. Test B: inject a small controlled ripple onto the tuning node (via a large resistor) and observe whether spur/PN responds strongly—high sensitivity indicates control-line dominance.
Fix
If reference-coupled: improve ref routing/termination/isolation and reduce leakage paths. If control-line dominated: reduce tuning-node impedance where appropriate, improve loop filter grounding/return, and minimize ripple on VCO rail and tuning node.
Pass criteria
Spur families are correctly classified (track Fpfd vs correlate with tuning ripple), and applied fixes reduce the dominant spur family by ≥ Δ dB to meet the system mask.
icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.