This page shows how to build direct-RF DAC and RF-synth clocking that passes a spur mask (not just a jitter number), while keeping SYSREF-based phase repeatability stable across re-lock, temperature, and traffic states.
The workflow is: identify whether the failure is spur-limited or PN-limited, trace the spur to its true origin (ref / fractional / power / activity / layout), then apply the shortest isolation and fix path with measurable pass criteria.
Definition & Scope: “Low-spur clocks” for Direct-RF DAC and RF Synth
This page defines low-spur clocks in the Direct-RF context and sets strict boundaries to avoid cross-page overlap.
The focus is discrete spurs + repeatability (not only a single RMS-jitter number).
A) Core vocabulary (non-negotiable definitions)
Spur (discrete line): a narrow tone at a specific offset/frequency (e.g., reference leakage, fractional-N spur, coupling, DDS image).
In Direct RF, a single spur can violate a mask even when noise floor looks acceptable.
Phase noise (continuous floor): the broadband skirt around the carrier described by the phase-noise curve (dBc/Hz vs offset).
It drives modulation noise (EVM/ACLR) through integrated phase error over defined windows.
Deterministic jitter: periodic or pattern-correlated timing/phase modulation.
It often appears as symmetrical sidebands or discrete tones, and should be treated as “spur-like” for acceptance.
B) What “low spur” means on this page
Low spur means discrete spur lines stay below the system’s spur mask within the offsets/bandwidths that matter for Direct RF
(reference leakage / fractional spurs / images / coupling products). The acceptance must be expressed in dBc vs offset or as a mask (not as a single “jitter” number).
C) What “low phase noise” means on this page
Low phase noise means the PN curve meets the RF modulation budget over relevant offset regions (close-in vs far-out),
and any integrated phase/jitter metric explicitly states the integration window. Without the window, numbers are not comparable.
D) SYSREF cooperation (DAC-side scope only)
On this page, SYSREF cooperation is treated as a repeatability anchor for deterministic phase/latency behavior
(e.g., consistent phase after re-lock / re-boot). It is not a protocol tutorial.
In scope: SYSREF edge placement, distribution skew sensitivity, arming/trigger timing, and repeatability acceptance.
Out of scope: JESD204 subclass mechanics, LMFC details, elastic buffer behavior (link to the dedicated JESD204 page).
Diagram: Direct-RF chain overview (spur vs PN vs SYSREF timing)
The diagram emphasizes three distinct acceptance categories: spur lines, PN floor, and SYSREF timing repeatability.
Why It Matters: Spur-dominated failure modes in Direct RF conversion
Direct RF systems often fail because of one deterministic spur, not because the broadband noise floor is marginal.
A “great jitter number” can coexist with a single mask-violating tone.
In-band SFDR: one line sets the limit even when the noise floor is low.
Mirror / image suppression: spur-aligned products appear at predictable offsets and survive averaging.
Regulatory emissions: narrow peaks can dominate compliance even if total power is low.
B) A practical rule: “jitter is fine” does not imply “spur is fine”
RMS jitter and integrated phase error often compress information into a single number.
Direct RF acceptance is frequently mask-driven: a single deterministic line can fail the mask even when integrated metrics look excellent.
The fastest mindset shift: treat each observed tone as a fingerprint that must be classified
(tracks reference, tracks fractional setting, tracks load/activity, or tracks layout coupling).
C) Symptom → Fingerprint → First check (quick isolation)
Symptom
ACLR/ACPR fails due to one narrow line
Fingerprint
Tone stays fixed vs output level; persists with averaging
Quick check
Nudge reference frequency and confirm whether the tone shifts by the same delta
Likely bucket
Reference leakage / coupling
Symptom
Spur moves when fractional settings change
Fingerprint
Offset/pattern changes with numerator/denominator mapping
Quick check
Freeze integer mode (if possible) or vary frac word while holding output near-constant; compare spur map
Likely bucket
Fractional-N spurs / quantization patterns
Symptom
Bench CW passes, real traffic fails
Fingerprint
Tone amplitude correlates with SERDES/FPGA activity state
Quick check
Repeat measurement while toggling traffic modes; log spur delta between states
Likely bucket
Digital coupling / supply modulation / crosstalk
Symptom
Cleaner output passes, DAC output fails
Fingerprint
Spur appears only after distribution/receiver/local supplies
Quick check
Probe at the DAC clock pin (not only at the source); compare spur maps at P1 vs P2
Likely bucket
Local coupling / termination / return-path mixing
The isolation list stays “first-check only” to keep this section diagnostic and avoid spilling into the full taxonomy and debug workflow.
D) Success criteria preview (what “good” looks like later)
Mask pass: discrete spurs below the declared spur mask in defined offsets.
Declared PN window: PN targets stated with offset points and/or an integration window.
Repeatability: after N re-locks/reboots, key spurs and phase alignment remain within thresholds.
Real-load condition: checks repeated under representative traffic/activity states, not only bench CW.
Diagram: Same noise floor, one spur can still fail the mask
The acceptance lens here is mask-first: a single spur can dominate even when broadband noise looks similar.
Direct RF designs typically require three coordinated paths from a reference source:
DAC clock (sampling timing), LO/synth reference (RF purity), and SYSREF/trigger (repeatable phase/latency).
This section stays system-level and avoids distribution/fanout device details.
A) Three-path roles (what each path must guarantee)
DAC clock path
Keeps sampling timing clean at the receiver pin (not only at the source). Acceptance is typically spur mask + declared PN window.
LO / synth reference path
Sets RF purity and spur structure through the synthesizer chain. The goal is low reference leakage + controlled fractional patterns in the offsets that matter.
SYSREF / trigger path
Anchors repeatability: deterministic phase/latency behavior after re-lock/reboot. Focus is edge integrity, distribution skew sensitivity, and receiver timing window.
B) Share one reference vs isolate domains (decision rules)
Prefer shared REF(coherence-first)
Multi-channel coherence is a hard requirement (beamforming, phase-aligned carriers, coherent test).
Frequency plan can avoid critical offsets where reference leakage would cross the mask.
Power/ground isolation is engineered so shared reference does not become a coupling highway.
Prefer isolated domains(spur-first)
A specific victim chain is extremely spur-sensitive (mask violations occur as narrow deterministic lines).
Traffic/activity causes failures (bench CW passes but real workload fails), indicating coupling paths exist.
Local receiver conditions dominate (cleaner output passes, but spur appears at DAC clock pin).
Common REF, separate clean domains(balanced)
A frequent compromise is a shared reference source with separate cleaning/isolation per path,
plus a SYSREF distribution that prioritizes edge integrity and receiver-window compliance.
C) Multi-card systems (master/slave + calibration hooks)
Distribution intent (system-level)
Master provides REF and a repeatability anchor (SYSREF/trigger).
Slave boards expose measurement and trim hooks (phase readback, controllable delay/phase trim).
Calibration parameters are stored (NVM/EEPROM) and validated after re-lock.
Key spur map snapshots at defined offsets (same RBW/avg settings each run).
Temperature points and activity states (idle vs traffic) attached to each run.
White-Rabbit/PTP/GNSS disciplining belongs to the timing pages (linked), not expanded here.
D) Bring-up sequence (shortest path to a stable baseline)
Confirm the architecture choice: shared REF vs isolated domains. Document which path is expected to be the spur “victim.”
Verify receiver-pin reality: compare spur maps at source output vs receiver pins (DAC clock pin and LO reference input).
Validate SYSREF at the receiver: edge integrity and window compliance, then run N re-lock cycles and record repeatability statistics.
Repeat under representative activity states (traffic/patterns). Treat “bench CW pass / real-load fail” as a coupling signature.
Default probe points: P1 Cleaner out · P2 DAC clock pin · P3 LO ref in · P5 SYSREF at receiver · RF out (mask)
Detailed distribution device selection and termination patterns belong to Distribution & Fanout.
Diagram: Three-path cooperation (Clock / LO Ref / SYSREF)
The architecture is defined by three coordinated paths and two system hooks: deterministic latency and phase alignment.
Key Specs That Actually Control Spurs (and how to read them)
Specs must be actionable: defined offsets, declared integration windows, and mask-based acceptance.
For Direct RF, spur masks and repeatability often dominate over a single RMS-jitter number.
A) Phase-noise curve: which offsets matter (Direct RF reading)
Close-in offsets
Typically correlate with slow phase modulation and near-carrier quality. If the system is mask- or EVM-sensitive near the carrier,
close-in PN must be explicitly bounded at stated offsets.
Far-out offsets
Typically correlate with broadband noise floor contributions. Far-out PN often shows up as raised skirts/noise density across wider offsets.
It must be controlled where the system integrates phase error.
Rule-of-thumb (writing the spec)
State PN at multiple offsets (not one point).
Tie the integration window to the system’s verification method.
Use mask language for acceptance where discrete tones can dominate.
B) Integrated jitter/phase error: integration window is mandatory
Non-comparable number (avoid)
RMS jitter = 120 fs
Actionable number (required)
RMS jitter (12 kHz–20 MHz) = 120 fs
For Direct RF acceptance, a low integrated metric is not sufficient if a deterministic line crosses the mask.
Use integration window + spur mask as the default contract language.
C) Spur metrics: record format that enables fast classification
A spur should be logged as a structured record so it can be classified quickly (reference leakage, fractional pattern, image, or coupling product).
Spur record (minimum fields):
– Level: ____ dBc
– Offset: Δf = ____ (from carrier)
– Tracking: follows {REF / FRAC / load / activity / temperature}?
– Condition: mode, RBW/avg, temperature, traffic state
– Location: observed at {Cleaner out / DAC pin / LO ref in / RF out}
SYSREF is a repeatability anchor, not “just a pulse.”
On the DAC side it must support deterministic phase/latency behavior across re-locks and reboots.
Protocol mechanics belong to the JESD pages; this section stays at receiver-window and edge-quality requirements.
A) What SYSREF must guarantee (DAC-side contract)
Repeatable phase relationship
The phase relationship among NCO / DAC / FPGA timing is reproducible after N bring-ups.
Window compliance at receiver
The SYSREF edge arrives inside the receiver’s allowed window relative to the DAC clock edges (not “nearby,” but inside bounds).
Bring-up determinism
“Arming → SYSREF → lock complete” is sequenced so the alignment state does not depend on random async phase at power-up.
Diagram: SYSREF vs DAC clock vs LO reference (window + Δt tolerance)
The focus is receiver-window compliance and Δt tolerance, not “pulse presence.”
Spur Source Taxonomy: treat spurs as a fault tree
A spur is a discrete line; the fastest path to a fix is correct classification.
Use tracking questions (REF / FRAC / load / activity / temperature) and probe-point discipline (P1/P2/P3/RF out) to avoid chasing the wrong mechanism.
A) Why a fault tree (classification drives the repair path)
The same spur at different points can imply different causes (source vs victim vs mixing).
Discrete lines often dominate masks even when broadband metrics look excellent.
Tracking-based splits turn “mystery tones” into repeatable decision steps.
B) Root questions (fastest split of the search space)
Q1: Tracks REF?
Nudge reference frequency or reference-related settings; confirm whether spur offset moves by the same delta.
Q2: Tracks FRAC?
Change fractional settings (numerator/denominator mapping); check if the spur map reorders in a repeatable pattern.
Q3: Tracks load / activity?
Toggle traffic/processing states and load conditions; log spur delta between states using identical RBW/avg.
Diagram: Spur fault tree (tracking → probe → action)
The tree is intentionally “first-check only” to keep classification actionable without expanding into cross-page theory.
Budgeting Workflow: from RF requirements → clock PN/spur requirements
This workflow converts RF specs (EVM/ACLR/ACPR, channel bandwidth, carrier, and spur mask) into
actionable clock targets:
offset-based phase-noise goals (dBc/Hz at key offsets) plus discrete spur limits (dBc at specific offsets).
The intent is to avoid “one RMS jitter number” decisions that miss spur-dominated failures.
A) Inputs (RF-side) — use a fixed field template
RF quality targets
EVM, ACLR/ACPR (or emission mask), plus the required measurement conditions.
Waveform context
Channel bandwidth, modulation class, carrier region, and output power state(s).
Spur mask (mandatory)
Allowed discrete lines in offset form: dBc @ Δf (and any “no-go” offsets).
Mode set for guardband
Frequency plans, sample rates, temperature range, rail range, and traffic/activity states.
B) Step-by-step flow (turn specs into targets)
Step 1Decide: spur-limited or PN-limited
Compare the RF mask margin: if a single line dominates the failure, treat it as spur-limited.
If the skirt/noise floor dominates adjacent leakage, treat it as PN-limited.
Step 2Set spur targets directly from the spur mask
Convert “allowed lines” into a target table: dBc at required Δf, plus “forbidden offsets.”
Keep each entry tied to a verification point (P1/P2/RF out) and measurement settings.
Step 3Translate RF sensitivity into PN offset targets
Define representative offsets for close-in and far-out regions.
Close-in targets typically protect modulation quality (EVM/near leakage), while far-out targets protect wideband skirts.
Guardband is mandatory because spur maps and PN can shift with temperature, rail noise, and fractional ratio changes.
Final targets must be worst-case across the declared mode set.
Step 5Lock the verification plan (points + settings + repeats)
Each target must have: probe location, RBW/averaging, activity state, and a repeatability condition (e.g., N bring-ups).
The output is a test-ready plan, not a narrative.
C) Practical heuristics (close-in vs far-out PN; spur dominance)
If adjacent leakage rises smoothly
Treat as PN-limited. Prioritize close-in offset targets for modulation fidelity.
If one or few discrete lines hit the mask
Treat as spur-limited. Use offset-based spur targets and classify sources by tracking.
If performance changes across states
Suspect coupling (rails/ground/activity). Compare identical RF/clock measurements across states before changing architecture.
Implementation Hooks: isolation, power integrity, and routing (spur-centric only)
This section keeps only the layout and power hooks that directly create or amplify discrete spurs.
Each hook is written as: Fingerprint → Quick check → Fix → Pass criteria.
Generic PCB routing theory belongs to the PCB/Routing pages.
A) Power-domain isolation (Ref / PLL / DAC-clock)
Fingerprint
Spur level changes with load states or regulator switching components; idle vs traffic produces a measurable delta.
Quick check
Toggle activity/load; log spur delta at P1 (cleaner out), P2 (DAC pin), and RF out under identical RBW/avg.
Fix
Separate rails/returns for reference and clock blocks; apply targeted filtering at the victim supply entry; keep high-dI/dt loops away.
Pass criteria
Worst-case spur across the declared mode set remains below the spur mask with defined margin.
B) Ground and return-path control (avoid digital return crossing clock loops)
Fingerprint
Spur is sensitive to probe ground, cable routing, or touch; “same” measurement changes with grounding details.
Quick check
Repeat measurements with a controlled short ground spring at the same point; compare stability across re-plugs and cable paths.
Fix
Provide continuous reference planes under sensitive nets; prevent return paths from detouring around splits/slots; shrink loop areas near victims.
Pass criteria
Spur mask pass is repeatable across N bring-ups and robust to benign handling/cabling changes.
C) Routing and termination (spur and coupling consequences only)
Fingerprint
Spur appears or grows at the DAC clock pin (P2) but not at the source (P1), indicating a local victim-side mechanism.
Quick check
Compare P1 vs P2 waveforms; look for ringing/edge distortion changes across modes; check for stubs and unused branches.
Fix
Remove stubs, enforce proper termination, preserve differential symmetry, and keep aggressors away to reduce mode-dependent injection.
Pass criteria
Spur level at P2 remains stable across modes and stays below the spur mask margin at RF out.
D) Physical isolation (LO ↔ DAC clock mixing paths)
Fingerprint
Spurs correlate with LO amplitude or proximity; tones resemble mixing products rather than pure reference tracking.
Quick check
Change LO power (or enable/disable LO path) and log spur delta; compare P2 changes vs RF out changes.
Fix
Enforce keepouts between LO and clock islands; add ground fencing/shielding; avoid parallel adjacency and shared return corridors.
Pass criteria
Spur mask pass holds across LO power states and operating modes with repeatable results.
E) Minimal bring-up checklist (spur-centric)
– Lock the measurement settings (RBW/avg/span) before comparing states
– Always compare P1 vs P2 vs RF out to localize source vs victim
– Log activity states (idle/traffic) and rail conditions for every capture
– Check stub/branch existence on victim nets (clock/SYSREF/LO ref)
– Confirm keepouts and return-path continuity in sensitive corridors
– Repeat N bring-ups; require repeatability, not a single “golden” run
The goal is a short isolation path that identifies whether a problematic spur
is reference-related, fractional/activity-related, or power/ground-coupled. The workflow focuses on
controlled single-variable changes and consistent measurement settings, so results are comparable and repeatable.
A) Tool choice (use the fastest instrument that answers the question)
Spectrum analyzer (SA)
Use when the failure is a discrete line against a spur mask: track tone movement vs knob changes.
Phase noise / jitter tool
Use when a noise skirt dominates leakage: compare close-in vs far-out regions across states.
Oscilloscope (victim-side)
Use to compare P1 vs P2 edge integrity and termination behavior when spurs appear only at the victim pin.
B) Mandatory probe points (compare, do not guess)
P1 · Cleaner output
Source-side baseline. If the spur is absent here but present at P2/RF out, treat as victim-side injection or mixing.
P2 · DAC clock at pin
Victim-side truth. Compare to P1 to separate “generated” vs “injected at the endpoint.”
P3 · LO ref / synth ref
Check mixing paths: if spurs correlate with LO settings, treat as LO↔clock coupling or intermod products.
P4 · Power ripple (victim rails)
If spur level tracks ripple amplitude or switching components, prioritize power/ground coupling fixes.
P5 · SYSREF / trigger
Isolate whether synchronization edges create repeatable activity patterns that appear as discrete lines.
Expected signature: if the spur tracks ref (offset/location follows ref changes),
classify as reference-related leakage or ref-path injection.
Step 2Change fractional / NCO / activity state
Expected signature: if the spur tracks ratio or activity (moves with fractional settings
or appears only under traffic), classify as fractional spur or digital modulation/coupling.
Step 3Change load / rails / switching state
Expected signature: if the spur tracks load or ripple (level changes with rail ripple or load),
classify as power/ground coupling or return-path mixing.
Hold SYSREF quiet (disconnect or inhibit) and compare to a controlled SYSREF sequence (single pulses or periodic bursts).
Interpretation
If the spur appears only when SYSREF activity is present (or becomes repeatably stronger/weaker),
treat SYSREF as a trigger for deterministic injection and prioritize distribution skew/edge placement checks.
E) Pass criteria (make results comparable and repeatable)
– Fix RBW / avg / span before comparing states
– Compare P1 vs P2 vs RF out to localize source vs victim
– Require spur mask pass with margin across declared modes
– Require repeatability: N warm boots / cold boots / re-locks
– Record activity state and rail conditions for every capture
Multi-device Coherence: phase alignment, drift, and re-lock repeatability
In multi-channel or multi-card direct RF systems, success requires more than “one good spectrum.”
The system must preserve coherent phase relationships and keep spur/mask pass repeatable
across boot and re-lock events and across temperature. This section defines a statistics-first validation approach.
A) Multi-DAC phase budget (skew + drift) and how to measure it
Budget components
Separate static distribution skew, deterministic latency variation after re-lock, and thermal drift over time.
Track each component independently to avoid masking the real limiter.
Measurement rule
Measure relative phase error between channels under the same reference and activity state.
Evaluate distributions (min/typ/max), not single snapshots.
A system may pass spur masks on a single run but re-lock into different deterministic phase states,
breaking coherence-dependent calibration or combining performance.
Statistics-first definition
For each scenario (warm boot, cold boot, re-lock), repeat N times and log:
phase error distribution, spur mask pass, and the exact operating state (ratios, activity, rails).
C) Thermal and aging hooks (observe first; compensate later)
Observe
Place temperature sensors near the reference/PLL and near the DAC. Log lock state, ratios, and calibration version for each run.
Control hooks
Use repeatable arming/trigger ordering and consistent state transitions. If external timing (WR/PTP/GNSS) is used, treat it as an external dependency and validate separately.
D) Acceptance rule (coherence is a matrix, not a single measurement)
– Define scenarios: warm boot / cold boot / re-lock / temperature sweep
– For each scenario: repeat N times and log phase error + spur mask pass
– Pass only if: phase error stays within budget AND spur pass is repeatable across the matrix
Diagram: Repeatability matrix (boot/relock/temp vs phase error / spur pass)
This section converts “low spur + repeatable phase state” into three practical gates. Each gate has checkable items,
clear pass criteria, and the minimum evidence to capture for fast debug and production traceability.
A) Design Gate — lock definitions, topology, and observability
Metrics are comparable
PN offsets, jitter integration limits, and spur expression (dBc @ offsets) are explicitly stated and shared across teams.
Spur mask is defined
A system mask exists (allowed lines by offset / band). “RMS jitter only” is not accepted as a go/no-go criterion.
Reference partition is intentional
Rules for “shared reference” vs “separate domains (DAC vs LO)” are documented to prevent hidden mixing paths.
Test points are reserved
Minimum probe set is planned: cleaner output, DAC clock at pin, LO ref, rail ripple, SYSREF node(s).
Repeatability hooks exist
Warm boot / cold boot / re-lock procedures are automatable; configuration snapshots are capturable (script + versioned profile).
Pass criteria
Spur mask is passable with margin in all key modes; the “source → victim → RF out” measurement chain is executable end-to-end.
B) Bring-up Gate — shortest path to spur origin (A/B discipline)
Three-point baseline is established
(1) Cleaner out → (2) DAC clock at pin → (3) RF out. Other probes are deferred until this chain is stable.
Only one variable per trial; lock the same operating state; save before/after snapshots with script + profile version.
SYSREF influence is tested
Toggle SYSREF injection and edge placement while monitoring repeatability (re-lock cycles) and spur movement.
Pass criteria
Spur class can be identified quickly (reference/fractional/activity/rails/layout); key results are repeatable across re-lock trials.
C) Production Gate — traceability, thresholds, and re-lock statistics
Configuration snapshot is stored
NVM/EEPROM fields capture clock profiles, key registers, firmware version, and mask version used for validation.
Re-lock matrix is mandatory
Warm boot / cold boot / re-lock cycles are executed; pass/fail is evaluated by spur mask + phase-repeatability criteria.
Environment is logged
Temperature points, supply mode, and operating state are recorded to make failures reproducible in the field.
Minimum probe set is preserved
At least cleaner out / DAC pin / RF out results are captured with the same instrument settings used in bring-up.
Pass criteria
Production runs yield consistent pass results under controlled settings; traceability fields enable one-pass reproduction of field issues.
ALT: Gate checklist timeline for design bring-up and production validation
Applications & IC Selection Notes (Direct-RF, spur-centric)
Selection is driven by failure mode (spur / phase-noise / repeatability), not by a single “jitter number”.
The goal is to choose a topology that prevents hidden mixing paths and makes SYSREF-based phase state repeatable.
Application buckets (Direct-RF only)
Wideband Direct-RF TX
Typical risk: a single discrete spur violates mask even when integrated jitter looks excellent. Prioritize isolation and spur fingerprints.
Multi-carrier / multi-mode
Typical risk: fractional spurs and activity-related lines appear only in certain NCO / bandwidth / data states. Enforce A/B discipline.
Coherent arrays / beamforming
Typical risk: phase state changes after re-lock or temperature drift. SYSREF distribution and repeatability matrix become first-class criteria.
Test equipment / signal generation
Typical risk: settings are hard to reproduce across units. Favor parts with stable profiles, NVM, and clear status/health signals.
Selection logic (If…then…) + concrete reference part numbers (MPN)
Repeatability fail: phase state changes across boot/re-lock/temp
If spur dominates…
Prefer jitter cleaners / attenuators with strong spur control, profile consistency, and clear reference partition options.
Validate with “tracks ref / frac / activity / rails” tests before changing layout.
If PN dominates…
Ensure the PN curve target offsets match the modulation sensitivity; avoid “good RMS jitter” that is integrated over the wrong window.
Fanout additive jitter and output standard selection can matter as much as the cleaner.
If repeatability dominates…
Favor parts that support deterministic SYSREF workflows, stable startup profiles (NVM), and health/status visibility.
Require a re-lock matrix (warm/cold/temp) as a formal acceptance test.
Note: oscillator frequency/suffix options are wide; selection must be driven by the spur mask and the measured “tracks ref/frac/activity/rails” signature.
Practical acceptance rule
Before changing layout, require: (1) isolate spur class (fault-tree branch), (2) confirm the fix at cleaner-out AND at DAC pin,
and (3) pass the re-lock matrix with stable spur positions and stable phase state.
ALT: Decision tree that selects clock topology by failure mode (spur, phase noise, repeatability)
Short, executable answers only. Each item is structured as: Likely cause / Quick check / Fix / Pass criteria.
Jitter number looks great, but a single spur fails ACLR—what’s the first “tracks ref or frac” check?
Likely cause
Deterministic spur (reference leakage or fractional-N spur) dominates ACLR, even when integrated jitter is low.
Quick check
Run two A/B trials while keeping RF output state identical: (A) change reference frequency (or swap reference source) and re-lock;
(B) change fractional settings (e.g., enable/disable fractional dithering or adjust modulus) while holding the same output frequency.
If spur spacing/offset tracks the reference/PFD → ref-related; if it changes with fractional pattern → fractional spur.
Fix
For ref-related spurs: improve ref-path isolation and reduce ref injection (partition refs if needed).
For fractional spurs: use a cleaner profile/topology with better fractional-spur behavior, constrain fractional modes, or adjust loop/profile to reduce pattern-to-output coupling.
Pass criteria
Spur is below the system spur mask with ≥6 dB margin in all required modes, and remains stable across ≥10 re-lock cycles (no new dominant lines).
Why does a spur move when I change the fractional setting, but not when I change the output frequency?
Likely cause
Fractional pattern or modulator artifact creates lines tied to the fractional sequence (not the RF carrier frequency itself).
Quick check
Hold output frequency constant and sweep fractional modulus/dither mode; then hold fractional settings constant and slightly move output frequency (same traffic state).
If spur follows fractional changes but not output moves, the line is fractional-sequence related (often repeatable by exact register set).
Fix
Prefer integer-friendly ratios where possible; select a cleaner/PLL mode with improved fractional spur performance; constrain fractional settings and keep a “known-good” profile in NVM for production repeatability.
Pass criteria
Worst-case fractional mode passes spur mask with ≥6 dB margin; changing output frequency does not re-introduce a mask-violating line.
SYSREF is present, yet phase repeatability after re-lock is poor—what do I log first?
Likely cause
SYSREF arrives, but capture/arming timing is non-deterministic (different edge relationship to DAC clock or inconsistent state machine timing).
Quick check
For ≥10 re-lock cycles, log: (1) SYSREF “captured/armed” status bit(s), (2) timestamp or counter at SYSREF capture,
(3) PLL/cleaner lock state, and (4) the exact configuration profile ID (register dump hash).
If the captured timestamp/state varies run-to-run, the arming window is not deterministic.
Fix
Enforce deterministic sequencing: lock clocks first, then arm capture, then inject SYSREF in a controlled window; reduce distribution skew; avoid asynchronous gating paths; keep a fixed profile for production.
Pass criteria
After ≥20 re-lock cycles, captured phase state is consistent (no unexpected phase jumps), and RF spur mask results remain unchanged run-to-run.
Why does disabling SYSREF remove a spur but worsen repeatability?
Likely cause
SYSREF distribution/coupling injects a deterministic spur, while SYSREF removal eliminates that injection but also removes deterministic phase alignment.
Quick check
Toggle SYSREF ON/OFF and record: spur amplitude change (dB), spur frequency/offset, and re-lock repeatability metric (phase/state consistency across ≥10 cycles).
If spur amplitude changes immediately with SYSREF, SYSREF path is a coupling aggressor.
Fix
Keep SYSREF for determinism, but harden its path: isolate SYSREF supply/return, shorten/route away from clock/LO, control edge rate, and enforce deterministic arming timing. Prefer differential routing where applicable.
Pass criteria
SYSREF-enabled mode passes spur mask with ≥6 dB margin, and phase repeatability remains stable across ≥20 re-lock cycles.
Why do spurs appear only under traffic/data activity, not in CW bench tests?
Likely cause
Digital activity modulates rails/ground or injects pattern-related feedthrough (SERDES/NCO/FPGA switching), creating discrete lines absent in CW.
Quick check
Run three states with identical clocking: (1) CW / idle, (2) PRBS/high traffic, (3) worst-case toggling pattern.
If spur amplitude changes by ≥3 dB with activity, correlate with rail ripple by probing the clock/PLL/DAC rails at the spur frequency (or its baseband equivalent).
Fix
Strengthen domain isolation (separate rails/islands), reduce shared return coupling, improve local decoupling at sensitive clock nodes, and minimize aggressor adjacency (routing/placement keepouts).
Pass criteria
Worst-case traffic state passes spur mask with ≥6 dB margin; spur amplitude variation across activity states is ≤1 dB for the dominant lines.
Cleaner output passes mask, but DAC output fails—what coupling path should be suspected first?
Likely cause
On-board coupling between clock/SYSREF/LO/digital domains and the DAC clock pin or analog output path (return-path or supply injection near the DAC).
Quick check
Compare spur at three points with identical settings: cleaner output → DAC clock at pin → RF out.
If spur is small at cleaner but grows at DAC pin, suspect local coupling near the DAC (clock routing adjacency, return discontinuity, rail injection).
Fix
Harden the last-inch clock path: shorten, keep differential pair tightly coupled, avoid stubs, keep return continuous, add isolation from aggressors, and improve local DAC rail filtering/decoupling.
Pass criteria
Spur growth from cleaner output to DAC pin is ≤1 dB for dominant lines, and RF out passes the system spur mask with ≥6 dB margin.
Why does changing power rail filtering shift spur amplitude more than expected?
Likely cause
Spur is rail-coupled (supply/ground modulation) rather than purely clock-generation intrinsic; filtering changes impedance at the offending frequency.
Quick check
Measure rail ripple near the clock/PLL/DAC domains while observing the spur. If spur changes ≥3 dB when rail impedance is altered,
and ripple at the spur-related frequency also changes, the dominant path is power/return coupling.
Fix
Increase domain isolation (separate LDO/filters), reduce shared impedance (shorter supply loops, better local decoupling),
and prevent return-path crossing that injects switching currents into sensitive clock/DAC regions.
Pass criteria
Dominant spur stays below mask with ≥6 dB margin across supply modes and activity states; spur amplitude sensitivity to rail-filter variants is ≤1 dB.
Why do I see symmetric sidebands around carrier that correlate with reference frequency?
Likely cause
Reference-related AM/PM modulation or leakage creates sidebands spaced by a reference/PFD-related frequency (often symmetric around the carrier).
Quick check
Slightly change the reference/PFD-related frequency and re-lock while keeping RF output state identical.
If sideband spacing shifts proportionally, the sidebands are reference-coupled; verify whether the line is present at DAC clock pin and/or SYSREF node.
Fix
Improve reference isolation (partition if needed), reduce coupling into DAC clock and output path (layout keepout/return continuity), and avoid unnecessary reference-related toggling near sensitive nodes.
Pass criteria
Reference-correlated sidebands are below mask with ≥6 dB margin across required reference options; sideband spacing behavior is explainable and controlled.
Why does a spur disappear at room temp but returns across temperature—what is the quickest isolation test?
Likely cause
Temperature shifts a coupling mechanism (VCXO/PLL behavior, rail impedance, mechanical stress, or layout-related mixing), re-enabling a spur path.
Quick check
Perform a 2-point A/B: room → hot (or cold) while holding the same configuration profile and traffic state; measure spur at cleaner out and at DAC clock pin.
If spur appears at DAC pin but not at cleaner out, the temperature-sensitive path is local coupling; if it appears at cleaner out, the source is upstream (reference/PLL).
Fix
Stabilize the sensitive domain: improve rail isolation over temperature, reduce mechanical/thermal gradients near clocks, and lock a temperature-robust cleaner profile; if needed, separate DAC vs LO reference domains.
Pass criteria
Across the required temperature range, the worst-case spur remains below mask with ≥6 dB margin; re-lock repeatability remains stable at each temperature point.
Multi-channel DAC: channels meet SFDR individually, but beamforming fails—what phase/coherence metric is missing?
Likely cause
Per-channel SFDR is insufficient to guarantee array performance; missing metric is relative phase (and drift) across channels under re-lock and temperature changes.
Quick check
Measure channel-to-channel phase error at the carrier (and at band edges if wideband), then repeat across ≥10 re-lock cycles and at ≥2 temperature points.
If phase changes by more than the beamforming budget (system-defined), coherence is the bottleneck.
Fix
Enforce deterministic SYSREF capture and distribution skew control; add per-channel calibration/trim hooks; use a repeatability matrix as an acceptance test, not only SFDR.
Pass criteria
Channel-to-channel phase error stays within the system beamforming budget across re-lock (≥20 cycles) and temperature (all required points), while spur mask remains passable.
Why does a “small” clock routing change fix spurs even though impedance looks correct?
Likely cause
Spur path is dominated by coupling/return geometry (mode conversion, nearby aggressor coupling, return discontinuity), not by nominal differential impedance.
Quick check
Compare spur at DAC clock pin before/after the routing tweak under identical configuration and activity state.
If spur changes by ≥3 dB while cleaner output is unchanged, the dominant path is local coupling (proximity/return), not the cleaner.
Fix
Prioritize coupling control: keep clock pairs tightly coupled, maintain continuous return, avoid crossing splits/slots, enforce keepouts from aggressors, and remove stubs; improve local decoupling near the clock receiver.
Pass criteria
The spur is below mask with ≥6 dB margin, and the improvement remains after ≥10 re-lock cycles and across required activity states.
How to distinguish reference leakage spur vs LO feedthrough using only a spectrum analyzer?
Likely cause
The line is either reference-related leakage/mixing or LO-related feedthrough/mixing; both can appear as discrete spurs near the carrier.
Quick check
Perform two single-variable moves while observing the spur marker: (A) change reference frequency (or PFD-related setting) and re-lock;
(B) change LO frequency by a small step while keeping the rest identical.
If the spur offset/spacing tracks the ref move → reference leakage; if it tracks LO move → LO feedthrough/mixing path.
Fix
For ref leakage: isolate/partition reference domains and reduce reference injection paths.
For LO feedthrough: increase LO-to-clock physical isolation, harden return paths, improve rail isolation, and avoid sensitive adjacency near DAC clock and analog outputs.
Pass criteria
The identified spur mechanism is eliminated or reduced below mask with ≥6 dB margin, and the classification remains consistent across ≥10 re-lock cycles and ≥2 activity states.
