RF LO Synthesizers (Frac-N PLL + External VCO)
← Back to:Reference Oscillators & Timing
This page is a practical playbook for designing and debugging RF LO synthesizers (Frac-N + external VCO) to meet phase-noise and spur masks at the LO port. It shows how to map observed spectrum behavior to measurable root causes and the fastest fix knobs (frequency plan, loop bandwidth, SDM/dither, isolation, and layout/PI).
What is an RF LO Synthesizer (and when you need one)
An RF LO synthesizer generates a tunable local oscillator for frequency conversion (up/down conversion) in a TRx chain. The design target is a phase-noise curve + spurious mask at the LO port—not generic “digital clock jitter” alone.
Engineering definition
Frac-N PLL + External VCO
PN curve + Spurs
A common architecture uses a (fractional-)N PLL to control an external VCO, trading loop bandwidth, tuning steps, lock time, and spur behavior to meet an RF mask.
Use an LO synthesizer when these constraints are real
- Wide tuning range is required (multi-band, multi-channel, multi-mode).
- Fine frequency step is required (channel raster, sweep, FMCW, calibration tones).
- Spur mask is tight (spurs can land near IF/beat tones or in-band blockers).
- Fast hop/lock time matters (scan/hop regimes, burst systems).
- Close-in phase noise is critical (EVM/phase error, reciprocal mixing sensitivity).
Avoid over-design when the system does not demand it
- Only a fixed or few LO frequencies are needed and spurs are not a mask driver.
- The task is primarily digital clock cleanup/distribution rather than RF mixing.
- Requirements are expressed only as a single RMS jitter number without an RF spur/PN mask.
Verification signals (what must pass at the LO port)
Phase-noise curve (offset-dependent)
Evaluate close-in vs far-out regions as a curve target (mask), not a single number.
Spurs (deterministic lines)
Confirm discrete spurs vs mask limits; classify by whether they track reference, fractional setting, or power/ground.
Lock / hop behavior
Validate lock time and post-hop settling before measuring PN/spurs (avoid “measurement-too-early” failures).
Scope rule (to avoid cross-page bloat)
This page uses an RF view (PN curve + spurs). Definitions and RMS-jitter integration windows should be referenced from
Key Specs & Selection
.
System boundary in a TRx (what this page covers / excludes)
This section defines the ownership boundary to prevent scope creep: the focus stays on the LO synthesizer module (PLL, loop filter, external VCO, and near-port output chain) and uses short cross-links for adjacent domains.
This page covers
- PLL-based LO synthesis (fractional-/integer-N) and configuration knobs that move PN/spurs.
- External VCO selection hooks (tuning range, Kvco sensitivity, pushing/pulling risk).
- Loop filter placement and control-path hygiene (what corrupts the tuning node).
- Near-port chain (divider/buffer/isolation) and where additive noise/spurs can appear.
- Bring-up and production hooks: measurement points, logs, and pass criteria.
This page does NOT cover (use short cross-links)
- Definitions and integration windows for RMS jitter / PN-to-jitter conversions → Key Specs & Selection.
- System clock distribution trees, redundancy routing, multi-domain fanout → Distribution & Fanout.
- Network timing and synchronization (PTP/SyncE/GNSSDO/holdover strategies) → Timing & Synchronization.
- Interface-specific ref-clock compliance details (JESD204/PCIe/SyncE classes) → Interface-Focused Clocks.
Hard guardrail
Any mention of PTP/SyncE/JESD204/PCIe is limited to one constraint sentence plus a cross-link. No deep dives here.
Measurement-point sanity check (before blaming “the PLL”)
When a spur or noise-floor anomaly appears, first confirm where it is measured. Each point isolates a different contributor:
Point
VCO output
Isolates VCO intrinsic PN and pushing/pulling sensitivity. If the issue is absent here, it is likely downstream.
Point
Post-divider
Isolates divider additive noise and divider-related spurs. Compare with a bypass/alternate divide when possible.
Point
Post-buffer
Isolates buffer compression/harmonics and supply-coupled spurs. Verify supply ripple correlation here.
Point
Board LO port
Captures the real delivered purity: termination, reflections, coupling, and connector/launch effects.
Topologies: Frac-N + external VCO, Integer-N, sub-sampling, multi-loop
LO architecture selection is a decision gate: different topologies shift the achievable phase-noise shape, spur risk, hop behavior, and implementation complexity. Each option below answers the same five questions to prevent scope creep.
Unified comparison
Keep it RF: PN curve + spurs
- Coverage & step: tuning range and step granularity.
- Spur risk: which spur classes are most likely to dominate the mask.
- PN shape: close-in vs far-out limitations (qualitative ownership).
- Lock / hop: lock time, hop settle, and measurement timing traps.
- BOM / layout: external VCO/control node sensitivity and floorplan demands.
Frac-N + ext VCO
Fine steps
Wide ratios
- Coverage & step: wide coverage with fractional channel raster.
- Spur risk: fractional spurs and integer-boundary sensitivity can dominate the mask.
- PN shape: close-in often bounded by VCO + loop shape; far-out can be limited by divider/buffer/additive noise.
- Lock / hop: flexible but requires settling discipline before PN/spur verification.
- BOM / layout: control node cleanliness (loop filter / tuning line) is a primary risk.
Integer-N + ext VCO
Cleaner spurs
Coarser step
- Coverage & step: step is tied to reference/PFD choices; channel raster may be constrained.
- Spur risk: reference-related spurs tend to be the dominant class (often easier to predict).
- PN shape: fewer fractional artifacts; close-in still depends on VCO and loop strategy.
- Lock / hop: can be robust with simpler state behavior.
- BOM / layout: similar analog hygiene requirements; fewer fractional tuning modes to validate.
Sub-sampling PLL
High-freq LO
Sensitive
- Coverage & step: depends on sampling/ref strategy; often targets specific high-frequency LO bands.
- Spur risk: sampling-related artifacts and coupling sensitivity can cause board-to-board spread.
- PN shape: strong potential for favorable close-in shaping when executed cleanly; control path must remain quiet.
- Lock / hop: can be fast, but verification must include sensitivity checks.
- BOM / layout: floorplan and isolation discipline are primary determinants of repeatability.
Multi-loop
Fast hop
Complex
- Coverage & step: can combine wide coverage with flexible step planning.
- Spur risk: multiple interacting loops increase the number of spur paths to validate.
- PN shape: enables separated roles (tracking vs cleaning) at the cost of extra coupling paths.
- Lock / hop: designed for fast transitions, but transient behavior must be verified explicitly.
- BOM / layout: highest implementation burden; repeatability depends on disciplined partitioning.
Topology → typical symptom → first measurable check
| Topology | Typical failure symptom | First measurable check | Interpretation |
|---|---|---|---|
| Frac-N + ext VCO | One spur dominates the mask; severity changes with fractional setting or “dither” mode. | Hold fOUT constant; vary frac word / dithering and observe whether the spur moves or scales. | If it tracks fractional settings → prioritize fractional spur paths (handled in spur-control sections). |
| Integer-N + ext VCO | Spurs appear at stable offsets that look related to reference/PFD spacing. | Change fREF/PFD within allowed range; confirm whether spur spacing/position tracks the change. | If it tracks reference → prioritize reference spur and ref isolation path checks. |
| Sub-sampling PLL | Close-in noise varies strongly by board or layout; “good on one build” but not repeatable. | Compare free-run VCO PN vs locked PN at the same node; log the tuning-node noise. | If lock degrades close-in → control/sampling sensitivity is dominant (floorplan/isolation becomes critical). |
| Multi-loop | Hop is fast, but transient spurs/noise appear right after a hop; results depend on measurement timing. | After hop, insert a defined settling delay and re-measure PN/spurs; compare early vs delayed readings. | If delayed measurement passes → transient/settling and test timing dominate (verify hop discipline). |
Note: table content is intentionally “first-check only”. Detailed knob tuning belongs to the loop-bandwidth and spur-control sections.
Noise & spur taxonomy (what creates what, and where it shows up)
A reliable debug workflow starts with classification: separate noise-floor regions from deterministic spurs, then run “tracking tests” to see what the anomaly follows (reference, fractional setting, divide plan, or power/digital activity).
Phase-noise regions (qualitative ownership)
Close-in region
Often shaped by VCO intrinsic PN, loop behavior, and reference coupling paths.
Far-out region
Often limited by divider/buffer additive noise and wideband supply/coupling.
Terminology guardrail
Use curve regions for debug. Formal definitions and PN↔jitter integration windows belong to
Key Specs & Selection
.
Spur taxonomy (5 classes used across this page)
Reference spurs
Often tied to fREF/PFD spacing and coupling.
Fractional spurs
Correlate with frac word / SDM / dithering choices.
Integer-boundary spurs
Explode at specific channels / divide plans (boundary sensitivity).
Power-rail spurs
Track supply ripple or its mixing products.
Digital-coupling spurs
Track digital activity (interface clocks / bursts / polling).
Tracking tests (first confirmation step for each spur class)
Track fREF / PFD
Change fREF/PFD; if spur spacing/position follows → prioritize reference spur paths.
Track fractional word
Hold fOUT constant; vary frac/dither; if spur follows → prioritize fractional spur paths.
Track divide plan / channel
Shift channel or divide plan slightly; if only specific channels blow up → prioritize integer-boundary sensitivity.
Track power ripple
Measure supply ripple; if spur equals ripple (or its products) → prioritize power-rail injection.
Track digital activity
Change bus/polling activity; if spur follows → prioritize digital coupling and partition checks.
Measurement caution (keep short)
Avoid over-interpreting early-hop readings; confirm the measurement point (VCO vs port) before assigning blame to the PLL core.
Loop bandwidth planning (shape the PN curve + lock time + stability)
Loop bandwidth is the primary system-level knob that trades phase-noise shaping, spur visibility, lock/hop time, and stability margin. This section is intentionally engineering-focused: it uses qualitative cause→effect rules and measurable verification gates, without control-theory derivations.
BW triangle
PN shape · Spurs · Lock time
Bandwidth ↑ (wider loop)
Stronger tracking of the reference and faster acquisition. The close-in region can become more influenced by reference/loop behavior,
while reference-related spurs may become more visible.
Bandwidth ↓ (narrower loop)
More VCO-dominated behavior and slower acquisition. The close-in region tends to reflect VCO intrinsic PN more strongly,
while reference spur sensitivity may reduce (depending on the coupling path).
Stability constraint (non-negotiable)
Bandwidth is limited by stability margin. Insufficient phase margin can create peaking, making close-in noise and spur visibility worse
even if lock time improves.
Before tuning bandwidth: lock these three targets
1) PN mask (curve target)
Specify which region is the hard constraint: close-in or far-out.
Use curve regions (not a single jitter number) to prevent mis-optimization.
2) Spur allowance (mask margin)
Identify which spur class is most likely to dominate the mask (reference / fractional / rail / digital / boundary).
Classification belongs to the taxonomy section; BW tuning assumes the class is known.
3) Lock / hop time budget
Define the maximum allowable time to reach a stable LO state (acquire + settle). Validation must measure after the defined settling delay
to avoid early-read false failures.
After tuning bandwidth: verify these three outcomes
A) Close-in PN trend
Confirm the close-in portion moves in the intended direction relative to the baseline, without introducing excessive peaking.
B) Reference spur visibility
Check whether reference-related spur lines grow relative to the mask margin after BW changes. If they grow, treat it as a coupling/throughput trade-off
(not a measurement artifact) only after confirming the measurement point.
C) Lock / hop time compliance
Measure acquisition and settling time against the budget using a repeatable sequence. Verify “steady-state after delay” rather than immediate post-hop snapshots.
Stability engineering note
Bandwidth changes must preserve stability margin. If close-in noise worsens while lock time improves, the most common cause is loop peaking
from insufficient phase margin or uncontrolled coupling into the tuning node.
External VCO selection & control hooks (Kvco, tuning range, pushing/pulling)
An external VCO can be the dominant determinant of close-in phase noise and system repeatability. Selection must prioritize coverage margin and sensitivity paths (Kvco, supply pushing, load pulling) alongside the phase-noise curve. The control-voltage path must be treated as a high-sensitivity analog node.
VCO selection priorities (system-first ordering)
Coverage margin
Tuning range must cover the band with margin for process, temperature gradients, and aging. Insufficient margin forces extreme Vtune values
and increases sensitivity to noise and drift.
Kvco (Hz/V)
Kvco sets how strongly control-voltage noise becomes frequency/phase modulation. Large Kvco improves tuning authority but raises sensitivity;
small Kvco reduces sensitivity but may constrain loop gain and tuning headroom.
Phase-noise curve
Compare the curve regions that matter to the receiver architecture. A good single-point PN number is not sufficient for mask compliance.
Pushing / pulling sensitivity
Supply pushing and load pulling determine whether board-level ripple, impedance changes, or coupling events become spurs and channel sensitivity.
Output power, harmonics, supply sensitivity
Output power and harmonic content must not overload the next stage. Supply sensitivity reveals how easily ripple becomes deterministic lines.
Control-voltage hygiene (noise → PN / spurs)
Treat Vtune as a high-sensitivity analog node
Vtune noise directly modulates the VCO. The loop filter and Vtune routing must remain isolated from fast digital edges and switching supply currents.
Isolation hooks (concept-level)
Use small isolation elements (series isolation, light RC filtering, guard discipline) to reduce coupling into the tuning node without destabilizing the loop.
Component sizing and stability details are validated in the bandwidth-planning section.
Common failure pattern
A “good datasheet VCO” can fail mask compliance if the tuning node is contaminated by supply ripple or digital activity, creating deterministic spur lines.
Stand-alone VCO test checklist (repeatable, measurable)
1) Free-run PN baseline
Measure the free-running PN curve at a defined test point to establish the intrinsic floor before loop shaping.
2) Tuning curve (Vtune → frequency)
Sweep Vtune and log frequency coverage plus slope changes. Confirm margin at both ends to avoid boundary sensitivity.
3) Supply pushing sensitivity (small injection)
Introduce a controlled small ripple on the VCO supply and check whether spur lines appear and track the injection frequency.
4) Load pulling / isolation sensitivity
Vary output loading/isolation and observe frequency offset or spur growth. Strong sensitivity indicates higher risk of board-to-board variation.
5) Thermal sensitivity quick scan
Apply a controlled temperature change or gradient and log drift direction and repeatability. Thermal gradients can look like random PN degradation.
Fractional-N spur control playbook (SDM, dithering, integer boundary traps)
When a fractional-N LO fails a spur mask, the fastest path to root cause is a single-variable, measurable workflow. This playbook maps spur observations to the most likely coupling chain (SDM behavior, PFD/CP non-idealities, divider coupling, reference leakage, or rail/digital injection), then applies fixes in ROI-first priority.
Step 0: Describe the spur in a repeatable way (avoid “mystery lines”)
What to record (minimum)
Spur offset, spur spacing, whether it appears as a single line or a cluster,
and whether it changes with configuration. Always record the measurement point (VCO out / post-divider / buffer / board port).
Fast class labels (use one)
Reference-related (tracks fREF/fPFD),
Fractional-related (tracks frac word/SDM state),
Integer-boundary (stubborn at certain points),
Rail/digital-coupled (tracks ripple or activity).
Root-cause chains: what creates which spur “signature”
SDM behavior & quantization shaping
Fractional modulation can introduce deterministic periodic components. Spur clusters that change with frac word or SDM mode typically originate here.
PFD / CP non-idealities
Nonlinearities can “mix” reference and fractional patterns into discrete lines. Spurs that strengthen with certain PFD/N plans often point here.
Divider / digital coupling
Divider state activity and digital transitions can couple into the loop or output path, producing lines that correlate with ratio choices or digital activity changes.
Reference leakage / throughput
Reference impurity (PN/spurs/EMI) can leak through the reference path into the loop. Spurs that track fREF or fPFD often indicate this chain.
ROI-first fixes (apply in this order to avoid “random tuning”)
Step 1 — Frequency planning (fastest, lowest risk)
- Use when the spur lands on a sensitive IF/channel region.
- Change only fOUT plan (small shift or alternative channelization), keep the rest unchanged.
- Expected: spur position moves relative to the channel; the best outcome is “avoidance” with mask margin.
Step 2 — Dithering / SDM mode (most common fractional knob)
- Use when the spur tracks frac word or appears as a cluster linked to SDM patterns.
- Change only one SDM/dither setting at a time.
- Expected: discrete lines reduce or spread; baseline noise can shift. Judge by mask margin, not aesthetics.
Step 3 — PFD frequency & N planning (structural)
- Use when spacing or location clearly correlates with fPFD or the divider plan.
- Try alternate N/PFD combinations that land at the same fOUT.
- Expected: spur spacing/placement changes; stubborn lines can disappear or relocate.
Step 4 — Loop bandwidth tuning (powerful but stability-limited)
- Use when close-in shape or reference-related visibility is the limiting factor.
- Follow a gated A/B process: lock targets → change BW → verify PN trend + spur margin + lock time.
- Expected: close-in curve reshapes; reference spur visibility can change. Stability margin is non-negotiable.
Step 5 — Isolation (rail / ground / digital) as the convergence tool
- Use when the spur tracks rail ripple or digital activity, and earlier steps do not converge.
- Run isolation A/B to prove the coupling path before committing to layout or partition changes.
- Expected: spur amplitude changes with isolation strength, confirming injection rather than SDM core behavior.
Integer boundary traps: how to recognize “stubborn points”
Signature
Certain frequency points show spur lines that remain high across multiple dither/SDM settings. These points often align with boundary-like ratio conditions.
Fast identification scan
Run a small frequency micro-sweep around the point (minimal change) and watch for abrupt spur growth or disappearance. Boundary behavior is step-like, not gradual.
Best response
Prefer re-planning N/PFD or frequency planning to avoid the stubborn point. Treat “hard tuning” at that point as last resort.
Highest-value measurements (two tests + one mandatory log triple)
Test 1 — Does the spur follow the fractional word?
Change fractional settings while keeping the measurement point and reference conditions stable. If the spur location or amplitude moves with fractional state,
prioritize SDM/dither and fractional pattern mechanisms.
Test 2 — Change fOUT method while holding fractional state
Adjust output frequency with a different N/PFD plan while holding the fractional state constant. Spur changes that track the plan indicate divider/PFD or reference throughput sensitivity.
Mandatory log triple (most valuable troubleshooting record)
fREF
reference frequency
fPFD
PFD frequency / plan
frac word
+ SDM / dither mode
Always append the measurement point (VCO out / post-divider / buffer / board port). Without a stable measurement point,
configuration logs cannot be compared.
Reference path & isolation (clean ref in, keep junk out)
Reference cleanliness impacts LO spurs and close-in behavior through three practical paths: reference PN, reference spurs, and injected EMI. This section focuses only on the reference input segment (source → interface → isolation/filter → PLL reference pin), and provides a high-confidence A/B method to attribute spur limits to the reference chain.
How reference quality turns into LO artifacts (path view)
Reference PN
Reference phase noise can enter the loop through the reference path and influence close-in behavior. Treat it as a curve-region contributor, not a single number.
Reference spurs
Discrete impurities on the reference can leak through and appear as reference-related lines at the LO output, often tracking fREF or fPFD.
Injected EMI / coupling
Coupled interference at the reference interface can act like deterministic modulation. If the line changes with environment or activity, suspect injection rather than PLL core settings.
Reference interface segment (only the LO input portion)
Single-ended vs differential
Differential reference interfaces generally improve immunity to common-mode injection and cable/connector coupling. Single-ended paths demand stricter return-current discipline.
Termination & coupling goal
The goal is controlled impedance behavior at the reference input and reduced reflection-driven sensitivity. Over-filtering can degrade edges and create new coupling points.
Return-current awareness
Reference input is a sensitive segment. Avoid sharing return paths with high-current switching domains near the connector and the PLL reference pin region.
Strongest attribution method: same PLL/VCO, swap reference only (A/B)
A/B steps (single-variable discipline)
- Freeze configuration and logs: fREF · fPFD · frac word (+ SDM/dither) and measurement point.
- Measure with Reference A: record spur lines and close-in trend.
- Swap to Reference B only: keep all PLL/VCO settings unchanged.
- Compare: spur margin and close-in trend changes.
- Conclude: large change implies reference-chain dominance; small change redirects attention to fractional/PFD/isolation mechanisms.
Critical control
The A/B test is only valid if the measurement point is unchanged (connector vs post-filter vs PLL pin). Moving the probe point can manufacture false improvements.
Isolation / filtering principles (benefit vs risk)
Benefits
Reduced injected EMI, improved repeatability, and reduced reference-related line visibility when the reference source is clean but the interface is noisy.
Risks
Over-filtering can degrade edges and amplitude, create termination mismatch sensitivity, or introduce new coupling nodes. Confirm with A/B before committing.
Output chain: divider / buffer / leakage / harmonics (LO purity at the port)
A common failure mode is “clean at the VCO node, dirty at the board port”. The output chain (divider, buffer/driver, termination, and reverse isolation) can add noise, create harmonics via waveform stress, or allow back-injection that converts reflections and activity into deterministic spurs. This section uses a test-point chain and a Δ-contribution method to attribute which stage dominates port purity.
Port purity failure map (what “breaks” after the VCO)
Additive noise
Divider/buffer stages can raise the baseline by their own noise contribution. When port noise degrades mainly in far-out regions,
suspect the post-VCO chain before blaming the PLL core.
Harmonics from waveform stress
Driver saturation or slew limits can distort the waveform and grow 2nd/3rd harmonics. Reflection-driven over/undershoot can trigger the same distortion at the port.
Back-injection (pulling / modulation)
Poor reverse isolation allows load reflections or nearby activity to modulate the chain and show up as spurs.
If changing the cable/termination changes a spur, back-injection is the primary suspect.
Termination / reflection sensitivity
Mismatch and return-path discontinuity turn the port into a reflection generator. Reflections can translate into deterministic lines through non-ideal output stages.
Stage risks (divider → buffer → port) and what they typically change
Divider
Typical impact: additive noise and ratio-linked sensitivity. If a spur appears or grows after the divider node, track correlation with divider plan and supply.
Buffer / driver
Typical impact: waveform stress (harmonics) and reverse isolation limits. If the port changes with load, the driver’s isolation and linear region are critical.
Termination & port environment
Typical impact: reflections and back-injection. If an attenuator/known-good termination improves purity, mismatch sensitivity is dominating.
Measurement chain (TP0→TP3) + Δ-contribution method
Attribute port degradation by measuring the same metrics at each node and comparing the incremental change (Δ) stage by stage. The stage with the largest Δ is the first repair target.
TP0 — VCO output
baseline spur set · baseline PN trend · baseline harmonics
TP1 — post-divider
Δ from divider (noise/spur growth, ratio-linked lines)
TP2 — post-buffer/driver
Δ from driver (harmonics, reverse isolation, additive noise)
TP3 — board LO port
Δ from termination/reflection/back-injection environment
What to compare at each TP (keep instrument settings stable)
- Spurs: track the worst few lines and their offsets; compute Δspur between adjacent nodes.
- PN trend: compare curve regions (close-in vs far-out) for “raised/lowered baseline” behavior; compute ΔPN trend qualitatively but repeatably.
- Harmonics: compare 2f/3f growth; a large Δharm indicates waveform stress in that stage.
Reverse isolation & reflection: when the load creates the spur
Mechanism (engineering view)
Reflections and nearby activity can re-enter the output chain when reverse isolation is insufficient. That back-injection becomes deterministic modulation
and appears as spurs or “sensitivity spikes” at the port.
Fastest confirmation A/B (single-variable)
Keep the synthesizer configuration unchanged, then swap only one of the following:
termination / attenuator / known-good cable.
A large spur change indicates reflection/back-injection dominance rather than PLL-core dominance.
Repair priority (ROI-first: fix the biggest Δ stage)
- Driver operating point: avoid slew/saturation; enforce correct swing/common-mode for the selected standard.
- Termination & impedance continuity: reduce reflections and sensitivity to port environment changes.
- Buffer selection: prioritize reverse isolation and low additive noise where the chain is sensitive.
- Back-injection path control: isolate coupling routes proven by the A/B termination test.
- Structural changes: only after Δ analysis confirms the output chain is the dominant limit.
PCB layout & PI/EMI checklist (RF + mixed-signal realities)
LO synthesizer failures frequently originate from physical reality: control-voltage contamination, supply ripple modulation, and digital coupling. This checklist focuses on loop-filter placement, Vtune routing, power integrity, and RF routing so issues can be proven with measurements rather than assumptions.
Loop filter placement & Vtune routing (highest sensitivity zone)
Placement
Place the loop filter adjacent to the charge-pump (CP) pins. Keep the control path compact to minimize pickup and reduce unintended series inductance.
Control-line discipline
Keep Vtune short, guard it, and route it away from fast digital clocks. Avoid crossing plane splits; enforce a continuous return reference under the control segment.
Measurement hook
Probe Vtune for ripple or discrete components that match the spur offset. If Vtune shows the same periodic content as the spur,
the control path is a confirmed modulation route.
Supply strategy (low-noise rails, partitioning, π filtering, continuous returns)
Low-noise rail intent
Use a low-noise supply strategy for PLL/VCO-sensitive rails. Partition noisy switching domains away from analog-sensitive nodes to reduce ripple-to-spur translation.
π filter placement
Place π filtering close to the sensitive load region, not at a distant rail source. The goal is to prevent ripple from reaching the sensitive pins through the final segment.
Measurement hook
Probe the sensitive rail for periodic ripple. If the ripple frequency equals the spur offset and the spur amplitude scales with ripple,
the supply path is the dominant injection source.
RF routing (impedance, ground reference, avoid split crossings, via return realism)
Impedance continuity
Treat the LO route as a controlled-impedance segment where mismatch translates into reflections. Reflections can become deterministic spurs through output non-idealities.
Return reference continuity
Avoid crossing plane splits or slots with the LO route. A forced detour in return current increases loop area, coupling, and reflection sensitivity.
Measurement hook
Swap only the termination/cable/attenuator at the port. If spurs respond strongly, routing mismatch and back-injection are verified contributors.
Layout faults that instruments can prove (evidence-first checklist)
Vtune contamination
- Evidence: ripple/discrete content on Vtune matches spur offset.
- Probe: Vtune node near CP/loop filter.
- Meaning: control path is a modulation route.
- Minimal action: temporary shielding/guarding or controlled low-pass reinforcement for A/B attribution.
Supply ripple spur path
- Evidence: rail ripple frequency equals spur offset; spur scales with ripple amplitude.
- Probe: sensitive rail at the load region, not only at the regulator.
- Meaning: PI coupling dominates over PLL-core tuning.
- Minimal action: local π-filter A/B or partition A/B to confirm injection sensitivity.
Digital clock coupling
- Evidence: spur correlates with digital activity or a switching frequency.
- Probe: near the coupling region; compare spectra with digital domain disabled/enabled.
- Meaning: physical proximity/return sharing is injecting deterministic content.
- Minimal action: temporary separation/ground reference improvement to confirm coupling path before a layout respin.
Bring-up & production test (measurements, logs, pass criteria)
This section turns an RF LO synthesizer into an engineering deliverable: a repeatable bring-up loop, a minimal production test set, and logs that make spur/PN failures traceable.
A) Bring-up minimal closed loop (6 steps; fixed order)
1) Power (conditions freeze)
Confirm rails, reference input level/termination, and partitioning before touching any PLL knobs.
2) Lock (repeatable criteria)
Use a deterministic lock indicator (status bit / LD pin / monitor flag) and record lock time on every run.
3) Measure (spur mask first, then PN mask points)
Start with the spur mask at sensitive offsets/bands; only then check phase-noise mask points (close-in + far-out).
4) Tune (only two knobs at a time)
Freeze everything except: (i) loop bandwidth profile, (ii) SDM/dither mode. Avoid multi-variable tuning that destroys traceability.
5) Verify (Δ attribution by measurement points)
Re-measure the same mask points and compare deltas at consistent testpoints (VCO / post-divider / post-buffer / port).
6) Store config (reproducible snapshot)
Store register snapshot + environment meta (temperature, rails, reference source) so the exact spectrum can be reproduced later.
B) Minimal measurement set (fast, mask-driven)
- Lock & dynamics: lock time, re-lock repeatability, unlock triggers (temp/rail corners).
- Output level: output power/amplitude at the intended port impedance; confirm no buffer compression artifacts.
- PN mask points: record a small set of mandatory offsets (close-in + far-out) rather than full curves.
- Spur mask points: measure at application-sensitive offsets/bands; compare before/after tuning.
Measurement discipline (anti-false-fail)
Keep testpoint, attenuation, termination, and sweep settings constant across A/B runs; otherwise Δ comparisons become meaningless.
C) Production test minimal set (screen risk without killing takt time)
100% test (must)
- Lock time ≤ [TBD] and stable lock indicator.
- Port output level within [TBD] window.
- Key spur mask points at sensitive offsets/bands pass.
Lot sampling (recommended)
- PN mask points (close-in + far-out) at fixed offsets.
- Corner checks: rail ± [TBD], temperature spot checks.
Escalation triggers
- Any new spur family appears → expand sampling around affected configs.
- Lock time drift across lots → audit reference/PFD settings and PI rail noise.
D) Must-log fields (the traceability backbone)
Reference
ref frequency, ref type/source, ref input level & termination state
PLL core
PFD frequency, R divider, N divider, frac word (INT/FRAC/MOD or equivalent)
Loop/CP profile
bandwidth config, charge pump current/setting, SDM/dither mode, fast-lock enable (if used)
Environment
temperature, key rails (PLL/VCO/buffer) voltage, board revision
Measurement meta
testpoint ID, attenuation/termination, instrument RBW/VBW & sweep profile (kept consistent for Δ comparisons)
E) Pass criteria template (mask-based; fill with system numbers)
- Lock: lock time ≤ [TBD]; re-lock phase/state repeatability meets [TBD].
- Spurs: at all sensitive offsets/bands, spur level ≤ [Spur mask].
- Phase noise: at required offset points, PN ≤ [PN mask] (point checks, not jitter tutorials).
- Output level: port amplitude/power in [TBD] range; no compression-driven harmonic growth.
- Corners (sampling): defined temperature/rail excursions still pass masks or follow documented derating.
Fast root-cause hint (when mask fails)
Every failure report must include: {fREF, fPFD, divider, frac word} + testpoint + BW profile. Without this tuple, spur/PN attribution becomes guesswork.
Applications & IC selection notes (constraints → decision tree → template)
This chapter maps application constraints to LO synthesizer knobs, then provides a one-page selection decision tree plus a fill-in template for datasheet/EVB verification.
A) Applications (constraint mapping only; no system expansion)
TRx / SDR / FMCW radar
- Close-in PN is often the dominant impairment near sensitive IF/beat regions.
- Discrete spurs can land inside passbands and fail masks even if the noise floor looks acceptable.
- Focus on: frequency planning, fractional spur control, and port purity.
Multi-LO / multi-channel
- Constraint is phase consistency across channels/cards, not just single-output PN.
- Selection must include repeatable lock behavior and traceable configuration snapshots.
- Phase alignment strategies belong to timing/distribution pages (link internally).
Frequency plan (engineering rules, not algorithms)
- Reserve guard bands around sensitive IF/beat windows.
- Avoid “integer boundary” neighborhoods when spurs become stubborn.
- Always log the tuple: fREF / fPFD / divider / frac word for reproducibility.
B) IC selection logic (decision tree + must-verify checklist + template)
Start with 5 questions (fixed order)
- Frequency range (coverage + external VCO plan)
- Step size & hopping behavior (fractional need, tuning density)
- Phase-noise mask points (offset-based requirements)
- Spur mask points (sensitive offsets/bands)
- Lock time / power / cost (deliverable constraints)
PLL core must-verify
- PFD max and allowed reference topologies
- Fractional spur control modes (SDM, dither) and documented trade-offs
- Programmable BW profiles + charge pump options
- Fast-lock behavior and repeatable re-lock evidence
External VCO must-verify
- Tuning range vs required coverage (including corners)
- Kvco vs loop stability margins and control-voltage noise sensitivity
- Pushing/pulling behavior under rail ripple and load variations
- Output power, harmonics, and reverse isolation at the intended port
Output chain must-verify
- Divider/buffer additive noise and compression-driven harmonic growth
- Termination/reflection sensitivity (spur growth due to mismatch)
- Port purity validated at the actual connector, not only at VCO node
Power & implementation must-verify
- Rail noise sensitivity (PLL/VCO/buffer) with injection checks
- Low-noise LDO choice, filtering, and partitioned returns
- Layout constraints for CP/loop filter/control line isolation
Reference examples (material numbers; starting points only)
These part numbers are provided to speed up datasheet/EVB lookup and lab A/B verification. Selection must be driven by the decision tree and the fill-in template below (corners + guardbands + masks).
PLL / synthesizer IC (external VCO capable)
- ADF4153A (fractional-N PLL synthesizer; external loop filter + external VCO)
- ADF41020 (integer-N PLL synthesizer; external loop filter + external microwave VCO)
- LMX2326 (TI; legacy integer-N family; datasheet notes status as OBSOLETE—use only as a reference baseline)
External VCO (example material numbers)
- Crystek CVCO55CC series example: CVCO55CC-2500-2500 (series sample material number)
- Mini-Circuits example: ZX95-2500+ (VCO family sample material number)
Low-noise rails (LDO examples)
- ADM7150 (ultralow-noise RF LDO family)
- TPS7A4700 / TPS7A47 (ultralow-noise high-voltage LDO family)
- LT3042 (ultralow-noise, ultrahigh-PSRR RF LDO family)
Note on suffix/package
Always verify package/suffix, temperature grade, and recommended external components. For LDOs and VCOs, confirm the exact output voltage or tuning range variant matches the rail plan and frequency plan.
Fill-in template (copy/paste and populate for each candidate)
Candidate
PN: ________ / VCO: ________ / LDO: ________
Range & step
fOUT min/max: ________ ; step: ________ ; hop time target: ________
Masks (points)
PN mask points: ________ ; spur mask points: ________
PLL configuration tuple
fREF: ________ ; fPFD: ________ ; divider: ________ ; frac word: ________
Bring-up evidence
lock time: ________ ; key spurs: ________ ; key PN points: ________
Implementation notes
rails: ________ ; control-line filter/guard: ________ ; port termination: ________
Recommended topics you might also need
Request a Quote
FAQs (troubleshooting only; measurable 4-line answers)
These FAQs only close out long-tail troubleshooting within the RF LO synthesizer boundary (PLL + external VCO + loop/BW + reference input + output chain + layout/PI + bring-up logs).
Always log this tuple for any spur/PN failure
fREF, fPFD, (R/N/INT), FRAC/MOD (or equivalent), BW profile, CP setting, temperature, key rails, and testpoint ID (TP0/TP1/TP2/TP3).
Spur moves when fractional word changes, but not when fOUT changes—what does that imply first?
Likely cause
Fractional-modulator–related spur family (SDM pattern / PFD-CP non-ideal interaction) tied to fPFD and FRAC/MOD rather than carrier frequency.
Quick check
Keep fPFD constant; vary FRAC/MOD (compensate INT to hold fOUT if possible) and confirm spur offset/level tracks FRAC/MOD; then change fPFD and confirm spur spacing/offset moves with fPFD.
Fix
Start with SDM/dither mode change (or MOD change) to break periodic patterns; if still failing, move fPFD and re-optimize BW at the new plan point.
Pass criteria
At all sensitive offsets, spur level ≤ [Spur mask] with the chosen SDM/dither + BW, and the failure is reproducible/traceable by the {fREF,fPFD,FRAC/MOD,BW} tuple.
A single spur fails the mask though phase noise is great—first “tracks ref vs tracks frac” check?
Likely cause
Discrete spurs are dominated by leakage/coupling mechanisms (reference feedthrough or fractional pattern), not by random PN.
Quick check
Run two A/B sweeps: (1) change fREF or R divider to change fPFD while holding fOUT; if spur spacing/offset follows fPFD → ref-related; (2) change FRAC/MOD while holding fPFD; if spur follows FRAC/MOD → frac-related.
Fix
If ref-related: reduce BW (or increase attenuation at fPFD via loop profile) and improve reference isolation/termination; if frac-related: switch SDM/dither/MOD first, then re-plan fPFD/N.
Pass criteria
The identified tracking rule holds across at least 3 channels/configs, and the spur at sensitive offsets is ≤ [Spur mask] at TP3 (LO port).
Close-in PN is worse than expected—what’s the first loop-bandwidth vs VCO-noise check?
Likely cause
The loop is not shaping noise as assumed (BW too small/large), or the VCO/CP/PFD noise dominates the close-in region.
Quick check
Change BW by ~2× (narrow ↔ wide) and re-measure close-in PN points at TP0/TP3; if close-in improves with wider BW, VCO noise likely dominates; if it worsens or stays, reference/CP/PFD/control-line noise is likely dominating.
Fix
Re-center BW so the close-in mask points are minimized while keeping reference spur under control; if control-line noise is suspected, add isolation R + extra C at the tune node and verify stability margin.
Pass criteria
All required close-in PN points are ≤ [PN mask] with a stable lock condition (no oscillation/peaking artifacts) and repeatable across 3 power cycles.
Far-out noise rises after buffer/divider—what measurement isolates additive noise fastest?
Likely cause
Divider/buffer additive noise (or compression) is lifting the far-out floor, even if the VCO node looks clean.
Quick check
Measure PN at the same offsets with identical instrument settings at TP0 (pre-divider) and TP2/TP3 (post-buffer/port); the far-out delta (Δ dB) isolates additive-noise contribution of the output chain.
Fix
Improve output-chain headroom/linearity (reduce drive/compression) or select a lower additive-noise buffer/divider option; confirm isolation/termination at the port to prevent re-injection.
Pass criteria
The measured Δ(far-out) from TP0→TP3 is within the allowable additive-noise budget, and TP3 far-out PN points meet [PN mask].
Reference spur increases when BW increases—what’s the first mitigation knob?
Likely cause
Wider BW increases reference feedthrough into the control path/output, lifting fPFD-related spurs.
Quick check
Sweep BW across two settings and measure the spur at offsets tied to fPFD; if spur rises monotonically with BW at the same testpoint, the spur is BW/feedthrough-driven.
Fix
First knob: reduce BW (or use a loop profile that attenuates around fPFD) until the spur meets mask; then compensate close-in PN with cleaner reference/CP settings rather than re-widening BW blindly.
Pass criteria
With the chosen BW, the reference spur at sensitive offsets is ≤ [Spur mask] and the required PN points remain ≤ [PN mask].
Integer boundary spur appears at specific channels—what frequency plan avoids it?
Likely cause
Certain N/FRAC/MOD neighborhoods create stubborn periodicity/leakage (“boundary” behavior), producing strong discrete spur families at specific channels.
Quick check
Move the channel slightly (±Δf) while keeping fPFD constant; if the spur “sticks” to specific N/FRAC ratios rather than sliding smoothly with frequency, it is plan-point dependent.
Fix
Re-plan fPFD/N to avoid the problematic N/FRAC/MOD zones (change fPFD or choose a different VCO band so divider ratios shift), then re-validate spur mask at the new plan points.
Pass criteria
The channel set avoids the boundary neighborhoods, and all channels pass the same spur mask at TP3 with logged {fPFD,N,FRAC/MOD}.
Control voltage shows ripple—how to prove it’s the spur root cause?
Likely cause
Ripple on the VCO tune/control node (or its return path) is FM-modulating the VCO, creating spurs at the ripple frequency (and/or its harmonics).
Quick check
Measure the tune-node ripple spectrum (high-impedance probe) and confirm the ripple frequency equals the LO spur offset; add a temporary isolation R + extra C at the tune node and check spur delta (Δ dBc).
Fix
Improve tune-line cleanliness: shorten/guard the control trace, add isolation R, optimize loop-filter grounding/return, and reduce injected rail noise feeding CP/loop filter.
Pass criteria
Tune-node ripple at the spur-related frequency is reduced below [Vtune ripple limit], and the corresponding LO spur at TP3 is ≤ [Spur mask] without introducing loop instability.
PLL locks but occasionally slips in temperature—what 2 logs reveal margin loss fastest?
Likely cause
Temperature drift pushes the VCO/control voltage toward a rail or triggers marginal VCO band/calibration behavior, reducing phase margin and slip tolerance.
Quick check
Log only two signals vs temperature: (1) Vtune (or tuning DAC code) headroom relative to rails, and (2) lock/cycle-slip counter (or lock status transitions) to correlate margin loss with Vtune saturation.
Fix
Re-plan divider/VCO band so Vtune stays mid-range across temperature; if available, re-run/calibrate VCO band selection and re-validate BW stability at hot/cold corners.
Pass criteria
Over the specified temperature range, Vtune remains within [Vtune_min, Vtune_max] headroom and lock/cycle-slip events are zero while meeting PN/spur masks.
Two boards with the same BOM show different spur levels—first layout/PI measurement to compare?
Likely cause
Board-level coupling differences (rail ripple, return-path discontinuity, or control-line pickup) are converting into discrete spurs despite identical schematics.
Quick check
Compare the VCO/PLL rail ripple spectrum at the same physical rail testpoint (same probe + bandwidth) and correlate ripple lines to LO spur offsets; then compare tune-node ripple as the second discriminator.
Fix
Add damping/decoupling at the offending rail resonance (or improve return stitching), and tighten control-line routing/guarding near the loop filter region.
Pass criteria
The rail/tune-node ripple lines no longer correlate to LO spur offsets, and both boards meet the same spur mask at TP3 under identical configs.
Phase noise meets spec at the VCO pin but fails at the LO port—what’s the first isolation/termination probe?
Likely cause
Reflections/back-injection at the port (poor match or insufficient reverse isolation) are converting into spurs/noise at TP3 even when TP0 is clean.
Quick check
Insert a 3–6 dB pad (or enforce a known-good 50 Ω termination) at the LO port and re-measure; if PN/spurs improve at TP3 without changing TP0, the issue is termination/isolation.
Fix
Add a permanent pad or improve port matching and reverse isolation (buffer choice/placement); verify the connector/cable load is within the intended impedance window.
Pass criteria
TP3 PN points and spur mask pass with the worst-case intended load/cable, and TP0→TP3 degradation stays within the allocated additive/isolation budget.
Dithering reduces spur but raises noise floor—how to choose the “least harmful” mode?
Likely cause
Dither spreads discrete energy into the noise floor; the trade is spur reduction versus elevated wideband noise at mask points.
Quick check
Compare 2–3 dither/SDM modes using the exact spur mask lines and required PN offset points; record (spur peak dBc) and (PN dBc/Hz at mask offsets) for each mode.
Fix
Select the mode that keeps PN mask points within margin while pushing the failing spur below mask; if needed, slightly re-tune BW to recover close-in points after mode selection.
Pass criteria
Both (spur mask) and (PN mask points) pass simultaneously under the chosen dither/SDM mode and across required channels/configs.
Lock time is okay, but spurs increase during hopping—what settling/measurement trap to avoid?
Likely cause
The measurement is capturing transient settling (fast-lock, VCO calibration, loop recovery) rather than steady-state spur performance.
Quick check
Use a fixed dwell delay after each hop and verify spur level converges (zero-span at the spur offset is fastest); compare spur readings at t=0, t=[Tsettle/2], t=[Tsettle].
Fix
Define and enforce a hop-to-measure settling time in firmware/test, and avoid “peak hold” or long sweeps that blend transients into the reported spur mask result.
Pass criteria
After the defined settling time [Tsettle], spurs at sensitive offsets are ≤ [Spur mask] for all hops in the plan, and results are repeatable across 3 runs.
