SPI / I²S Bridges & Mux for Level and Clock-Domain Conversion
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SPI / I²S bridges and muxes make multi-device interconnects reliable by turning timing, level, and routing into measurable budgets and repeatable switch/validation steps.
This page maps each topology to concrete pass/fail criteria and production-ready test hooks, so “it works” becomes “it has margin” across cable length, temperature, and manufacturing variation.
H2-1. Definition & scope
Intent
Establish clear engineering definitions for bridge/mux/switch/gateway, map typical use-cases, and lock the page boundary so later sections stay deep (not wide).
What this page covers
- Move SPI / I²S / TDM signals across selection points, domains, and distance.
- Handle level shifting, clock relationships, routing safety, and observability.
- Turn “works on bench” into repeatable bring-up and production outcomes.
Hard boundaries (to prevent topic overlap)
- No OS/driver/app protocol deep-dive (register semantics, software stacks).
- No audio DSP theory (filters/codecs internals); only bus interop & timing.
- No generic PLL/phase-noise textbook; only interface-side clock/jitter criteria.
Deliverables (practical outputs)
- Selection metrics (latency, skew, CDC, tri-state, slot map, observability).
- Reference topologies (SPI multi-slave, I²S fan-out, TDM slot routing, SerDes remote I/O).
- Timing pass criteria (setup/hold/skew/jitter/turnaround budgets).
- Validation plan (bench → bring-up → production test hooks).
- Failure signatures for fast debug (symptom → likely layer → first probe).
Engineering definitions (by signal / clock / control paths)
Mux
Selects one of several signal routes; typically transparent to protocol. Clock is usually passed through (but adds skew/prop delay). Control selects the route.
Switch
Connects/disconnects electrical paths like controlled wiring. It is clock-agnostic and focuses on signal integrity (Ron, capacitance, leakage).
Bridge
Adapts bus behavior (buffering, retiming, CDC, format packing). Often introduces state machines and observability counters.
Gateway
Terminates one side and reconstructs the other side (more endpoint-like). Mention-only here; deep protocol layers belong to dedicated pages.
Typical use-cases (problem → common failure → best-fit category)
SPI master ↔ multi-slave routing
Problem: select CS paths and prevent MISO contention while extending length. Failure: intermittent readback errors, “only-read/only-write”, cable sensitivity. Fit: mux/switch for routing; bridge when buffering/retiming/CDC is required.
I²S source ↔ multiple codecs/amps
Problem: distribute/switch BCLK/LRCLK/SD without breaking phase relationship. Failure: pop/click, channel swap, occasional sample drop. Fit: I²S mux/switch with safe switching; bridge if buffering or format adaptation is needed.
TDM slot aggregation / remap
Problem: combine/split channels by slot maps with deterministic frame sync. Failure: silent channels, wrong slot, 1-bit alignment shift. Fit: TDM aggregator/router with slot map + mute behavior + observability.
SerDes remote I/O (board/cable)
Problem: move synchronous buses across distance/noisy domains with robust recovery. Failure: relock variance, latency drift, hard-to-see link faults. Fit: SerDes bridge with remote deserialize + clear lock/fault visibility.
H2-2. Taxonomy & architecture map
Intent
Convert “what device class is needed?” into a first-principles selection map using four dimensions: clock-domain crossing, distance, buffering/retiming, and observability.
SPI path
Pure mux (shared SCLK/MOSI, switch CS)
- Best when timing margin is already healthy.
- Primary risks: CS glitch, MISO tri-state contention.
Multi-master / arbitration (risk callout)
- Rare; complexity often outweighs benefit.
- Primary risks: bus lock, recovery ambiguity.
SPI↔SPI bridge (FIFO / retime / isolate)
- Used when buffering/CDC/extension is unavoidable.
- Primary risks: added latency + state machine corner cases.
I²S / TDM path
I²S mux / switch (external clocks)
- Preserves synchronous relationship when switching is safe.
- Primary risks: pop/click, LRCLK phase/edge corruption.
TDM aggregator (multi I²S → single TDM)
- Solves channel scaling when SoC TDM lanes are limited.
- Primary risks: slot alignment drift, deterministic latency not tracked.
TDM router (slot remap / mute / optional gain)
- For complex channel routing and safe reconfiguration.
- Primary risks: “empty slot behavior” mis-set looks like a hardware fault.
SerDes bridge (remote transport)
parallel/synchronous → serialized (with remote deserialize)
- Targets board-to-board or cable distance and noisy ground domains.
- Key requirements: lock visibility, error counters, deterministic recovery.
Selection dimensions (used throughout the page)
- CDC: does the solution cross clock domains?
- Distance: is transport local or remote?
- Buffer/retime: is FIFO or retiming required?
- Observability: are faults measurable (status/counters/loopback)?
H2-3. Signals & timing fundamentals
Intent
Quantify the variables that most often break bridges and muxes: edge relationships, data windows, turnaround behavior, and deterministic slot alignment—so CDC, SI, validation, and production criteria can be built on a single timing ledger.
SPI · minimum timing fields
- SCLK: frequency, duty, rise/fall (edge speed drives window loss).
- Mode: CPOL/CPHA defines the sampling edge (window anchors here).
- CS→SCLK: setup/hold around first/last edge (glitch risk).
- Setup/hold: MOSI/MISO stability vs the sampling edge.
- MISO turnaround: release/drive timing (contention shows up here).
Failure fingerprint
Intermittent readback errors or “only-read/only-write” behavior often indicates a reduced MISO window or tri-state contention during turnaround.
I²S · minimum timing fields
- BCLK/LRCLK: phase relationship and edge convention (sample vs change).
- Alignment: I²S vs left-justified defines MSB position vs LRCLK.
- Bit depth: effective bits and padding behavior (zeros vs sign-extend).
- Master: who sources clocks (master/slave affects CDC risk).
- Skew: data-vs-clock skew (fan-out/mux adds skew).
Failure fingerprint
Pop/click or channel swap after switching commonly points to LRCLK edge corruption, MSB misalignment, or unsafe switching without mute/hold sequencing.
TDM · minimum timing fields
- Frame sync: polarity/type (pulse vs level) and periodicity.
- Slots: count per frame and slot width (bits per slot).
- Empty slot: drive-0/drive-1/hold/Hi-Z (mis-set looks like a fault).
- Burst vs continuous: impacts FIFO sizing and underrun risk.
- Determinism: fixed latency and stable slot map across resets.
Failure fingerprint
A single silent channel with otherwise healthy framing often indicates slot-map mismatch, empty-slot behavior misconfiguration, or a 1-bit alignment shift.
Timing ledger (single language for SPI / I²S / TDM)
1) Source budget
- Edge speed (tr/tf) and output drive configuration.
- Clock quality proxy (cycle-to-cycle edge variation).
- Available data window vs sampling edge (baseline margin).
2) Interconnect penalty
- Propagation delay + channel skew (clock vs data mismatch).
- Duty distortion (DCD) and added edge uncertainty (Δt).
- Turnaround hazards (tri-state release/drive overlap on MISO).
3) Sink tolerance
- Setup/hold requirements and input threshold behavior.
- Clock/data skew limits and jitter sensitivity.
- Stable framing expectations (slot map and latency determinism).
Pass logic
Remaining margin = Source window − Penalty ≥ Sink requirement + Guardband. Guardband accounts for temperature, lot-to-lot variation, cable/fixture variance, and test-to-test correlation.
Minimal measurement loop (fast, repeatable)
Logic analyzer
Confirms mode, framing, slot map, and protocol-level structure (but not edge quality).
Oscilloscope
Measures tr/tf, ringing, skew, DCD, CS→SCLK edges, and turnaround windows.
Patterns
Use simple vectors (walking-1, fixed tones, slot markers) to expose 1-bit shifts and channel swaps.
H2-4. Level shifting & edge integrity
Intent
Focus on real failure mechanisms introduced by level conversion and routing devices: edge slowdown, threshold crossing uncertainty, tri-state contention, and clamp/ESD distortions. The goal is not “it toggles”, but “it has margin”.
Directionality & tri-state
- SPI MOSI and MISO behave differently; MISO turnaround defines contention risk.
- I²S data is one-way, but clocks/control can be shared and skew-sensitive.
- Routing devices must not leak-drive “inactive” paths during switching.
Quick check
Force-select a single slave path and observe whether MISO remains quiet when “inactive”. Any edge-correlated activity suggests contention or leakage drive.
Auto-direction risk
- Auto-sense direction may mis-detect during fast edges or MISO tri-state windows.
- Small timing shifts (temperature, cable, probe loading) can trigger “threshold failures”.
- Symptoms often appear only beyond a certain clock rate.
Rule
For high-speed SPI or any link with true tri-state turnaround, prefer explicit-direction buffering or dedicated one-way channels.
Threshold crossing uncertainty
- VIH/VIL mismatch + slower edges shrink the effective sampling window.
- Skew and duty distortion on clocks directly reduces setup/hold margin.
- What “looks like amplitude” can still fail at the threshold band.
Quick check
Measure 10–90% rise/fall and the time spread of threshold crossings (Δt) at the receiver pin. A larger Δt is a direct margin killer.
Overshoot, clamp, and ESD distortion
- Input clamps and ESD structures can create steps, rebound, or double-crossings.
- Long lines amplify reflections; probe ground choice can hide/reveal the issue.
- Small series R can often “linearize” the edge without changing logic levels.
Pass criteria
No secondary threshold crossings; ringing decays before the sampling window. Peak overshoot/undershoot stays below the clamp-trigger region (threshold-based X% limit).
Minimal edge KPIs (defines “margin”, not just “toggling”)
Rise/fall
Edge speed relative to unit interval (UI). Slower edges reduce data window and increase Δt.
Ringing
Peak and decay time. Dangerous when it causes secondary threshold crossings.
Duty (clock)
Duty distortion shifts sampling points and reduces setup/hold symmetrically.
Skew
Channel mismatch (clock vs data; lane vs lane). Fan-out/mux often increases it.
Δt (uncertainty)
Spread of threshold crossing times at the receiver—directly subtracts from margin.
H2-5. Clock-domain crossing & buffering (FIFO, retiming, phase relationships)
Intent
Turn “does this cross clock domains?” into a selectable architecture. Bridges and muxes fail when long-term rate error accumulates or when retiming changes phase relationships that receivers treat as hard constraints.
When CDC is mandatory (treat any “YES” as a hard trigger)
- Independent clocks: source and sink are driven by different oscillators/PLLs (not phase-related).
- Remote clock reconstruction: a far-end device rebuilds clocks (CDR/PLL) and is not locked to the source.
- Asynchronous links: even ppm-level frequency offset accumulates and forces slip over time.
- Recoverability required: the system must survive re-lock, hot-plug, or cable events without silent data corruption.
Practical consequence
“Short-term jitter” causes small fill-level wobble; “long-term rate error” causes monotonic drift that eventually overflows/underflows unless true rate matching is implemented.
Option A · Transparent path (no CDC)
- Use when: one domain, phase relationship is controllable and stable.
- Wins: lowest latency, simplest behavior, easiest determinism.
- Fails when: added delay/skew/edge uncertainty consumes the timing ledger margin.
What to monitor
Waveforms at the receiver pin: skew, duty distortion, ringing, and threshold-crossing spread (Δt).
Option B · Elastic buffer (small FIFO)
- Use when: clocks are related, but short disturbances must be absorbed.
- Wins: masks brief stalls and burstiness; improves local robustness.
- Fails when: long-term frequency offset exists (fill-level drifts to full/empty).
What to monitor
FIFO fill-level trend + near-full/near-empty counters. Wobble is fine; monotonic drift is a red flag.
Option C · Async FIFO + rate matching (true CDC)
- Use when: clocks are independent or rebuilt at the far end.
- Wins: absorbs long-term ppm offset; enables stable behavior over temperature and time.
- Fails when: reset/alignment strategy is weak (silent slip or mis-framing).
What to monitor
Fill-level long-term stability, slip events, and alignment-marker consistency across resets/relocks.
Option D · Retiming (re-sampling edges)
- Use when: edge quality collapses (slow edges, large Δt, heavy ringing).
- Wins: restores clean sampling points; improves eye/window locally.
- Fails when: phase/latency changes violate receiver expectations (hard constraints).
What to verify
Added delay determinism, phase shift, duty distortion, and whether latency is fixed or mode-dependent.
I²S/TDM special case: phase relationships are hard constraints
Clock-data coupling
BCLK/LRCLK define sampling boundaries. Any structure that changes phase or makes delay variable must include explicit frame/slot alignment rules and observability.
Slip looks like audio bugs
A 1-bit or 1-slot slip manifests as channel swap, periodic clicks, or silent lanes—not “protocol failure”.
Guardbanding
Validate across temperature and long runs. Track fill-level drift and alignment markers; do not rely on “works at boot”.
Selection rules (one-line decisions)
- Same clock source and stable phase → choose Transparent; manage margin via edge integrity (H2-4).
- Only short disturbances → choose Elastic buffer and monitor fill-level.
- Independent/rebuilt clocks or long-term drift → choose Async FIFO + rate matching.
- Window collapses due to edges/Δt → consider Retiming only if phase/latency changes are allowed.
- I²S/TDM → any variable-latency structure requires explicit frame/slot alignment and observability.
Minimal validation loop (distinguish short-term vs long-term issues)
- Track fill-level trend: wobble is acceptable; monotonic drift indicates rate mismatch.
- Count events: underflow/overflow/relock counters reveal silent failures.
- Use alignment markers: frame/slot markers must remain stable across resets and long runs.
H2-6. SPI bridging & muxing patterns (topologies and common pitfalls)
Intent
SPI failures in bridge/mux systems are dominated by chip-select glitches, MISO tri-state reality, readback window loss, and long-line reflections that masquerade as software issues. This section turns those risks into repeatable patterns and fast discrimination tests.
Five variables that decide success (align with the timing ledger)
CS integrity
CS→SCLK setup/hold and glitch-free switching determine whether devices interpret a transaction boundary correctly.
MISO tri-state
Unselected slaves must be truly high-Z; weak drive or clamp behavior can still corrupt readback.
Turnaround
Release/drive timing around reads (MISO turnaround) is where contention and window collapse show up first.
SCLK edges
Reflections can create secondary threshold crossings, effectively generating extra “edges” and bit slips.
Mode/rate changes
CPOL/CPHA and frequency transitions can break internal timing if the bridge/mux does not re-arm cleanly.
Pattern A · CS fan-out (one master, many slaves)
- Requirement: glitch-free CS switching; avoid CS transitions while SCLK is active.
- Risk: a CS glitch can be interpreted as a transaction boundary and push slaves into illegal states.
- Mitigation: enforce “close-before-open” sequencing and hold SCLK in a safe idle state.
Quick check
Probe CS and SCLK at the mux output: verify CS edges do not coincide with active SCLK toggling.
Pattern B · MISO return isolation (contention control)
- Problem: “unselected” slaves may still weak-drive or clamp MISO.
- Symptom: write looks stable; read intermittently fails or depends on which slave is active.
- Mitigation: dedicated return mux, per-slave isolation/series R, or explicit tri-state control.
Quick check
Force-select a single slave and hold others inactive; if readback stabilizes, prioritize contention isolation.
Pattern C · Long lines and bit slips (reflection-driven)
- Mechanism: SCLK ringing can create secondary threshold crossings.
- Symptom: occasional byte/bit shift, worse at higher rate or with longer cabling.
- Mitigation: source series R, controlled edge rate, improved return path and termination strategy.
Quick check
Add a small series resistor at the driver; if errors drop sharply, reflection/edge integrity is the primary driver.
Pattern D · Mode/rate transitions (state re-arming)
- Mechanism: CPOL/CPHA changes alter sampling edges; bridges must re-arm cleanly.
- Symptom: stable at a fixed mode, fails after switching modes or rates.
- Mitigation: enforce safe-idle switching, re-initialize bridge state, validate per-mode timing.
Quick check
Lock mode and rate to a single setting; if failures vanish, the transition path (not steady-state timing) is at fault.
Bring-up & production: fast discrimination (timing vs contention)
- Single-slave isolate: force one CS active, others inactive. If readback improves, prioritize MISO isolation.
- Read-only vs write-only: if read is worse, focus on MISO turnaround and return-path window.
- Near vs far probing: capture SCLK/MISO at the source and at the slave; secondary crossings imply reflection risk.
- Loopback (if available): if loopback passes but real slave fails, the slave-side tri-state/window is the limiting factor.
H2-7. I²S & TDM interop (aggregation, splitting, slot management)
Intent
Cover bus interconnect and interoperability only: format alignment, slot semantics, and master/slave clock strategy. The goal is not “audio plays”, but “format is deterministic and production-verifiable”.
I²S interoperability deltas (what must be pinned down before wiring)
Alignment
I²S vs Left-Justified/Right-Justified: MSB alignment point relative to LRCLK edge must match the sink expectation.
Bit depth & padding
16/24/32-bit word width and how unused bits are padded (0/1/hold) must be defined to avoid “quiet but wrong”.
Channel polarity
LRCLK polarity mapping (L/R meaning of LRCLK=0/1) must be consistent, or channels swap silently.
Sampling edge
BCLK sampling edge and data-valid window must align across the bridge/mux; retiming/added skew reduces margin first.
Interop checklist output
Record: format (I²S/LJ/RJ), word width, pad policy, LRCLK polarity, BCLK edge, and any required frame markers before implementing aggregation or splitting.
TDM interoperability: slot semantics > “bus toggles”
Slot map
Slot index → channel mapping must be explicit (ch0/ch1/…); remap must preserve frame boundary determinism.
Mute slot
Define mute behavior per sink: write 0, write 1, or hold-last. Mute ambiguity causes inconsistent production results.
Empty slot policy
Unused slots must be defined as 0 / 1 / Hi-Z. “Hi-Z” can be interpreted as noise and trigger false activity.
Frame configuration
Slots-per-frame, slot width, and continuous vs burst framing must match receiver expectations to prevent slips.
Master/slave clock strategy (BCLK/LRCLK ownership)
Who is master
Choose the domain whose sampling clock must be authoritative (lowest jitter / system reference). Avoid dual-master ambiguity.
Distribution
Fan-out topology and skew control matter more than “it toggles”. Multi-sink systems need low-skew clock distribution.
Interop risk signature
A “works at boot” system that later clicks or swaps channels commonly indicates master mismatch or frame-boundary slip.
Decision rules
- Multiple sinks + phase sensitive → enforce a single master and observable clock distribution.
- Slot remap/mute/empty-slot semantics differ → require a TDM router/aggregator with explicit slot policy.
- Reset/relock must be production-safe → require alignment markers and counters; avoid “no-observability” designs.
Latency & synchronization (fixed delay calibration; avoid L/R misalignment)
Deterministic vs variable
Aggregation/splitting introduces pipeline delay. Production systems require determinism or an explicit re-alignment method.
L/R symmetry
Ensure left and right channels see matched delay. Any asymmetry becomes channel skew and can show up as spatial shift.
Slip signature
A 1-bit or 1-slot slip presents as periodic clicks, wrong channel mapping, or intermittent silence—not a clean fault flag.
“Audible” vs “production-ready”: minimum verification set
Frame capture
Capture LRCLK/FS and verify slot boundary consistency and channel polarity across resets and long runs.
Tone pattern
Use deterministic patterns (L-only / R-only / alternating) as markers to prove remap and mute policies.
Pass criteria
Over a defined run, no slot slips; channel mapping remains stable; L/R alignment error < X samples; mute/empty-slot behavior matches policy under reset/relock events.
H2-8. SerDes bridges for remote I/O (move synchronous buses to the far end)
Intent
Describe SerDes-ifying SPI/I²S/TDM as an engineering choice: packaging/unpackaging, clock strategy, observability, and fail-safe behavior under link loss—not a high-speed protocol tutorial.
Typical uses (when SerDes is system-level margin)
- Remote codec/ADC placement: move data conversion away from noisy zones or thermal hot spots.
- Board-to-board / cable extension: connectors and harnesses where parallel timing becomes fragile.
- Pin/resource pressure: reduce wide synchronous interfaces into a small serialized link.
- Field diagnostics: require lock state and error counters for production and serviceability.
Rule of thumb
When distance, isolation needs, or environment make the synchronous timing ledger impossible to guardband, SerDes is a system-level mechanism to regain determinism and observability.
Architecture primitives (DATA / CLK / CTRL as first-class paths)
Packaging
Local side packs synchronous payload (SPI frames or I²S/TDM frames + markers) into a serialized stream.
Clock strategy
Decide forwarded clock vs recovered clock. Recovered clock implies true CDC behavior and requires alignment observability.
Control sideband
Provide SPI/I²C control as a sideband channel or as an embedded logical channel. Decide behavior under link loss.
Key metrics that change system behavior (treat as selection inputs)
Latency
End-to-end link latency must be known. Determine if latency is fixed or mode-dependent (retraining, rate changes).
Lock/training time
Boot-to-audio time and relock time define UX and system recovery behavior. Track lock state explicitly.
Error handling
BER alone is insufficient; define CRC/retry/drop behavior and how the far end presents errors to the system.
Observability
Lock state + error counters + slip/marker counters are required for production screening and field diagnostics.
Relationship to SPI & I²S/TDM (separate vs combined transport)
Separate control
SPI control stays usable for recovery (mute/reset/diagnostics) even if the data link is degraded, but requires defined reset ordering and consistency rules.
Combined transport
Single link is simpler, but link loss removes control. Fail-safe and recovery must be implemented without relying on the missing control plane.
Decision rule
If the system must remain controllable under link loss (mute/reset/diagnose), prioritize an independent control mode or a resilient sideband.
Fail-safe behavior under link loss (define “bad-state shape” upfront)
Audio output state
Choose a deterministic output policy: mute, hold-last, or force-zero. Verify behavior across lock loss and relock.
Relock alignment
After relock, frame/slot alignment must be re-established deterministically to avoid channel swaps and clicks.
Pass criteria
On link loss, enter safe state within Y ms. After relock, restore stable audio within Z ms with no persistent error counter growth.
Minimal validation set (lock state + latency + pattern)
- Read link status: lock state and error counters must be accessible and logged.
- Measure latency: verify fixed vs variable latency across mode changes and retraining.
- Exercise recovery: repeat reset/hot-plug/relock and confirm alignment markers remain stable.
H2-9. Control plane & configuration (registers, power-up order, state machine)
Intent
Treat configuration, power-up, and state as engineering actions. Avoid driver implementation details, but make initialization, safe switching, and recovery deterministic and production-verifiable.
Power-up, reset, and default routing (prevent startup glitches)
Default route
Define the post-reset route selection: which path is enabled, which outputs are gated, and whether a “safe route” can be strapped or stored.
Output policy
During reset and configuration windows, enforce a deterministic output policy (mute / hold / force-zero / Hi-Z) to prevent burst noise and undefined frames reaching codecs or amplifiers.
Glitch sources
Common glitch sources include unstable strap pins, rail sequencing causing input clamp conduction, and a “dead zone” between reset deassertion and the first valid configuration write.
Production pass criteria
From power-up to “stream enabled”, the system stays in a safe audio state and does not emit switching bursts; any transient at the output stays below X (system-defined limit) and does not correlate with reset/config events.
Configuration channel conflicts (control bus vs bridged bus)
Conflict model
When the bridge/mux is configured over I²C/SPI while also bridging SPI traffic, shared wires can create bus ownership ambiguity and MISO contention.
Isolation strategy
Prefer an independent control channel. If sharing is unavoidable, enforce a strict time-division policy: “configure window” → “open window” → “fault fallback window”, with hard isolation in between.
MISO tri-state rule
At any instant, only one device is allowed to drive MISO. Ownership must be switched only after entering a safe state.
State observability (the production gate)
Must-read status
- LOCK / STREAM_ACTIVE
- CRC_ERR / FRAME_SLIP
- UNDERFLOW / OVERFLOW
- FIFO LEVEL (or high/low water)
- ACTIVE_ROUTE / PENDING_ROUTE
Minimum log fields
Version/build ID, configuration summary, lock time, counter snapshots (delta), route history, last fault reason code, and recovery attempt count.
Pass criteria
Over a defined run time T, LOCK remains asserted; slip counters stay at 0; under/over flags never assert; CRC counters do not grow persistently.
Safe switching (route change sequence template)
Step 1 — Pre-mute
Enter a deterministic safe audio state before any re-route (mute/zero/hold). This prevents partial frames from reaching sinks.
Step 2 — Stop or freeze (optional)
Gate BCLK/LRCLK or freeze output if supported. Use only when required by the sink’s alignment constraints.
Step 3 — Flush & align
Flush FIFOs and switch only on a frame boundary or marker. This prevents frame slip and channel swaps.
Step 4 — Switch route
Perform the route change as an atomic action where possible. Avoid intermediate states that expose both sources or neither.
Step 5 — Verify & unmute
Re-enable stream, confirm LOCK and counters remain stable, then exit safe audio state. Define a maximum retry count.
Switch pass criteria
After a switch request, within N frames the route is stable; slip counters remain 0; CRC/error counters do not jump; safe-audio exit produces no burst events.
Fault → recover (define system behavior, not just chip behavior)
Fault classes
- LOCK loss / relock oscillation
- CRC storm / frame slip growth
- FIFO under/over asserts
- Route mismatch / pending route timeout
Recovery policy
Enter safe-audio immediately, attempt relock with a bounded retry count, then escalate to hard reset and reconfigure. Always re-verify alignment markers and routing after recovery.
Production pass criteria
On fault, safe-audio is asserted within Y ms; recovery completes within Z ms; error counters stop growing; routing and channel mapping remain correct after relock.
What this implies for device selection (control-plane checklist)
Must-have
- Readable LOCK and error counters
- Deterministic default route / safe output
- Atomic or glitch-safe route switching
- FIFO / alignment observability
Strongly preferred
- Hardware mute/zero policy
- Frame-boundary aligned switching
- Configurable empty-slot and remap policy
- Reason codes for fault classification
H2-10. Validation, debug & production test hooks (bench → A/B → factory)
Intent
Build a repeatable test plan and close the loop with selection metrics: compare direct vs bridged paths, change one variable at a time, and express pass/fail using counters, frame integrity, and deterministic patterns.
The A/B rule: direct vs bridge, change one variable
Baseline
Establish a direct-connection baseline. Every bridge/mux change must be compared against this reference.
One variable
Change only one variable per run: rate, cable length, temperature, supply corner, load, or clock source.
Record signatures
Log failure signatures (slip, channel swap, burst noise, read-only/write-only SPI, counter storms) with time correlation.
Suggested run record
Config summary + variable value + counter deltas + captured frame snapshot + observed symptom + next suspected path.
Bench verification (minimum instrumentation and what to capture)
Oscilloscope
Capture clock edges and duty/skew around the bridge. Compare direct vs bridged at identical load and probe setup.
Logic analyzer
Capture frame boundaries, slot mapping, LR polarity, and SPI transaction integrity. Prefer a dedicated LA header.
Deterministic patterns
Use known patterns (1 kHz tone, L-only/R-only alternating, walking ones) as markers to prove mapping and alignment.
Loopback hooks (cut the problem by layer)
Layer 1 — SPI loopback
Verify directionality and bus ownership. Failures here often map to MISO contention or control/bridged-bus conflicts.
Layer 2 — TDM slot loopback
Mirror slot i to slot j (or to a debug slot) to validate remap, mute, and empty-slot policy without changing endpoints.
Layer 3 — Link loopback (if available)
Isolate the SerDes link from the remote endpoint and validate CRC/BER behavior under controlled stress.
Counters and digital pass/fail (capture “rare” as numbers)
Delta counters
Use counter deltas over a defined run window, not single snapshots. Rare faults become measurable.
Suggested pass/fail
FRAME_SLIP = 0; UNDER/OVER = 0; CRC_ERR < X; LOCK remains asserted for T seconds; route switch yields no counter spike.
Factory screening flow (bench compressed into a reproducible plan)
Stage 1 — Bring-up self-check
Read ID/version, clear counters, confirm default route, program configuration summary, and verify lock time is within spec.
Stage 2 — Pattern + loopback
Run deterministic patterns, validate slot mapping with loopback, and ensure directionality (SPI) with ownership rules enforced.
Stage 3 — Stress corners
Sweep one corner at a time (rate/temperature/cable) and accept only if counter deltas stay within limits and no slips appear.
Common failure fingerprints (symptom → quickest check → likely path)
Read-only / write-only SPI
Quick check: MISO ownership and tri-state release; confirm control bus is not sharing with bridged SPI without isolation. Likely path: contention, mis-isolation, wrong windowing.
L/R swapped or wrong channel
Quick check: LRCLK polarity + slot map + marker capture. Likely path: remap configuration, polarity mismatch, frame-boundary slip.
Periodic pops / frame drops
Quick check: FIFO under/over flags and delta counters across a fixed time window. Likely path: clock drift, CDC policy, inadequate buffering.
Selection closure: test hooks as requirements
Hard requirements
- Readable lock + error counters
- Loopback or equivalent isolation hooks
- Deterministic safe state on faults
- Frame/marker observability for alignment
Why it matters
Without built-in hooks and counters, validation collapses into subjective symptoms; production screening becomes inconsistent across lots, temperature, and harness variation.
H2-11. Engineering checklist (Design → Bring-up → Production)
Intent
Convert earlier sections into executable, checkable gates. Each item maps to a measurable outcome using hooks and counters (see H2-10) and controlled state transitions (see H2-9).
Gate A — Design checklist (define constraints before layout)
Checklist
- ☐ Voltage domains & VIH/VIL limits fixed
- ☐ Clock master defined (SCLK, BCLK/LRCLK)
- ☐ Format pinned (I²S/LJ/RJ, TDM slots/width)
- ☐ Max rate + margin strategy documented
- ☐ Topology/length bounded (stubs/connectors)
- ☐ SPI ownership rule enforced (single MISO driver)
- ☐ Safe-state policy defined (mute/hold/zero/Hi-Z)
- ☐ Test hooks reserved (TP/LA header/loopback)
Pass criteria (examples)
- All rails and level translation satisfy VIH/VIL with margin.
- Default route is safe: no unintended stream during reset/config.
- Reserved access points exist for scope/LA and loopback enable.
Note
Prefer direction-controlled translators for SPI/MISO. Auto-direction families can fail with high-speed edges and tri-state behavior.
Example material numbers (verify package/suffix/availability)
SPI bus switch / Mux
TI SN74CBTLV3257
TI TS5A23157
ADI ADG772 / ADG774
Level translators (direction-controlled)
TI SN74LVC1T45
NXP 74LVC2T45
Auto-direction (use with care)
TI TXS0108E
TI TXB0108
Digital isolation (SPI/I²S/TDM)
TI ISO7741 / ISO7742
ADI ADuM1401
ESD protection arrays
TI TPD4E05U06
Nexperia PESD5V0S1UL
Littelfuse SP0502BAHT
Passives (edge control / EMI)
Series R: Yageo RC0402FR-0733RL (33 Ω, 1%)
Ferrite: Murata BLM18AG601SN1D
Clock buffer (if needed)
TI CDCLVC1102
TDM/slot remap alternative
Lattice iCE40UP5K (small FPGA)
Gate B — Bring-up checklist (make failures classifiable)
Checklist
- ☐ Minimal boot order fixed (power → reset → cfg → lock → stream)
- ☐ Safe-switch template used (mute → stop → flush → switch → verify)
- ☐ Counter baselines captured (LOCK/ERR/SLIP/FIFO deltas)
- ☐ A/B run: direct vs bridged (one variable per run)
- ☐ Marker patterns verified (L-only/R-only, walking ones, 1 kHz tone)
- ☐ Route switching stress tested (N switches without counter spikes)
- ☐ Fault→recover policy verified (bounded retries, then reset)
Pass criteria (examples)
- LOCK remains asserted for T seconds under nominal conditions.
- SLIP = 0; UNDER/OVER = 0; CRC_ERR < X over the delta window.
- Switching produces no burst events and no persistent counter growth.
Bring-up utilities (examples)
USB-to-SPI bridge (debug): Microchip MCP2210, FTDI FT2232H
Gate C — Production checklist (freeze vectors, thresholds, and logging)
Checklist
- ☐ Fixture + access points finalized (TP/LA/loopback enable)
- ☐ Test vectors frozen (pattern + loopback + corner sweep)
- ☐ Numeric pass/fail thresholds locked (counter deltas)
- ☐ Environmental fields logged (temperature, rails, cable batch, fixture ID)
- ☐ Switch stress included (N consecutive switches)
- ☐ Failure fingerprints mapped to next checks
- ☐ Retest and quarantine rules defined
Material examples (screening focus)
ESD arrays: TI TPD4E05U06; Nexperia PESD5V0S1UL
Isolation: TI ISO7741; ADI ADuM1401
Mux/switch: TI SN74CBTLV3257; TI TS5A23157
Series R: Yageo RC0402FR-0733RL; Ferrite: Murata BLM18AG601SN1D
Logging must include
Temperature, rail setpoints/actuals, harness/cable batch, fixture ID, configuration summary, lock time, and counter deltas.
H2-12. Applications (project mapping only, no extra theory)
Intent
Map real projects to selection and validation hooks. Each scenario provides: a one-line topology, key metrics, and the exact hooks to run (H2-10, H2-11).
Industrial: long-run SPI sensors & remote I²S capture
Topology: Host SPI + I²S/TDM → mux/bridge + protection (+ isolation if needed) → remote sensor/codec domain.
Key metrics
- SPI readback margin (MISO ownership, turnaround window)
- Edge quality after protection/isolation (rise/fall, ringing)
- Frame integrity (SLIP=0, FIFO under/over=0 over T)
- Fault response (safe-audio asserted within Y ms)
Validation hooks
- A/B: direct vs bridged; sweep one variable (length/temperature)
- Use counter deltas (LOCK/ERR/SLIP/FIFO) over a fixed window
- Loopback first: SPI loopback → TDM slot loopback
Example materials
Mux/switch: TI SN74CBTLV3257; TI TS5A23157
Isolation: TI ISO7741; ADI ADuM1401
ESD: TI TPD4E05U06; Nexperia PESD5V0S1UL
Series R: Yageo RC0402FR-0733RL; Ferrite: Murata BLM18AG601SN1D
Consumer: multi-source audio switching & TDM aggregation
Topology: Multiple I²S sources → switch/mux → TDM aggregator (or slot remap) → single SoC ingress.
Key metrics
- Glitch-free switching (no burst; counters stable)
- Slot mapping correctness (no L/R swap; no wrong channel)
- Deterministic latency (switch settles within N frames)
Validation hooks
- Safe switch template (mute → stop → flush → switch → verify)
- TDM slot loopback + marker patterns (L-only/R-only)
- Switch stress: N consecutive switches without counter spikes
Example materials
Switch: TI TS5A23157; ADI ADG772
Slot remap/aggregation: Lattice iCE40UP5K (small FPGA)
Level shift (direction): TI SN74LVC1T45; NXP 74LVC2T45
ESD: TI TPD4E05U06
Device debug: external SPI bridge + I²S/TDM monitor tap
Topology: External debug control plane → isolated/controlled SPI access → target; optional I²S/TDM “tap” for frame visibility.
Key metrics
- Bus ownership (avoid control-vs-bridged conflicts)
- Observability (LA header/TP points; readable counters)
- Debug attach/detach does not change timing margin (A/B proof)
Validation hooks
- SPI loopback first to prove direction and contention-free MISO
- Counter delta window to capture rare faults
- Safe state enforced before route/ownership changes
Example materials
USB-to-SPI bridge (debug): Microchip MCP2210; FTDI FT2232H
Isolation (if needed): TI ISO7741; ADI ADuM1401
Controlled access switch: TI SN74CBTLV3257; TI TS5A23157
ESD: TI TPD4E05U06
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H2-13. FAQs (SPI / I²S / TDM bridges & mux) — actionable, data-structured
Format
Each answer is exactly four lines: Likely cause / Quick check / Fix / Pass criteria (numeric thresholds use X/N/T placeholders, to be set by the system timing/noise budget).
SPI readback has intermittent errors: check MISO contention or sampling edge first?
Likely cause: MISO is not fully tri-stated during device switches, or the MISO valid window is too tight at the sampling edge.
Quick check: Capture CS+MISO on a logic analyzer; look for MISO driving when the target device is not selected. Scope SCLK/MISO and verify MISO crosses VIH/VIL only once near the sampling edge.
Fix: Enforce single-driver ownership and add controlled isolation on MISO (e.g., TI SN74CBTLV3257 or TI TS5A23157 as a gated path); add series R on SCLK/MISO (e.g., Yageo RC0402FR-0733RL 33 Ω, 1%). (Verify package/suffix/availability.)
Pass criteria: Over T seconds, readback errors < X (or CRC_ERR delta < X) and no evidence of non-selected MISO drive events.
The same board fails when cable/trace length changes: what A/B proves reflection instead of software?
Likely cause: Reflection/ringing creates multiple threshold crossings or shifts the effective sampling point, causing bit slips.
Quick check: Run an A/B test changing only length; scope SCLK at the receiver end and check for overshoot/undershoot and second crossings near VIH/VIL. Keep firmware/config constant.
Fix: Add source series termination on SCLK (e.g., Yageo RC0402FR-0733RL 33 Ω) and limit stubs; if a clock fan-out exists, use a proper buffer (e.g., TI CDCLVC1102). (Verify package/suffix/availability.)
Pass criteria: At maximum length, SCLK shows 0 extra VIH/VIL re-crossings and error counters remain flat (delta = 0) over T seconds.
After switching SPI mode, only some slaves fail: what bridge/mux “state residue” is most common?
Likely cause: The route or timing state is not fully reset (CS gating, internal enable, or edge relationship expectations), so the first transaction after a mode change violates the slave’s setup/hold.
Quick check: Compare “mode change with flush/reset” vs “mode change without it”; capture CS-to-first-SCLK timing and confirm the first frame is not truncated or shifted.
Fix: Standardize a mode-switch sequence: stop traffic → deassert CS → flush/disable route → reconfigure → re-enable route → verify; if needed, gate the route with a controlled switch (e.g., TI SN74CBTLV3257). (Verify package/suffix/availability.)
Pass criteria: Mode switch repeated N times shows 0 first-frame failures and readback errors < X.
I²S has audio but left/right are swapped: shortest path to confirm LRCLK phase/alignment?
Likely cause: LRCLK polarity or I²S vs LJ/RJ alignment mismatch causes channel interpretation to flip.
Quick check: Play a deterministic marker (L-only then R-only) and capture LRCLK/BCLK/SD; verify the MSB position relative to LRCLK edge matches the configured format.
Fix: Lock the bus format (I²S/LJ/RJ + word length + padding) across endpoints; if remap is unavoidable, implement explicit slot/channel routing (e.g., small FPGA such as Lattice iCE40UP5K). (Verify package/suffix/availability.)
Pass criteria: With L-only/R-only markers, cross-channel leakage < X dB and no audible swap across N reboots.
TDM has intermittent pops: how to quickly classify underrun vs overrun (what counters/watermarks)?
Likely cause: FIFO underrun (consumer faster than producer) or overrun (producer faster than consumer) due to clock drift or wrong buffering strategy.
Quick check: Read underrun/overrun flags and FIFO level watermarks; correlate pop events with counter deltas and whether FIFO hits low/high thresholds.
Fix: Add/enable elastic buffering and set stable watermarks; ensure switching uses “mute → stop → flush → switch → verify” before resuming stream. (Optional isolation for noisy domains: TI ISO7741 / ADI ADuM1401.) (Verify package/suffix/availability.)
Pass criteria: Over T seconds at worst-case conditions, UNDERRUN = 0, OVERRUN = 0, and FIFO stays within [L, H] with margin.
TDM slot mapping is correct but one channel is silent: what “empty-slot behavior” mis-setting is most common?
Likely cause: Empty-slot output policy is wrong (Hi-Z/hold vs forced 0/1), causing the receiver to treat the slot as invalid or muted.
Quick check: Force a known pattern into the slot (e.g., constant mid-scale or toggling MSB) and verify the slot waveform exists and matches expected bit order/width.
Fix: Explicitly set empty-slot behavior and keep it consistent across the chain; if the bridge/mux cannot enforce it, implement a slot sanitizer/router (e.g., Lattice iCE40UP5K). (Verify package/suffix/availability.)
Pass criteria: Target slot shows expected activity (energy/amplitude > X) and the channel is not muted across N power cycles.
Switching audio sources causes pop/click: mute first or stop clocks first — what order is correct?
Likely cause: Route changes while non-zero samples or active edges are present, producing discontinuities at the receiver.
Quick check: Compare two sequences and log burst/pops: (A) stop clocks first vs (B) mute first; correlate with counter deltas and waveform discontinuities.
Fix: Use a fixed safe-switch sequence: mute → stop stream (or hold SD) → flush/settle → switch route → verify alignment → unmute. For controlled routing, use a switch/mux like TI TS5A23157 or ADI ADG772. (Verify package/suffix/availability.)
Pass criteria: Perform N consecutive switches with 0 audible pops and no persistent error-counter growth (delta = 0) over T.
SerDes remote audio latency increases: check retraining/re-lock first or adaptive buffering first?
Likely cause: Link retraining/re-lock adds step latency, or adaptive buffering deepens FIFO to maintain continuity under drift.
Quick check: Correlate latency changes with link-lock events and FIFO watermark shifts; read lock-state counters and buffer-level telemetry around the event.
Fix: Stabilize the link (reduce triggers for retraining) and bound adaptive buffering; ensure fail-safe behavior on lock loss (mute/hold) is deterministic. (Isolation option for noisy sites: TI ISO7741 / ADI ADuM1401.) (Verify package/suffix/availability.)
Pass criteria: Latency remains within ±X frames over T and lock-state does not churn (re-lock count < X).
After level translation, SCLK amplitude looks OK but the link is unstable: threshold/edge or input clamp first?
Likely cause: Slow edges linger in the VIH/VIL threshold region, or input clamp/ESD structures distort edges and introduce jitter-like uncertainty.
Quick check: Measure rise/fall time and time spent inside [VIL, VIH]; inspect overshoot/undershoot at the receiver pin. Compare with a direct-connect baseline.
Fix: Prefer direction-controlled translators (e.g., TI SN74LVC1T45 or NXP 74LVC2T45) and low-cap ESD arrays (e.g., TI TPD4E05U06); add series R (e.g., Yageo RC0402FR-0733RL). (Verify package/suffix/availability.)
Pass criteria: rise/fall < X, no extra VIH/VIL crossings, and error counters remain flat (delta = 0) over T.
Logic analyzer frames look correct but audio sounds wrong: how to rule out a 1-bit slot alignment error?
Likely cause: A 1-bit slip at the slot boundary (MSB alignment) or inconsistent padding/word length across devices.
Quick check: Inject a deterministic pattern (walking ones or known alternating code) and verify MSB position and slot boundary across the entire chain; compare to the configured word length and alignment mode (I²S/LJ/RJ/TDM).
Fix: Lock word length/padding across all endpoints; if the bridge cannot guarantee alignment, add explicit bit/slot correction in a router (e.g., Lattice iCE40UP5K). (Verify package/suffix/availability.)
Pass criteria: Pattern verification yields bit errors = 0 over N frames and the audible artifact disappears.
Production yield collapses on a specific day: which missing environment/log fields are most common?
Likely cause: A process/environment change (cable batch, fixture, temperature, rail setpoints) is not recorded, preventing correlation and causing repeat escapes.
Quick check: Audit logs for: cable/harness batch, fixture ID, temperature, rail setpoint vs measured, configuration summary (format/slot mapping/mux route), and counter deltas during test.
Fix: Make these fields mandatory and add a fast A/B reproduction script; include screening components consistently (ESD: TI TPD4E05U06, isolation: TI ISO7741) if the site is noisy. (Verify package/suffix/availability.)
Pass criteria: Root cause can be explained by a logged variable; after the fix, yield returns to baseline and counter deltas remain within < X over T.
Failures only at cold temperature: check bridge delay drift first or receiver tolerance shift first?
Likely cause: Receiver timing tolerance shrinks (setup/hold/jitter margin reduces) or bridge/translation delay drifts beyond the timing ledger budget.
Quick check: Compare cold vs room baselines: capture edges and alignment markers; read error counters and FIFO events under identical traffic patterns and only change temperature.
Fix: Reduce rate or increase margin (series R, topology tightening); prefer robust direction-controlled translation (TI SN74LVC1T45) and consistent protection (TI TPD4E05U06). (Verify package/suffix/availability.)
Pass criteria: At cold corner, error counters stay within < X and no under/over events occur over T; functional test passes for N consecutive cold cycles.
Material numbers shown above are examples for engineering implementation only. Always verify package, suffix, voltage rating, speed grade, and availability against the latest datasheets and supply chain constraints.
