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Break/Wake & Idle Detect (UART) for Low-Power Wake-Up

Break/Wake & Idle Detect (UART) for Low-Power Wake-Up

← Back to: I²C / SPI / UART — Serial Peripheral Buses

Break/Idle wake makes UART a reliable “sleep → wake → confirm” control path: detect a clean wake preamble, require a short confirm token, then enter Active only when the bus is quiet and clocks are ready. This page defines the timing windows, false-wake immunity, and validation criteria so low-power wake-up stays fast, measurable, and stable in real cables and noisy environments.

Definition & Scope: Break / Wake / Idle Detect (UART)

Break and idle detection treat the UART RX line as a low-power wake sensor: a long LOW (BREAK) or a long HIGH/no-edges gap (IDLE) becomes an event that can exit Stop/Standby. Wake-up detection is not the same as “normal receive”; robust designs add timing guards and a post-wake confirmation step.

Term BREAK (line LOW extended)
  • What it is: RX stays LOW long enough to exceed normal frame semantics (longer than a typical start bit + data window).
  • Why it matters: a strong, unambiguous “attention” event for wake and re-sync, often used as a preamble in LIN-style workflows.
  • Keep scope tight: detailed frame-format breakdown belongs in the “Frame Format” page; this page focuses on wake and sleep coordination.
Term IDLE (no edges / line HIGH gap)
  • What it is: a continuous quiet window—no valid transitions—typically with RX held at the idle level (often HIGH).
  • Why it matters: a clean condition for entering sleep (bus quiet) and a programmable interrupt source for low-duty polling.
  • Design note: idle detection quality depends on edge/noise behavior; “false edges” can block idle, and “threshold drift” can fake it.
Term Wake source (Stop/Standby exit)
  • What it is: an event routed into an always-on domain that can exit deep sleep (e.g., WUF / wake interrupt).
  • Critical nuance: waking does not guarantee the UART clock, sampling, or DMA is already stable for the first payload byte.
  • Robust approach: wake on BREAK/IDLE, then require a post-wake confirmation pattern before entering full Active mode.
Scope guard This chapter defines BREAK/IDLE as wake primitives. Full UART framing, noise/error mechanics, and PHY level details should stay on their dedicated pages.
Three typical scenarios (where BREAK/IDLE fits)
Scenario A
System sleep → remote wake
  • Trigger: BREAK (or BREAK + short token) as an unambiguous wake request.
  • Risk: false wakes from glitches, and first-frame loss due to clock bring-up.
  • Hook: require a post-wake confirmation pattern inside a bounded window; otherwise return to sleep.
Scenario B
Bus quiet → low-power polling
  • Trigger: IDLE window reaching a programmable threshold (N bit-times / 1 frame-time).
  • Risk: spurious edges prevent idle; threshold drift fakes idle.
  • Hook: define a sleep-entry policy (quiet + debounce + guard) separate from normal receive logic.
Scenario C
LIN-style coordination: BREAK/IDLE as a wake preamble
  • Trigger: a wake request that looks like BREAK, followed by a bounded “listen-first” phase.
  • Risk: multi-node simultaneous wake → collisions.
  • Hook: after wake, enforce a confirmation + backoff rule before allowing transmissions.
Diagram: Normal frame vs BREAK vs IDLE gap (wire-level intuition)
RX line states used for wake-up sensing bit-time scale 1T 2T Normal BREAK IDLE normal frame: short LOW then HIGH stop BREAK: long LOW (wake preamble) IDLE: long HIGH / no edges LOW HIGH

What Exactly Triggers a Wake: Hardware Flags vs Line Reality

Wake-up behavior depends on where the RX event is detected: on the wire (edges/levels), inside the UART receiver state machine (framing/break/idle logic), or in a dedicated always-on wake tap. The same waveform can produce different flag combinations across vendors; correct design starts with a platform-specific wake check list.

Physical view What exists on the wire
  • Levels: RX holds HIGH (idle) or LOW (dominant) for a duration.
  • Edges: transitions can be real data edges or noise-induced glitches.
  • Durations: “long” must be defined in bit-times or a programmable timebase (guard + debounce included).
  • Failure mode: false edges can block IDLE; threshold drift can fake quiet/high windows.
Hardware view How UART RX interprets it
Break detect (common mechanism)
  • Stop-bit expectation: UART expects a HIGH stop; a sustained LOW causes framing error.
  • Break classification: if LOW persists beyond a vendor-defined threshold (often multiple bit-times), a BREAK flag is asserted.
  • Design implication: “framing error” and “break” can co-occur; designs should not rely on only one flag.
Idle detect (common mechanism)
  • Quiet window: no qualifying activity for N bit-times, 1 frame-time, or a programmable idle counter.
  • Edge sensitivity: depending on the IP, any detected edge (even noise) can reset the idle counter.
  • Design implication: idle is a timing construct; it must be paired with debounce/guard policy.
Wake view Platform wake check list (must confirm)
  • Wake sources allowed: RX edge? start bit? BREAK flag? IDLE flag? dedicated WUF?
  • Threshold units: BREAK(min) and IDLE(min) are defined in bit-times, frame-times, or a separate timebase.
  • Always-on domain: is RX sampling active in deep sleep, or is wake driven by a simpler edge detector?
  • Bring-up risk: after wake, confirm UART clock, sampling, FIFO/DMA readiness before trusting the first payload byte.
  • Flag lifecycle: how flags are latched/cleared and how quickly the wake tap reacts (avoid missing the wake preamble).

A robust default policy is wake → listen-first → confirm token: enter Active mode only after a bounded confirmation pattern arrives; otherwise return to sleep to suppress false wakes.

Diagram: UART RX path and where wake taps commonly exist
Always-on (low-power) detection island RX Input filter Edge detect Sampling /oversample RX state machine Flags BREAK IDLE WUF Wake taps may be: edge-based, state-based, or flag-based (platform dependent) Input filter helps reduce false edges that cause false wake or block IDLE Wake tap candidate location UART RX: wire signal → receiver logic → flags → wake routing

Timing Rules: Minimum Break Length, Idle Windows, and Guard Times

Reliable wake-up requires a time-parameter set that is consistent across hardware, firmware, and the remote node. Define thresholds in bit-times or frame-times, then add guard and confirmation windows so noise, clock drift, and node latency do not cause false wake or missed wake.

1
Required timing parameters (define all six)
tBREAK(min) Minimum LOW duration that must qualify as a BREAK wake preamble.
  • Define in: bit-times (preferred), not milliseconds, to keep behavior consistent across baud rates.
  • Risk if too short: noise spikes mimic BREAK; wake rate rises.
  • Risk if too long: slow wake; remote node may time out or violate its own preamble rules.
tIDLE(min) Quiet window needed to declare IDLE for sleep entry and/or idle interrupt.
  • Define in: N bit-times, 1 frame-time, or the IP’s idle counter unit (verify which).
  • Risk if too short: normal inter-frame gaps look like IDLE; sleep entry becomes unsafe.
  • Risk if too long: power saving is delayed; bus stays in higher-power mode unnecessarily.
Guard time Error margin for drift, remote latency, and detection uncertainty.
  • Covers: baud error, low-power RC clock drift, temperature drift, and remote-node scheduling jitter.
  • Placement: around boundaries (BREAK end, delimiter, confirm token window).
Debounce / filter Glitch rejection window for false edges and short spikes.
  • Goal: prevent ESD/EMI spikes from triggering edge-based wake or corrupting idle counters.
  • Trade-off: stronger filtering reduces false wake but increases wake latency and may distort short tokens.
Confirm window Post-wake time window to validate a known token/header-like pattern.
  • Why: BREAK/IDLE alone can be produced by faults; confirmation suppresses false Active entries.
  • Design rule: if no valid token arrives inside the window, return to sleep (bounded power cost).
Sleep entry Policy for when “no traffic” is sufficient to enter deep sleep.
  • Inputs: bus quiet time, pending TX, remote-node expectation, and a guard against inter-frame gaps.
  • Practical: require “quiet + stable idle level + no pending work” before entering sleep.
2
Typical starting points (placeholders)

Start with conservative values, then tune using measured false wake rate and wake latency. Use placeholders until the platform’s UART/IP definitions are confirmed.

  • tBREAK(min): X–Y bit-times (must exceed the IP’s break threshold with guard).
  • tIDLE(min): X–Y frame-times (must exceed worst-case inter-frame gap + jitter).
  • Guard time: X–Y bit-times (covers drift + remote scheduling + detection uncertainty).
  • Debounce/filter: X–Y microseconds (reject spikes shorter than the shortest valid token edge spacing).
  • Confirm window: X–Y milliseconds (must include “wake-to-ready” plus token arrival budget).
  • Sleep entry: X–Y milliseconds (no traffic + stable idle + no pending TX).
3
Inputs to extract (datasheet / IP / protocol)
UART/IP definitions
  • What qualifies as BREAK (threshold unit and minimum duration).
  • What qualifies as IDLE (counter unit; does any edge reset it).
  • Wake sources available in deep sleep (edge / start / break / idle / WUF).
  • Wake-to-clock-ready and wake-to-UART-ready timing (for confirm window sizing).
LIN-style minimal structure (wake-relevant only)
  • Presence of a BREAK-like preamble (dominant low).
  • Delimiter (short high) separating BREAK from the next token.
  • Sync/header-like token for confirmation (do not expand full protocol here).
Main error sources to budget
  • Clock drift (low-power RC oscillator, temperature, supply changes).
  • Baud error (local + remote combined).
  • Remote node latency (wake scheduling jitter and response time).
  • Noise/EMI bursts (glitch density and false edges).
Diagram: Wake preamble timing window (BREAK → delimiter → token, with MIN + GUARD + CONFIRM)
Wake sequence as a timing contract (platform + remote node) time → HIGH LOW BREAK DELIM TOKEN sync/header-like tBREAK(min) GUARD CONFIRM window Wake on BREAK/IDLE → enter Active only if TOKEN is observed inside CONFIRM (else return to sleep)

Low-Power Architecture Patterns (MCU Sleep Modes + UART Wake)

Choose an architecture based on power, wake latency, and false-wake tolerance. The key question is how much logic remains in an always-on island versus what stays in a gated domain.

Pattern A Stop/Standby + UART wake (keep RX path alive)
  • Use when: the MCU supports wake from UART events in deep sleep and the cable environment is moderate.
  • Pros: simplest integration, fastest wake.
  • Risks: edge-based wakes can be noisy; “wake ≠ ready” can drop the first payload byte.
  • Key parameters: wake source type (edge/start/break/idle), break/idle thresholds, wake-to-ready time.
Pass criteria (placeholders)
  • First valid byte capture rate ≥ X% after wake.
  • False wake events ≤ X per hour under worst-case EMI.
Pattern B External wake filter → then enable UART
  • Use when: ultra-low power, long cables, or high false-wake cost (battery, harsh EMC, hot-plug).
  • Pros: better false-wake immunity; always-on island can be minimal.
  • Risks: higher BOM/complexity; must handle UVLO, plug/unplug transients, and wake pin behavior.
  • Key parameters: external filter threshold, wake pin polarity/latch, wake-chain latency budget.
Pass criteria (placeholders)
  • False wake reduction ≥ X× versus Pattern A under injected noise.
  • Wake-chain latency ≤ X ms (measured to first valid token).
Pattern C Duty-cycled listening + IDLE policy
  • Use when: the platform has limited deep-sleep UART wake support, but can tolerate wake latency.
  • Pros: power is tunable via duty cycle; reduced dependence on always-on UART sampling.
  • Risks: longer worst-case latency; poor window design can miss wake or wake too often.
  • Key parameters: listen window, sleep window, idle threshold, and resync/confirm strategy.
Pass criteria (placeholders)
  • Worst-case wake latency ≤ X ms at the chosen duty cycle.
  • Missed-wake probability ≤ X under defined remote timing jitter.
Diagram: System wake architecture (always-on island vs gated domain)
Battery /PMIC Remote node Cable Transceiver (UART/LIN PHY) Always-on island Wake tap Filter /debounce Wake controller Gated domain (off in deep sleep) CPU + clocks UART driver + DMA/FIFO App Wake path Data path (after wake) Architecture goal: wake with minimal always-on logic, then enable full UART stack

LIN-Style Coordination: Sleep / Wake Handshake Without Collisions

A robust low-power bus uses a listen-first wake handshake: a wake preamble requests attention, a confirmation token proves intent, and only then normal traffic begins. This prevents multi-node collisions and avoids entering Active state on noise-only events.

Core
Minimum concepts (wake-relevant only)
  • Roles: Master coordinates bus order; Slave follows listen-first rules after wake.
  • Sleep entry: deep sleep is allowed only after a stable IDLE window meets the sleep criteria.
  • Wake request: a break-like wake signal (dominant LOW) requests attention.
  • Bus idle: collision-free traffic requires a measurable quiet window (no edges + stable level).
  • Confirm token: a short, fixed-format token/header-like pattern proves that wake is intentional.
Risks
The three collision drivers to control
  • Multi-node wake: more than one node detects wake and transmits immediately.
  • Ambiguous talker: after wake, nodes do not know who should speak first.
  • Unsafe first frame: the first frame arrives before clocks/UART stack are fully ready, causing mis-detect and re-collisions.
State machine
Wake token → confirm → normal traffic (three-stage handshake)
  1. SLEEP — Entry condition: stable IDLE meets sleep criteria (no pending TX, quiet window met).
    Trigger out: BREAK/WAKE request detected → Next: WAKE-DETECT
  2. WAKE-DETECT — Action: exit deep sleep, start clocks, enable RX path; do not transmit.
    Trigger: UART ready → Next: CONFIRM-LISTEN
  3. CONFIRM-LISTEN — Action: listen-first; accept only a fixed token/header-like pattern inside the confirm window.
    Success: TOKEN OK → Next: ACTIVE Timeout → BACK-TO-SLEEP
  4. ACTIVE — Normal traffic is allowed only after confirmation. Collision control remains: keep listen-before-talk where applicable.
    Return-to-sleep trigger: IDLE window + sleep entry criteria
  5. BACK-TO-SLEEP — Action: rollback to sleep when confirmation fails or bus order cannot be established.
    Exit: stable IDLE achieved → Next: SLEEP
Pass criteria (placeholders)
  • Collision-free entry to ACTIVE ≥ X% across worst-case multi-node wake tests.
  • Confirm timeout rollback always returns to SLEEP within X ms.
Safety
First-frame design rules (avoid “wake ≠ ready” failures)
  • Make it fixed: a short token/header-like pattern with a known length and stable spacing.
  • Make it confirmable: acceptance only inside the confirm window; reject out-of-window patterns.
  • Make it rollback-safe: failure to confirm must not enter ACTIVE; return to sleep deterministically.
  • Make it collision-resistant: enforce listen-first; a single designated talker sends the confirm token.
Diagram: Sleep ↔ Wake state machine (edges labeled by BREAK / IDLE / TOKEN / TIMEOUT)
LIN-style wake handshake (listen-first, confirm before active) SLEEP wake path only WAKE-DETECT clocks start CONFIRM listen-first ACTIVE normal traffic BACK-TO-SLEEP rollback BREAK UART ready TOKEN OK TIMEOUT IDLE + sleep criteria Normal path Rollback path

False Wake Immunity: Noise, Glitches, Common-Mode, Hot-Plug

False wake is a system-level failure mode: a non-intentional event triggers wake, consumes energy, and may enter Active state incorrectly. The design goal is to reject noise early, require confirmation, and rollback deterministically.

Source
False-wake sources (wake-relevant)
EMI/ESD glitches
Short spikes and bursts create false edges or corrupt idle counters.
Common-mode drift (long cable)
Slow threshold movement produces pseudo-edges or unstable idle levels.
Hot-plug / ground bounce
Plug/unplug transients and return-path changes trigger spurious wake events.
UVLO / slow ramp
RX input becomes undefined during brown-out or slow power-up.
Quick check
Fast isolation steps (what to observe first)
  • Point 1 — RX pin: capture spikes, edge density, and level stability around false wakes.
  • Point 2 — after filter: verify whether filtering removes the event before wake detect.
  • Point 3 — flags/logs: record the wake source (edge/break/idle/WUF) and confirm outcome.
  • Sanity rule: a wave that “looks like break” may not satisfy the IP’s break threshold; confirm by flags + measured duration.
Mitigation
Wake-focused countermeasures (layered)
1) Filter early
Apply hardware RC and/or digital debounce so short glitches cannot create wake edges or corrupt idle counters.
2) Require composite conditions
Accept wake only when multiple conditions align (BREAK + delimiter + token pattern), not on a single edge.
3) Confirm before Active
Enter ACTIVE only after a valid token is observed inside the confirmation window.
4) Roll back deterministically
If confirmation fails or the bus remains unstable, return to sleep with bounded time and energy.
Pass criteria (placeholders)
  • False wake events ≤ X per hour under defined injected noise and hot-plug tests.
  • Any false wake must exit Active/Confirm and return to sleep within X ms.
Diagram: False-wake path (risk sources → RX → detect → wake) with mitigation taps
False-wake immunity = filter early + composite trigger + confirm + rollback EMI / ESD Common-mode drift Hot-plug / bounce UVLO / slow ramp RX pin Filter /debounce Wake detect edge / break / idle Confirm token window Rollback to sleep Active enable CPU / UART stack Tap: FILTER Tap: COMPOSITE Tap: CONFIRM Tap: ROLLBACK Mitigation path Risk marker

Firmware Implementation Blueprint: ISR, Timeouts, and State Machines

A reliable wake system separates responsibilities into three layers: a minimal interrupt layer (L0) records wake candidates, a confirmation layer (L1) validates intent within bounded windows, and a coordination layer (L2) controls bus order (listen-first, backoff, and safe entry to Active).

L0
Interrupt layer (BREAK / IDLE / WUF)
  • Goal: convert asynchronous hardware flags into a minimal event record and return quickly.
  • Inputs: BREAK/IDLE/WUF flags, optional RX-edge indication, timestamp tick.
  • Outputs: event bits or queue items (EVT_BREAK, EVT_IDLE, EVT_WUF, EVT_RXBYTE).
  • Hard rules: no token parsing, no protocol actions, no long loops inside ISR.
L0 “good citizen” checklist
  • Record event type + timestamp + optional RX level snapshot.
  • Clear/ack flags using platform-required sequence (implementation-specific, kept out of this page).
  • Schedule the main wake state machine (deferred work) deterministically.
L1
Confirmation layer (window timing + token validity + debounce)
  • Goal: decide CONFIRMED vs REJECTED within bounded time and energy.
  • Debounce: short glitches may raise candidates, but cannot confirm wake.
  • Confirm window: accept only a fixed token/header-like pattern inside the window.
  • Rollback: if the window expires or token is invalid, return to SleepArming (do not enter Active).
Minimum “token validity” (protocol-agnostic)
  • Length: token fits in the RX buffer without crossing the wake-to-ready gap.
  • Structure: fixed spacing and predictable edges (avoid “random bytes” acceptance).
  • Timing: token must land inside confirm window (reject out-of-window patterns).
L2
Stack coordination (enter Active + allow TX + collision backoff)
  • Goal: enforce listen-first ordering and prevent simultaneous transmit after wake.
  • Allow-TX gate: TX is enabled only after confirmation + bus quiet + stack readiness.
  • Backoff: if bus is not quiet or collision is suspected, defer TX with bounded retry strategy.
  • Return-to-sleep: if traffic is absent and idle criteria are satisfied, arm sleep deterministically.
Key “gates” to log (debug-friendly)
  • Wake source: edge / BREAK / IDLE / WUF (what started the chain).
  • Confirm outcome: token OK vs timeout vs invalid pattern.
  • TX gate: allowed vs deferred (quiet/busy/backoff).
Timeouts
Required timeout set (bounded behavior)
wake_confirm_timeout
Maximum time allowed in CONFIRM state. Expiry triggers rollback to SleepArming.
bus_quiet_timeout
Maximum time waiting for a stable quiet window after wake. Expiry triggers backoff or rollback policy.
sleep_entry_timeout
Maximum time in SleepArming before re-evaluating conditions (prevents accidental sleep during normal gaps).
Pass criteria (placeholders)
  • Rollback after confirm failure must complete within X ms.
  • Wake-to-first-valid-byte worst-case latency ≤ X ms under defined conditions.
Data path
DMA/buffer strategy (avoid first-frame loss)
  • Early capture: keep a small RX ring buffer active or re-enabled immediately on wake; confirm tokens can be reconstructed from buffered bytes.
  • Window coverage: choose confirm window to cover clock start + UART ready + token arrival skew.
  • Depth rule: RX buffer depth must exceed the minimum confirm token size with margin.
  • Back-pressure hook: if burst traffic is expected after wake, ensure higher layers can defer TX until allow-TX gate opens.
Pseudocode
Minimum state machine skeleton (platform-agnostic)
enum Event { EVT_BREAK, EVT_IDLE, EVT_WUF, EVT_RXBYTE, EVT_TICK };
enum State { SLEEP, WAKE_DETECT, CONFIRM, ACTIVE, SLEEP_ARMING };

State st = SLEEP;
Timer T_confirm, T_quiet, T_sleep;

on_isr(flag_break, flag_idle, flag_wuf, rxbyte_opt):
  if flag_break: push_event(EVT_BREAK, now())
  if flag_idle:  push_event(EVT_IDLE,  now())
  if flag_wuf:   push_event(EVT_WUF,   now())
  if rxbyte_opt: push_event(EVT_RXBYTE, now(), rxbyte_opt)
  schedule_wake_fsm()

wake_fsm_step(event):
  switch (st):

    case SLEEP:
      if event in {EVT_BREAK, EVT_WUF}:
        st = WAKE_DETECT
        start_clocks_minimal()
        enable_rx_path()
      break

    case WAKE_DETECT:
      if uart_ready():
        st = CONFIRM
        T_confirm.start(wake_confirm_timeout)
        T_quiet.start(bus_quiet_timeout)
      break

    case CONFIRM:
      if event == EVT_RXBYTE:
        buffer_byte(event.byte)
      if token_valid_in_window() and bus_quiet_ok():
        st = ACTIVE
        allow_tx(false)          // listen-first gate
      if T_confirm.expired():
        st = SLEEP_ARMING        // rollback
      break

    case ACTIVE:
      if allow_tx_conditions_met():
        allow_tx(true)
      if idle_window_met() and no_pending_work():
        st = SLEEP_ARMING
        T_sleep.start(sleep_entry_timeout)
      break

    case SLEEP_ARMING:
      if traffic_resumes():
        st = ACTIVE
      else if sleep_conditions_met() and T_sleep.expired():
        prepare_sleep()
        st = SLEEP
      break
Notes: token_valid_in_window() should validate a minimal fixed pattern (length + structure + timing). allow_tx_conditions_met() should enforce listen-first and bus-quiet requirements to avoid collisions.
Diagram: Firmware state machine with timeout wheels (Confirm / Quiet / Sleep-entry)
Firmware blueprint = L0 events → L1 confirm → L2 coordination (bounded by timeouts) SLEEP wake-only WAKE-DETECT clocks up CONFIRM token window ACTIVE allow-TX gate SLEEP-ARMING idle criteria BREAK/WUF UART ready TOKEN OK CONFIRM TO IDLE met T_confirm wake_confirm_timeout T_quiet bus_quiet_timeout T_sleep sleep_entry_timeout

Power & Latency Budget: What to Measure and How to Close the Loop

Low-power performance should be closed by measurable KPIs: sleep current, wake latency to the first valid byte, and false-wake rate. Each tuning knob must be linked to what it improves and what it costs.

KPI
I_sleep (Sleep current)
  • Definition: steady-state current after entering SLEEP (exclude wake transients).
  • Log: supply rail, temperature, and whether duty-cycled listening is used.
  • Target: ≤ X µA (placeholder).
KPI
Wake latency (t_wake → first valid byte)
  • Definition: from wake trigger edge/BREAK/WUF to confirmed first valid byte consumable by upper layers.
  • Decompose: clock start + UART ready + confirm parsing.
  • Target: worst-case ≤ X ms (placeholder).
KPI
False wake rate (per hour/day)
  • Count levels: false_detect, false_confirm_fail, false_active (most severe).
  • Log: wake source (BREAK/IDLE/edge/WUF) and outcome.
  • Target: false_active ≤ X / day (placeholder).
Test
Measurement conditions (repeatable closure)
Cable length / loading
Short/medium/long line (X/Y/Z) and realistic connector/grounding setups.
Noise injection / transients
Injected glitch/burst patterns and hot-plug events; log wake source and confirm outcome.
Temperature & supply corners
Low/room/high temperature; brown-out and slow-ramp profiles; verify stable sleep and no spurious active entry.
Knobs
Tuning knobs and primary effects
  • Filter/debounce window ↑ → false wake ↓, but wake latency ↑.
  • Confirm window ↑ → false_active ↓, but wake energy ↑ (clocks stay on longer).
  • tBREAK(min) ↑ → noise immunity ↑, but short wake requests may be missed.
  • tIDLE(min) ↑ → stable sleep entry ↑, but sleep entry delay ↑.
  • bus_quiet_timeout ↑ → collision resilience ↑, but worst-case time-to-traffic ↑.
  • Backoff range ↑ → multi-node convergence ↑, but worst-case latency ↑.
  • RX buffer depth / early DMA ↑ → first-frame loss ↓, but memory/always-on cost ↑.
Pass criteria (placeholders)
  • After tuning, false_active ≤ X / day while t_wake ≤ X ms.
  • I_sleep meets target with the same confirm logic enabled (no “test-only” configuration).
Diagram: Filter window trade-off (false wake ↓ vs latency ↑) + energy impact
Trade-off closure: FILTER window ↑ → false wake ↓, but latency/energy ↑ FILTER WINDOW LOW → HIGH FALSE WAKE RATE per hour/day ↓ decreases WAKE LATENCY t_wake → first valid byte ↑ increases ENERGY PER WAKE: confirm window ↑ → clocks-on time ↑ → energy ↑ Over-filter risk

Debug & Validation: Scope/LA Triggers, Test Vectors, Production Hooks

Validation should be repeatable: correlate line reality (RX waveform) with wake flags (BREAK/IDLE/WUF), confirm-window behavior, and first-valid-byte reliability. The same evidence must be usable for bring-up and production.

Lab
Bring-up instrumentation and triggers
  • Capture points: RX line + wake/domain-enable (if available) + UART flags/bytes (decoded or buffered).
  • Trigger A (recommended): break low width ≥ tBREAK(min)=X to anchor wake-start timing.
  • Trigger B: idle high gap ≥ tIDLE(min)=X followed by an edge (idle→activity transition).
  • Synchronous proof: confirm whether wake occurs before UART is fully ready (wake≠ready) and whether confirm token lands inside the window.
Bring-up “must-prove” outcomes
  • Flag correlation: line-level break/idle features match BREAK/IDLE/WUF flags ≥ X%.
  • Confirm closure: token-in-window success ≥ X% under defined conditions.
  • First-valid-byte: wake-to-first-valid-byte ≤ X ms; loss rate ≤ X.
Production
Manufacturing hooks and repeatable vectors
  • Loopback hook: a minimal internal or fixture-assisted loopback that can exercise wake→confirm→rollback paths.
  • Counters: wake_count, false_wake_count, active_entry_count (optional: confirm_timeout_count, quiet_fail_count).
  • Event log (minimum fields): timestamp, wake_source (BREAK/IDLE/WUF/edge), state_path, first_valid_byte_time, supply corner (optional).
  • Vector pass rule: every test vector must produce an expected counter delta (no “silent pass”).
Minimal production vector set
  • Wake path: break (or edge/WUF) triggers wake_count +1.
  • Confirm path: valid token inside window → active_entry_count +1.
  • Rollback path: invalid token or forced timeout → false_wake_count +1, no Active entry.
Diagram: Test vector matrix (vector icon + expected flag + expected outcome)
Vectors must map to: waveform → expected flag → expected state (ACTIVE/ROLLBACK) NORMAL FLAG: NONE ACTIVE BREAK-only LOW FLAG: BREAK CONFIRM IDLE-only HIGH FLAG: IDLE LISTEN NOISE FLAG: NONE ROLLBACK Expected: no Active entry UVLO FLAG: WUF SAFE Expected: gate wake under low VDD HOT-PLUG FLAG: NONE ROLLBACK Expected: confirm must fail

Engineering Checklist (Design → Bring-up → Production)

Gate-based readiness prevents field surprises. Each gate is scoped to break/idle wake: thresholds and windows (Design), correlation and first-byte reliability (Bring-up), and measurable false-wake limits with traceable logs (Production).

Design gate
Spec completeness and bounded behavior
  • tBREAK(min) defined with guard margin. Pass: X
  • tIDLE(min) defined with sleep entry criteria. Pass: X
  • Debounce/filter window defined and justified by noise model. Pass: X
  • Confirm window covers wake-to-ready budget. Pass: X
  • Minimum token validity rule defined (length/structure/timing). Pass: X
  • Rollback policy defined (confirm timeout → SleepArming). Pass: X
  • Listen-first and allow-TX gate defined (no wake-and-talk collision). Pass: X
  • False-wake KPI definition includes detect/confirm_fail/active levels. Pass: X
  • Counters/log fields defined for traceability. Pass: X
Bring-up gate
Correlation, confirm closure, first-byte reliability
  • Measured break low width matches spec and triggers the expected flag. Pass: X
  • Measured idle gap matches spec and triggers the expected idle indication. Pass: X
  • Flag correlation (waveform ↔ flag) ≥ X%. Pass: X
  • Token-in-window success ≥ X%. Pass: X
  • Confirm timeout always rolls back (no silent Active entry). Pass: X
  • Wake-to-first-valid-byte worst-case ≤ X ms. Pass: X
  • First-byte loss rate ≤ X (or ≤ X%). Pass: X
  • Noise/hot-plug vectors do not enter Active; confirm fails as expected. Pass: X
Production gate
KPI thresholds, counters, and traceable rollback
  • false_active ≤ X / day (or X / 24h soak). Pass: X
  • Production vectors produce expected counter deltas (error = 0). Pass: X
  • Event log fields (timestamp/source/outcome/latency) are present for every wake attempt. Pass: X
  • Confirm failures always produce a log entry (no silent rollback). Pass: X
  • Loopback/self-test covers wake→confirm→rollback paths. Pass: X
  • Active dwell under abnormal conditions remains bounded (≤ X). Pass: X
Diagram: Gate flow (Design → Bring-up → Production) with pass thresholds
Gate flow locks readiness: thresholds → correlation → measurable production limits DESIGN thresholds state machine confirm token PASS X BRING-UP flag correlation first valid byte rollback proof PASS X PRODUCTION false-active KPI counters logs PASS X Rule: every gate has measurable pass criteria (X) and traceable evidence (flags, counters, logs)

Applications (Strictly Within This Page)

Application guidance here is limited to break/idle wake behavior: who wakes whom, how wake is confirmed, and how collisions and false wakes are prevented under real cabling and noise conditions.

Scenario A
Battery device: remote UART wake of a sleeping controller
  • Goal: allow a remote node to wake the MCU from STOP/Standby, then deliver a short “first token” without losing the first valid byte.
  • Constraints: wake≠ready (clock start-up), limited always-on power, risk of spurious edges on long harnesses.
  • Recommended wake recipe: BREAK → confirm token within window → enter Active; confirm failure rolls back to sleep.
  • Key knobs: tBREAK(min)=X, confirm_window=X, debounce/filter=X, wake-to-ready budget=X.
  • Example material numbers (evaluate): MCU: STM32L476RG, SAMD21G18A, SAML21J18B, RA2L1 (series) · Level/PHY: MAX3232E, TRS3232E · ESD (low-C examples): TPD2E001, PESD5V0S1BA
Pass criteria (X placeholders)
False Active ≤ X/day · wake-to-first-valid-byte ≤ X ms · token-in-window success ≥ X%
Scenario B
Automotive/industrial: LIN-style sleep → wake request → confirm
  • Goal: predictable multi-node wake with minimal collisions; wake confirmation must be explicit before allowing normal traffic.
  • Constraints: multiple nodes share the bus; noise bursts and hot-plug events are common; wake must not trigger uncontrolled transmissions.
  • Recommended wake recipe: listen-first after wake detect; only one role (typically master) sends a confirm token/header; nodes remain silent until confirmed.
  • Key knobs: bus_quiet_timeout=X, confirm_window=X, backoff range=X, allow-TX gate defined.
  • Example material numbers (evaluate): LIN transceiver: TLIN1029-Q1, TJA1029, MCP2003B · MCU examples: S32K116, STM32G0B1, LPC5528
Pass criteria (X placeholders)
Collision-free wake convergence ≥ X% · false wake ≤ X/day · confirm timeout always rolls back (100%)
Scenario C
Long cable / noisy environment: idle-only is fragile
  • Goal: prevent spurious wake due to EMI/ESD bursts, common-mode shifts, and hot-plug transients.
  • Constraints: idle-gap counters can be disrupted by noise; edge-only wake may be too sensitive.
  • Recommended wake recipe: avoid idle-only; require BREAK + pattern (delimiter + token) for confirmation; strict rollback on confirm failure.
  • Key knobs: filter window=X, guard=X, confirm window=X, “composite trigger” rule defined.
  • Example material numbers (evaluate): ESD (low-C): TPD2E001, PESD5V0S1BA, RClamp0524P · Series-R (0402 examples): ERJ-2RKF33R0X, CRCW040233R0FKED · Decoupling (X7R examples): GRM155R71C104KA88
Pass criteria (X placeholders)
No Active entry under noise vectors · confirm-fail rollback = 100% · false wake ≤ X/24h soak
Scenario D
Multi-node sharing: avoid simultaneous talkers
  • Goal: ensure wake recovery converges even if multiple nodes wake at once.
  • Constraints: collisions and “wake storms” increase energy and delay; uncontrolled first transmission is the top risk.
  • Recommended wake recipe: listen-first + allow-TX gate; single initiator confirm token; if multi-initiator is possible, use priority + bounded backoff.
  • Key knobs: bus_quiet_timeout=X, backoff=X, allow-TX conditions, retry limit=X.
  • Example material numbers (evaluate): RS-485 transceiver examples: THVD1550, ADM3065E, MAX13487E · Isolation (if required): ISO3082, ADM2587E
Pass criteria (X placeholders)
Convergence to single talker ≤ X ms · collision retries ≤ X · false-active remains ≤ X/day
Diagram: Wake topology (who wakes whom) with confirm direction and collision risk
MASTER / CONTROLLER MCU (sleep) UART RX wake Confirm token listen-first gate CABLE / BUS NODE A Transceiver + filter NODE B UART TX/RX NODE C Wake request source WAKE REQ (BREAK) CONFIRM TOKEN COLLISION RISK WAKE REQ CONFIRM TOKEN RISK

IC Selection Notes (MCU/UART + Transceiver Wake Features)

Selection is narrowed to wake-critical capabilities only: wake source availability in low-power modes, local filtering and fail-safe behavior on the line interface, and measurability (counters/logs) to control false wakes.

Must-have
Wake must work in the intended sleep state
  • MCU/UART: verify wake from STOP/Standby via RX event (edge/start/break as supported), and verify whether break/idle detect exists and is usable for wake confirmation.
  • Low-power clocking: verify whether wake detection runs in an always-on domain or requires high-speed clocks.
  • Data-path safety: verify that the first confirm token can be captured (buffer/DMA or a long enough confirm window).
  • Line interface: choose a transceiver whose default/fail-safe behavior does not create random RX toggles during sleep, UVLO, or slow ramp.
Concrete material numbers (starting points to evaluate)
MCU examples: STM32L476RG, STM32L072CZ, LPC5528JBD100, SAMD21G18A, SAML21J18B, MSP430FR2355, S32K116
Nice-to-have
Local wake filter + explicit wake pin
  • Wake pin: a separate wake output simplifies Mode B (external pre-wake → enable UART after clocks stabilize).
  • Local filtering: transceiver-level filtering can suppress glitches before they reach the MCU wake tap.
  • Fail-safe / idle bias: stable default line state reduces idle/edge ambiguity in noisy environments.
  • Isolation (if required): ensure the isolated interface does not introduce unpredictable wake toggles during power sequencing.
Concrete material numbers (evaluate and verify)
LIN: TLIN1029-Q1, TJA1029, MCP2003B
RS-485: THVD1550, ADM3065E, MAX13487E
RS-232: MAX3232E, TRS3232E
Isolation: ISO3082, ADM2587E
Pitfalls
Common “wake-only” traps to screen out
  • Wake exists but confirmation is missing: edge-only wake without composite confirm tends to false-wake under EMI.
  • Idle detect not valid in deep sleep: idle counters may stop when clocks are gated; screen for real sleep-state behavior.
  • UVLO / slow ramp ambiguity: floating or drifting RX input during low VDD can create spurious wake events; require gating or fail-safe behavior.
  • Hot-plug / ghost-powering: unintended back-powering can toggle RX or wake pins; verify sequencing and clamp paths.
  • Protection capacitance side effects: ESD arrays or RC networks can distort thresholds/edges; validate false-wake KPI after protection is populated.
Protection examples (wake-sensitive; verify impact)
ESD: TPD2E001, PESD5V0S1BA, RClamp0524P · Series-R: ERJ-2RKF33R0X, CRCW040233R0FKED (detailed protection tradeoffs belong in the Port Protection page; keep this page wake-focused)
Diagram: Wake-focused selection tree (inputs → mode A/B/C)
Inputs → decisions → recommended architecture (Mode A / Mode B / Mode C) Sleep current target I_sleep goal Cable environment length / noise False wake tolerance events/day Need lowest I_sleep? Noisy / long cable? Multi- node share? MODE A Stop/Standby + UART wake RX always-on path MODE B Transceiver pre-wake wake pin + local filter MODE C Duty-cycled listen idle/break confirm window YES YES YES
Practical note
The listed material numbers are example starting points. For each candidate, confirm in the datasheet: (1) which wake source works in the intended sleep mode, (2) whether break/idle detect is available for confirmation, (3) default line state and UVLO behavior, and (4) false-wake performance after protection components are populated.

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FAQs

These FAQs close out long-tail bring-up and production issues strictly within break/idle wake behavior. Each answer is a measurable loop: diagnose → check → fix → pass/fail.

Break is detected, but the MCU does not wake — is the wake source not in the low-power domain?
Likely cause: wake event is not routed as a wake-up source in STOP/Standby; wake logic is clock-gated; interrupt flag sets but does not trigger power-state exit.
Quick check: log BREAK/WUF flag transitions during sleep; scope the “wake pin / domain enable / VDD rail” versus RX activity; confirm the wake source works in the exact sleep mode.
Fix: enable the correct wake source in the power controller; move wake tap to an always-on path (Mode A) or use an external pre-wake pin/filter (Mode B); require confirm token after clocks stabilize.
Pass criteria: wake success ≥ X% across VDD min/max and temperature; wake-to-domain-enable ≤ X ms; no “flag-only” events without wake (0 occurrences / X trials).
Idle interrupt keeps firing — is RX drifting, biased wrong, or unstable under undervoltage?
Likely cause: RX input is floating or biased incorrectly in sleep; idle counter is too short; UVLO/slow ramp causes threshold chatter that produces “fake idle” classification.
Quick check: scope RX DC level and edge activity during sleep; record idle IRQ rate in a quiet cable state; compare idle_count programming vs real bit-time.
Fix: enforce a defined line state (fail-safe bias / pull configuration) during sleep; increase tIDLE(min) and add debounce; gate idle-detect until VDD is stable and a confirm token is required.
Pass criteria: idle IRQ rate ≤ X/hour on a quiet line; false Active entries = 0 over X hours; idle detect correlation ≥ X% with measured idle gaps.
Too many false wakes in a noisy environment — add filtering first, or add a confirm token first?
Likely cause: wake relies on edge-only or idle-only triggers; debounce is too short; no composite confirmation exists to reject noise/glitches.
Quick check: inject a known glitch/noise vector and count false_wake_count and active_entry_count; scope glitch width versus filter window.
Fix: implement composite confirmation: BREAK → delimiter → token within confirm window; then tune filter/debounce only as needed to meet latency; enforce rollback on confirm timeout.
Pass criteria: false Active ≤ X/day; confirm-timeout rollback = 100%; no Active entry under noise vectors in X trials.
First frame loses bytes after wake — clocks/sampling not ready, or FIFO/DMA is too shallow?
Likely cause: wake-to-ready latency is longer than the remote’s first-byte timing; RX starts sampling before clocks settle; RX buffer overrun occurs during wake transition.
Quick check: measure t_wake→first_valid_byte and compare to confirm window; check overrun/framing counters; capture RX and domain-enable on the same trigger.
Fix: extend confirm window and enforce a guard time before token; enable DMA/ring buffer early; require remote retry (token repeated) until confirmation is acknowledged.
Pass criteria: first valid byte capture ≥ X% at worst-case wake latency; overrun count = 0 over X wake cycles; t_wake→first_valid_byte ≤ X ms.
Remote sends break; receiver sometimes logs framing error but does not flag break — how to validate the break-length threshold?
Likely cause: break low width is below the IP’s break-detect threshold; baud/bit-time mismatch shifts the effective width; oversampling and stop-bit expectations differ.
Quick check: scope RX low width in bit-times; compare to the IP’s documented break criteria; test at a slower baud to see if break detection becomes consistent.
Fix: increase break duration to ≥ (X + margin) bit-times; ensure delimiter/high gap exists; align oversampling/baud tolerance and confirm with a token window.
Pass criteria: break-flag correlation with measured width ≥ X%; no “framing-only” events when width ≥ threshold (0 / X trials).
Multiple nodes wake and talk at the same time — what is the minimum backoff/arbitration strategy?
Likely cause: no listen-first gate after wake; multiple initiators are allowed to transmit immediately; no bounded random backoff exists.
Quick check: logic-analyzer trace shows overlapping start bits within X ms after wake; collision retries spike; confirm token appears from multiple sources.
Fix: define allow-TX gate: only master (or one elected role) sends confirm token; other nodes stay silent until confirmed; add bounded random backoff [0..X] and retry limit X.
Pass criteria: convergence to single talker ≤ X ms; collision retries ≤ X per wake; no bus-storm beyond X events/day.
False wake rate changes at low/high temperature — check threshold drift first, or common-mode behavior first?
Likely cause: RX bias/threshold margin changes with temperature; pull components and transceiver fail-safe shift; cable common-mode noise susceptibility changes.
Quick check: log false Active per hour versus temperature; scope RX idle level and edge density at hot/cold; compare VDD ripple/UVLO events to wake counters.
Fix: increase noise margin (stronger bias, better fail-safe, or Mode B pre-wake filter); tune debounce/confirm window for worst case; require composite confirm token, not edge-only.
Pass criteria: false Active ≤ X/day across the specified temperature range; confirm-fail rollback = 100%; no missed true wakes ≥ X% success at hot/cold.
Plugging/unplugging the cable wakes the system — ESD/ground bounce or ghost powering?
Likely cause: hot-plug transients create RX edges; ground bounce couples into the wake tap; back-power paths temporarily bias RX/wake pins (ghost powering).
Quick check: scope RX and VDD during plug events; correlate wake events with VDD ramp/UVLO flags; check whether wake happens before clocks are stable.
Fix: gate wake during the first X ms after plug detection; require confirm token before Active; add series-R/RC only if validated not to worsen thresholds; eliminate back-power paths with proper sequencing/clamps.
Pass criteria: no Active entry on plug/unplug without valid confirm token (0 / X events); false Active per plug ≤ X; recovery to sleep current ≤ X ms.
Idle-only wake is unstable — how to migrate to break + pattern composite confirmation?
Likely cause: idle counters are disrupted by noise edges; line biasing is not stable; idle gaps vary with traffic patterns and timing drift.
Quick check: compare idle IRQ count to actual measured idle gaps; verify whether idle-only triggers occur during normal inter-frame spacing.
Fix: require BREAK as the wake preamble, then a delimiter + token inside confirm window; treat idle-only as “arming” (sleep-entry) rather than “wake”.
Pass criteria: token-in-window success ≥ X%; false Active ≤ X/day; idle-only no longer triggers Active (0 / X hours).
LIN-style wake causes bus chaos — is the wake header/confirm design wrong?
Likely cause: nodes transmit immediately after wake; confirm token is not centralized; bus quiet time is not enforced; multiple initiators create collisions.
Quick check: logic-analyzer timeline after wake: identify who transmits first and whether multiple start bits overlap; check bus_quiet_timeout violations.
Fix: enforce listen-first; only master sends confirm header/token; slaves remain silent until confirmed; apply bounded backoff and retry limit on any initiator role.
Pass criteria: wake handshake success ≥ X%; collisions ≤ X per X wakes; confirm-timeout rollback = 100%.
Sleep entry is too aggressive and normal gaps are treated as a wake preamble — how to set sleep criteria?
Likely cause: sleep_entry_timeout is shorter than real inter-frame gaps; no hysteresis exists; idle detection is used as a wake trigger rather than a sleep-arming condition.
Quick check: log “last RX activity time” and compare to sleep_entry_timeout; check if sleep occurs during bursty traffic; count idle IRQs during normal traffic patterns.
Fix: increase sleep_entry_timeout to ≥ X frame-times; require N consecutive quiet windows; add hysteresis and block sleep while pending TX/ACK exists.
Pass criteria: no unintended sleep entry during normal traffic (0 / X minutes of scripted traffic); sleep current meets target within X ms after true idle; wake success remains ≥ X%.
wake_count is high but users feel nothing — how to define false-wake pass criteria and metrics?
Likely cause: wake_count counts detect-level events, not confirmed Active entries; confirm-fail rollbacks inflate wake statistics; pass criteria is missing or uses the wrong denominator.
Quick check: split counters: wake_detect_count, active_entry_count, confirm_fail_count; compute ratios over X hours.
Fix: redefine “wake” as confirmed Active entry; track detect-only and confirm-fail separately; set a false-wake KPI in events/day and enforce rollback on confirm timeout.
Pass criteria: false Active ≤ X/day; (active_entry_count / wake_detect_count) ≥ X% for real events; confirm_fail_count is bounded ≤ X/day.
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