Level Translation for Multi-Voltage IO (1.2–5 V)
← Back to: I²C / SPI / UART — Serial Peripheral Buses
Level Translation means letting digital IO cross voltage domains safely and predictably—without breaking open-drain behavior, causing contention, or back-powering in mixed power states.
The goal is to choose the right translator family (direct connect, open-drain pass, auto-direction, or DIR/OE control) and verify it with measurable margins: thresholds, rise-time, injection current, and glitch/overshoot limits.
What “Level Translation” Really Means
Intent: lock the scope (digital IO levels only)
Level translation ensures digital IO signals remain valid when two voltage domains differ (for example, 1.2 V ↔ 5 V). It is not about changing the protocol. It is about meeting thresholds, preserving signal semantics (open-drain / tri-state), and preventing power-state hazards such as back-powering.
Core objects this page cares about
- Voltage domains: VDD_A / VDD_B differ; inputs/outputs must still satisfy logic thresholds.
- Thresholds & leakage: VIH/VIL, VOH/VOL, input leakage (IIN), and clamping paths.
- Semantics: push-pull vs open-drain (wired-AND) vs tri-state release behavior.
Not included (avoid scope creep)
- Protocol conversion (I²C/SPI/UART framing, addressing, timing rules) — keep those in the bus-specific pages.
- PHY/transceivers (RS-232/RS-485/CAN) — that belongs to the “Voltage Levels & PHY” page.
- Isolation and ESD/surge protection — treated as separate system topics; this page only references their interface constraints.
Three questions that decide the correct translator family
- Direction: unidirectional, bidirectional, or tri-state release required?
- Driver type: push-pull or open-drain (wired-AND must be preserved)?
- Speed & load: edge rate, trace/cable length, and total capacitance (Cin + wiring + connectors)?
Design hook
Treat level translation as a spec: define domains, power states (powered/unpowered), and required semantics (open-drain/tri-state) before picking parts.
Pass criteria
The chosen approach must satisfy VIH/VIL and ABS MAX, preserve open-drain/tri-state behavior, and show no back-powering across all power sequences.
First Gate: Can It Connect Directly?
Intent: avoid unnecessary translators with a worst-case check
A translator should not be the default. Direct connection is often the most reliable solution if (and only if) thresholds, absolute maximum ratings, and power-state safety all pass. Use this section as a deterministic gate before selecting parts.
Direct-connect gate (worst-case rules)
Rule 1 — DC thresholds must have margin
- High-level margin: VOH(min, driver) ≥ VIH(min, receiver) + ΔV
- Low-level margin: VOL(max, driver) ≤ VIL(max, receiver) − ΔV
ΔV accounts for noise, ground bounce, temperature drift, and supply tolerance.
Rule 2 — Absolute maximum ratings must not be violated
- If VIN can exceed the receiver’s VDD, confirm the pin explicitly supports over-voltage tolerant operation.
- Check any clamp/ESD structures that may conduct into VDD or GND during transients.
Rule 3 — Powered/unpowered states must be safe (no back-powering)
- If one domain can be off while the other drives HIGH, the receiver must specify Ioff / partial power-down behavior.
- “5 V tolerant” is not sufficient unless the datasheet covers the unpowered condition.
Rule 4 — AC behavior must be credible at the required speed/load
If the signal sees long traces/cables, large Cin, or fast edges, a “DC-pass” direct connection may still fail. When this is suspected, treat it as a signal-integrity problem and move to the speed/load analysis later in the page.
Worked example: 1.8 V driver → 3.3 V receiver
- Collect worst-case datasheet values: VOH(min), VOL(max) (driver), and VIH(min), VIL(max) (receiver), across temperature and supply tolerance.
- Compute margins: ΔV_H = VOH(min) − VIH(min) and ΔV_L = VIL(max) − VOL(max).
- Decide: direct-connect passes only if ΔV_H ≥ ΔV and ΔV_L ≥ ΔV, and ABS MAX + powered/unpowered safety also pass.
If the thresholds pass but power-state safety fails (back-powering risk), direct connection is not acceptable without additional gating (OE/series-R) or a suitable translator.
Common direct-connect pitfalls to eliminate early
- Thresholds look OK at typical, but fail at worst-case (cold corner + low VDD).
- “5 V tolerant” misread: unpowered condition not guaranteed, causing clamp conduction into VDD.
- Edge-related failures: direct wiring passes DC checks but shows ringing/undershoot at the receiver pin.
Pass criteria (make it measurable)
- DC: ΔV_H and ΔV_L exceed the chosen margin ΔV across all corners.
- ABS MAX: receiver pin voltage stays within allowed range during normal operation and expected transients.
- Power states: with either side unpowered, input injection current stays below X mA (set X per datasheet/system policy).
Translator Taxonomy: Pick the Right Family
Intent: build a decision tree, then deep-dive later
Translator selection becomes deterministic when it starts from three inputs: direction, driver type (push-pull vs open-drain), and speed/load (edge rate, capacitance, and wiring length). This section maps those inputs to a small set of reliable translator families.
Selection inputs (answer these before reading datasheets)
- Direction: unidirectional, bidirectional, or tri-state release required?
- Driver type: push-pull or open-drain (wired-AND must be preserved)?
- Speed & load: DC/slow or high-speed; light load or large Cin/long wiring/strong pull-ups?
Translator families (what each family is best at)
Unidirectional buffer
Most robust
- Use when: direction is known (SPI MOSI/SCLK/CS, UART TX/RX).
- Strength: deterministic timing, predictable drive, easiest to validate.
- Watch: output enable defaults, partial power-down / Ioff behavior.
Bidirectional open-drain
I²C / wired-AND
- Use when: the bus is open-drain and must preserve wired-AND behavior.
- Strength: preserves LOW dominance; HIGH comes from pull-ups.
- Watch: pull-up placement/strength, rise-time budget, low-V domain pull-down margin.
Auto-direction
Use with caveats
- Use when: contention is unlikely and edge behavior stays within the device’s detection window.
- Strength: minimal control pins; convenient for simple bidirectional IO.
- Avoid when: push-pull on both ends, strong pull-ups, or high-speed/large Cin wiring.
DIR / OE controlled
Deterministic
- Use when: high speed, large load, strict timing, or hot-plug/power sequencing needs gating.
- Strength: safest control over direction and tri-state behavior.
- Watch: switch safely (OE off → change DIR → OE on), obey tDIS/tEN.
Practical rules (fast decisions)
- Prefer unidirectional parts whenever direction is known; it reduces ambiguity and failure modes.
- For wired-AND buses, choose a family that preserves open-drain; do not “upgrade” it into push-pull behavior.
- If speed/load/power sequencing is harsh, DIR/OE-controlled beats auto-direction for determinism and validation.
Open-Drain Preservation for I²C and Wired-AND Signals
Intent: keep wired-AND semantics intact across voltage domains
Open-drain buses depend on a strict rule: LOW must always dominate, and HIGH must be produced by pull-ups (not by a push-pull driver). Preserving this behavior across domains is mandatory for arbitration, ACK/NAK signaling, and any wired-AND logic.
What must remain true (behavior constraints)
- LOW dominance: any device can pull the line LOW, and that LOW is seen on all segments.
- HIGH by pull-up: when all devices release the line, the line returns HIGH via pull-up resistors.
- No forced HIGH: translators must not source a push-pull HIGH that breaks wired-AND behavior.
Pull-up placement (where the HIGH level comes from)
Rule
Each voltage domain should have its own pull-up to its local VDD, so the bus HIGH level is valid on both sides without forcing current through clamp paths.
Segmented buses
When the bus is segmented (buffers/switches/long wiring), treat each segment as a separate RC rise-time budget. One pull-up cannot “guarantee” timing across all segments.
Classic bidirectional open-drain pass element (what matters in practice)
- LOW transfers through conduction: pulling LOW on either side makes the pass element conduct and propagates LOW to the other side.
- HIGH is not “driven” through: both sides rise HIGH via their pull-ups; the pass element mainly ensures LOW dominance, not a pushed HIGH level.
- Boundary condition: very low VDD on one side (e.g., 1.2 V) plus strong pull-ups/large loads on the other side can reduce LOW margin. Validate LOW level at the far side, not only at the driver pin.
Rise-time budgeting (RC method that stays valid across designs)
- Estimate total bus capacitance CBUS per segment: device Cin + trace + connector/cable + probe effects.
- Choose a target rise-time tR,target (per system timing margin policy). Then set an initial pull-up using a conservative RC approximation: RP ≤ tR,target / (k · CBUS) where k is an engineering constant dependent on the rise-time definition and waveform shape.
- Check LOW-level current: pull-up current must be within the sink capability and thermal policy, otherwise increase RP or segment the bus (do not compensate by forcing a push-pull HIGH).
Practical consequence: RP too large → slow rise and timing loss; RP too small → power loss and more ringing/EMI risk.
Common failure modes (symptom → first check)
- Fast pull-ups + edge acceleration: overshoot/ringing and false transitions. First check: waveform at the farthest node (not near the master).
- Low-V domain cannot hold LOW: remote side sees a “shallow LOW”. First check: LOW voltage on the opposite side under worst sink current.
- Pull-ups placed on only one side: the other side rises slowly or floats. First check: confirm each domain has a defined pull-up strategy.
- Mode/edge limits: some implementations do not tolerate very high-speed modes. First check: measure rise-time margin vs system target on the worst segment.
Pass criteria (measurable acceptance targets)
- LOW propagation: pulling LOW on either side forces the other side below X·VDD_low (choose X per noise policy).
- Rise time: each segment meets tR ≤ X ns under worst-case capacitance and temperature.
- Static current: pull-up current at LOW stays within sink capability and system power budget (≤ X mA).
Auto-Direction Translators: How They Work and Why They Fail
Intent: answer “Is auto-direction reliable?”
Auto-direction devices do not “know” direction; they infer it from edges, voltages, or short internal timing windows. Reliability depends on whether real bus behavior stays inside those assumptions: edge shape, pull-up strength, tri-state behavior, and the possibility of simultaneous driving.
Common detection mechanisms (what “auto” usually means)
Edge + one-shot
Timing window
A detected edge triggers a short drive/assist pulse; direction is assumed for that window. If the edge is too slow/too fast, the window can misalign.
Weak drive + sense
Bias behavior
The device biases lines weakly and uses internal sensing to decide which side is driving. Strong pull-ups or heavy loading can distort the inference.
Comparator-based
Thresholds
Internal comparators sample voltage or slope and latch direction. Noise, slow transitions, and intermediate/Hi-Z states can cross thresholds and flip direction.
Typical failure modes (trigger → symptom → first check)
1) Push-pull contention
- Trigger: both ends actively drive (or can overlap during switching).
- Symptom: current spikes, heating, “flattened” edges, sporadic bit errors.
- First check: capture the overlap window; look for plateaus and supply current surges.
2) Pull-up too strong
- Trigger: strong pull-ups force the line quickly and bias direction detection.
- Symptom: double-steps, brief reverse drive, “mystery” glitches on transitions.
- First check: relax pull-ups or remove edge acceleration and re-test stability.
3) Edge too slow / too fast
- Trigger: RC slow edges or very fast edges miss the internal timing window.
- Symptom: works on short traces; fails on long wiring or heavy Cin; temperature sensitivity.
- First check: compare rise/fall times at the farthest node against the device’s assumptions.
4) Tri-state / intermediate states
- Trigger: Hi-Z release or mid-level transitions (e.g., MISO release) cross thresholds.
- Symptom: narrow pulses, direction flips, next edge causes contention.
- First check: zoom into release windows; verify no threshold crossings during Hi-Z.
When to stop “guessing direction” and use DIR/OE control
- Strict timing: narrow sampling windows or intolerance to glitches.
- Large load: big Cin, long traces/cables, connectors, or heavy pull-ups.
- High speed: fast edges or tens of MHz and beyond.
- Reverse-drive possible: push-pull on both ends, tri-state release, or shared lines.
Pass criteria (measurable)
- No contention signature: no abnormal supply current spikes during direction inference windows.
- Glitch control: no pulses above X (threshold) or wider than X ns during tri-state transitions.
- Worst-case load: stable across the maximum Cin/trace length and temperature corners.
Direction-Pin (DIR) and OE Control: Deterministic and Safe
Intent: controlled direction + controlled Hi-Z
DIR/OE parts make direction explicit and tri-state behavior controllable. This is the preferred approach for high speed, large loads, strict timing, and any design that must manage power sequencing or hot-plug safely.
Roles (what each pin controls)
DIR
Direction
- Fixed direction: simplest and most robust.
- Dynamic switching: allowed, but must follow a safe sequence (OE gating + delays).
OE
Safety
- Power-up isolation: keep buses Hi-Z during reset/unknown states.
- Hot-plug / modular: isolate during insertion/removal transients.
- Back-power prevention: block unintended current when one domain is unpowered.
Safe switching sequence (SOP)
- Disable outputs: set OE = 0 (Hi-Z).
- Wait for disable: hold for tDIS ≥ X (datasheet-based).
- Change direction: toggle DIR only while outputs are Hi-Z.
- Setup time: wait tSU(DIR) ≥ X before enabling.
- Enable outputs: set OE = 1 and allow tEN ≥ X before the next critical sampling edge.
Direction mapping (typical SPI example)
- MOSI / SCLK / CS: fixed A→B direction → unidirectional buffers are ideal.
- MISO: fixed B→A direction → separate unidirectional channel is preferred.
- If a bidirectional part is used: group signals by direction and avoid dynamic DIR toggling during active transfers.
Pass criteria (measurable)
- No glitch on DIR change: during DIR toggles (OE=0), the line stays below/above thresholds by margin X.
- Disable/enable timing met: measured tDIS/tEN allow safe sampling windows.
- Power-state safety: with one domain unpowered, no back-power current exceeds X mA (system policy).
Power Sequencing, Partial Power-Down, and Back-Powering Traps
Intent: prevent “logic works, but power states kill it”
Many “mysterious” translation failures are caused by power-state violations rather than logic thresholds. If a signal is present while a target domain is unpowered, current can flow through input protection structures and ghost-power the rail. This leads to half-awake logic, unstable reset behavior, latch-up-like symptoms, and non-repeatable bring-up.
Symptom map (what it looks like on real boards)
- “Off” rail never reaches 0 V: a small lift appears during cable attach or when a neighbor domain is active.
- Reset becomes unreliable: brown-out or hot-plug causes partial boot, stuck states, or random direction behavior.
- Intermittent contention or heating: overlapping drive happens during power transitions or when pins float.
- “Works after replug”: power-state history affects behavior (classic sign of injected current paths).
Back-power current paths (what actually conducts)
Clamp path
IO → VDD
If an input exceeds an unpowered domain’s rail by a diode drop, current can flow from the input into the rail. The domain may partially power and misbehave.
ESD / input network
Leak + inject
Protection networks can conduct in ways that are not obvious from “5 V tolerant” marketing. The unpowered state must be validated explicitly.
Translator path
Ioff / isolation
Without true Ioff or VCC isolation, the translator can become the bridge that injects current into an unpowered domain during hot-plug or sequencing gaps.
Datasheet gates (requirements to verify)
- Ioff / IO-off leakage: defined behavior when VCC=0; leakage/injection limited to X (system policy).
- Partial power-down support: valid operation when only one domain is powered; no unintended outputs.
- VCC isolation: explicit internal isolation that prevents rail lift during input presence.
- Power-state truth table: defined output state for each VCC_A/VCC_B combination and OE/DIR state.
Must-do mitigation (translator-focused)
1) OE gating for power-up and hot-plug
- Default: OE=0 (Hi-Z) until both rails are valid and stable.
- Enable: wait tEN ≥ X before critical sampling edges.
- Disable: assert OE=0 early on brown-out; wait tDIS ≥ X.
2) Series-R as an injection limiter
- Purpose: limit clamp current during “signal-before-power” events and reduce edge spikes.
- Placement: near the driving source of the risky edge (MCU or translator output).
- Validation: verify rail lift and injection current against system limits.
3) Brown-out behavior must be defined
- Avoid floating thresholds: prevent IO from hovering mid-level during VDD ramps.
- Reset integrity: hold resets until rails are valid; release after OE sequencing.
- Repeatability: cycle power and hot-plug events to confirm deterministic recovery.
Pass criteria (measurable)
- Injection current: with VDD=0 and VIN=High, injected current ≤ X mA (policy).
- Rail lift: “off” rail rise ≤ X V during cable attach / neighbor-domain activity.
- Reset behavior: no false release or stuck states across brown-out ramps.
- Recovery: N-cycle hot-plug/power-cycle test passes without latch or abnormal heating.
Signal Integrity: Edge-Rate, Capacitance, and High-Speed Translation
Intent: make “speed / edge / load” predictable and testable
Translation often “works” at the bench but fails in the system because the edge shape at the receiver is not what the driver assumes. Input capacitance, traces, connectors, and cables form an RLC environment that produces overshoot, ringing, and timing erosion. Edge-rate must be engineered: fast enough for timing margin, slow enough to reduce ringing and EMI.
Dominant loads (what increases effective capacitance)
- IC input Cin: each receiver adds pF-scale load; many endpoints add up.
- Trace + vias: routing length, stubs, and reference changes create discontinuities.
- Connector + cable: impedance steps and added C/L increase reflections.
- Pull-ups (open-drain): strong pull-ups speed edges but can worsen ringing and mis-detect risks.
What goes wrong (receiver-side view)
Overshoot / undershoot
Discontinuities reflect energy. Peaks can violate absolute maximum ratings and create false switching.
Ringing and double-threshold crossings
A single transition can cross thresholds multiple times, producing extra edges, direction flips, or spurious sampling.
Timing erosion
Slow edges and long settling reduce noise margin and shrink the usable sampling window.
Series-R damping strategy (minimal rules that work)
- Goal: reduce ringing and overshoot while keeping timing margin.
- Placement: put series-R close to the strongest edge source (MCU output or translator output).
- Decision rule: tune using far-end waveforms; prioritize eliminating double-threshold crossings.
- High-speed guidance: prefer unidirectional buffers or dedicated high-speed translators; avoid generic auto-direction when load varies widely.
Pass criteria (simple and measurable)
- Overshoot/undershoot: within ABS MAX − X across worst-case load and cable conditions.
- Settling: ringing decays within X ns so the receiver sees a stable level before sampling.
- No double-crossing: transitions cross logic thresholds once (no extra edges).
- Timing window: receiver threshold is met with margin X under worst-case corners.
Protocol-Specific Patterns: I²C vs SPI vs UART (Translation-Relevant Only)
Scope: signaling type + direction + tri-state behavior
Not covered: protocol timing rules / PHY transceivers
The bus name matters because translation constraints are driven by signaling style (open-drain vs push-pull), directionality (uni- vs bi-directional), and whether a line must release into Hi-Z. The goal is to map each protocol’s wiring pattern to a translator family priority list.
I²C
Bi-dir on same lines (SDA/SCL)
Open-drain + pull-ups
What matters for translation
- Open-drain must be preserved: no push-pull “help” on the bus.
- Pull-up strategy defines edges: pull-up rail, location, and segmentation.
- Bidirectional on shared lines: direction-guessing structures are error-prone when edges vary.
Translation hazards
- LOW-transfer weakness: low-voltage side may not pull the high-voltage side low reliably under strong pull-ups.
- Overshoot/ringing: strong pull-ups and edge accelerators can create false threshold crossings.
- Mis-detect risk: direction-guessing behavior under varying RC/load is fragile.
Preferred translator families (priority)
- Open-drain bidirectional (pass-style / I²C-preserving shifters).
- I²C-specific buffers / segmenters that keep wired-AND semantics.
- Avoid generic auto-direction unless pull-ups, load, and rise-time are tightly controlled and validated.
SPI
Mostly uni-dir lines
Hi-Z on MISO (common)
What matters for translation
- MOSI/SCLK/CS are one-way: deterministic unidirectional channels are ideal.
- MISO is opposite direction: treat it as a separate unidirectional path.
- Tri-state release: multi-slave designs often rely on MISO Hi-Z between drivers.
Translation hazards
- Auto-direction mismatch: Hi-Z release or load variation can trigger direction errors and glitches.
- Unsafe DIR switching: changing DIR without disabling OE can create contention or extra edges.
Preferred translator families (priority)
- Unidirectional buffers/translators split by signal direction (most robust).
- DIR/OE controlled channels (prefer fixed direction groups; avoid mid-transfer flips).
- Avoid generic auto-direction for high speed, heavy load, or multi-slave MISO Hi-Z patterns.
UART
TX/RX are uni-dir
PHY (RS-232/485) → jump
What matters for translation
- Threshold margin: VIH/VIL compatibility and noise margin dominate link stability.
- Power states: Ioff / partial power-down avoid back-powering during sequencing and hot-plug.
Translation hazards
- Slow edge + noise: reduced margin shows up as framing/parity errors.
- Back-power traps: “5 V tolerant” is not sufficient without defined VCC=0 behavior.
Preferred translator families (priority)
- Unidirectional translators with solid VIH/VIL margin and predictable edges.
- Add OE when needed for power sequencing, isolation, and hot-plug safety.
- If RS-232/RS-485 is required: use a dedicated PHY transceiver page (not covered here).
Key takeaway
I²C: preserve open-drain and engineer pull-ups. SPI: split directions and respect Hi-Z release. UART: maximize threshold/noise margin; keep power-state behavior deterministic.
Selection Checklist: What to Look for in Datasheets
Intent: turn selection into a deterministic checklist
Translator selection is reliable only when datasheet fields are converted into gates (hard reject), rank criteria (fit and margin), and verification items (measurable acceptance). The checklist below keeps multi-voltage, mixed-power-state systems from failing during bring-up.
Gate: reject conditions
- No defined VCC=0 behavior: missing Ioff / partial power-down / isolation spec in a multi-rail system.
- Signaling mismatch: open-drain preservation required but the path can drive push-pull high.
- Direction uncertainty: target topology has reverse-drive or Hi-Z release but only generic auto-direction is available.
- Overshoot risk without control: expected ringing can exceed safe limits with no margin for damping.
Rank: compare candidates using these groups
Electrical
- VIH/VIL, VOH/VOL, input leakage, drive strength, pull-up compatibility.
- Ioff, fail-safe input, over-voltage tolerance, partial power-down support.
Timing
- Propagation delay (tPLH/tPHL) and channel-to-channel skew.
- DIR/OE switching timing, enable/disable behavior (tEN/tDIS).
Robustness
- Hot-plug tolerance, input range (beyond rails), safe defaults under brown-out.
- Defined behavior during mixed-power states (one rail up, one rail down).
System
- Package, channel count, OE/DIR pins, power-up default states.
- Idle power, dynamic switching power, thermal headroom.
Verify: minimal acceptance tests (measurable)
- Power-state test: VDD=0, VIN=High → injected current ≤ X mA and rail lift ≤ X V.
- Waveform test: far-end overshoot/undershoot within limits; no double-threshold crossings.
- Enable/dir test: OE/DIR transitions create no threshold-violating glitches; obey tDIS/tEN.
- Worst-case load test: max Cin / cable / temperature corners remain stable with margin X.
Engineering Checklist (Design → Bring-up → Production)
Goal: deterministic translation across power states
Output: gates + evidence + pass criteria (X placeholders)
This checklist turns level-translation decisions into three auditable gates. Each gate includes items to check, required evidence, and measurable pass criteria. Concrete material numbers are provided as reference examples—verify package, suffix, and availability for the target build.
Gate 1 · Design
Lock boundaries + power-state behavior
Checklist (design-time)
- Voltage-domain matrix: VDD_A/VDD_B min/typ/max, plus mixed-power states (A on/B off, A off/B on).
- Back-power policy: define whether any injection is allowed; default is “No injection when VDD=0”.
- Direction map (protocol-relevant only): I²C (bi-dir open-drain on shared lines), SPI (uni-dir split, MISO opposite), UART (TX/RX uni-dir).
- Pull-up budget (open-drain): choose pull-up rail/location/segmentation; verify rise-time and static power in worst-case load.
- SI hooks (translation-focused): series-R placement plan and maximum capacitive load per net; avoid “generic auto-direction” in high-speed/heavy-load paths.
Required evidence (attach to design package)
- Voltage-domain table + mixed-power state matrix.
- Direction map per net (by function, not by protocol theory).
- Pull-up budget note (target rise-time and estimated static loss).
- Translator family decision note (why open-drain / uni-dir / DIR+OE is chosen).
Pass criteria (set project thresholds)
- VIH/VIL margin: worst-case ΔV ≥ X mV across temp/process/noise.
- Power-state safety: VDD=0, VIN=High injection current ≤ X mA; rail lift ≤ X V.
- Open-drain behavior: no driven-high on SDA/SCL; pull-up strategy meets rise-time ≤ X ns at max load.
Reference material numbers (examples; verify package/suffix)
Open-drain / I²C-preserving
- NXP PCA9306 (dual bi-dir I²C level translator, pass-style).
- TI TCA9406 (dual bi-dir translator for open-drain buses).
- TI TCA9517A (I²C buffer/repeater class; use when segmentation is needed).
- Discrete MOSFET approach: BSS138 (bi-dir open-drain level shifting topology).
DIR/OE deterministic (best for SPI split / controlled switching)
- TI SN74LVC8T245 (octal bus transceiver family; DIR/OE controlled).
- TI SN74AXC8T245 (AXC family; DIR/OE controlled for low-voltage domains).
- Nexperia 74LVC1T45 / 74LVC2T45 (single/dual-bit, DIR controlled options).
Auto-direction (use only with constraints + validation)
- TI TXS0108E (auto-direction class; commonly used for open-drain/mixed use cases under constraints).
- TI TXB0108 (auto-direction push-pull class; avoid when Hi-Z release or strong drive contention is possible).
Sequencing helpers (optional but practical)
- TI TPS3808 (supervisor family; gate OE until rails are valid).
- onsemi NCP303 (supervisor family alternative).
- Low-cap ESD arrays (port protection hook): Nexperia PESD5V0S1UL, TI TPD4E05U06 (use per port policy).
Gate 2 · Bring-up
Validate control + waveforms + fault recovery
Probe plan (minimum)
- A-side IO (near translator input) and B-side IO (near translator output).
- OE and DIR pins (if used), plus VDD_A and VDD_B rails.
- Ground reference points to avoid measurement artifacts.
OE/DIR control verification (SOP)
- Hold OE=0 on power-up; confirm both sides remain Hi-Z (no driven-high on open-drain nets).
- Set DIR (if applicable), wait ≥ X (tSU placeholder), then assert OE=1.
- Direction changes must follow: OE=0 → wait tDIS → DIR flip → wait → OE=1.
- Capture A/B waveforms and confirm glitch-free enable/disable and stable threshold margins.
Fault injection (must-run)
- Power-off test: force VDD_B=0 while driving/toggling from the live side; verify injection current and rail lift stay within limits.
- Hot-plug sequence: simulate “signal first, power later”; verify OE gating prevents ghost powering and lockups.
- Strong pull-up / heavy load: tighten pull-ups or add capacitance; confirm no false threshold crossings and stable low transfer (open-drain).
Bring-up pass criteria (placeholders)
- Injection: VDD=0, VIN=High → ≤ X mA; rail lift ≤ X V.
- Waveform: overshoot/undershoot within safe bounds; no double-threshold crossings; settling ≤ X ns.
- Control: OE/DIR transitions are glitch-free; contention events = 0 under all injected faults.
Bring-up tool references (model numbers)
- Logic analyzer: Saleae Logic Pro 8 / Logic Pro 16 (I²C/SPI/UART decode).
- Oscilloscope (entry): Rigol DS1054Z (waveform sanity; bandwidth depends on edge rate).
- Differential probing (optional): choose probes matched to expected bandwidth and common-mode range.
Gate 3 · Production
Scriptable tests + isolation tree + margin logs
Production test script (minimum)
- Loopback / continuity: verify channel mapping and direction (A→B and B→A where applicable).
- Edge acceptance: coarse waveform constraints (overshoot/settling/glitch amplitude) with limits X.
- Power-state safety spot-check: sample units run VDD=0 injection test (or proxy) per policy.
Failure isolation (which side is incompatible?)
- Rails first: confirm measured VDD_A/VDD_B at worst-case corner is inside the voltage-domain table.
- Control state: check OE/DIR default straps/firmware match the direction map.
- Waveform split: compare A-side vs B-side node behavior to locate translator-side vs source/load-side issues.
Margin log (traceability fields)
- Unit ID / lot / date code; ambient (or temperature bin).
- Measured VDD_A/VDD_B; OE/DIR configuration snapshot.
- Key metrics (overshoot/settling/glitch/injection proxy) with limits X.
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FAQs (Troubleshooting, Data-Driven)
Scope: level translation only (no PHY/protocol deep-dive)
Format: Likely cause / Quick check / Fix / Pass criteria (X)
Each answer is constrained to translation-relevant behavior (direction control, open-drain preservation, power-state safety, and edge/RC effects). Thresholds use X placeholders to be set per project.
1) 1.8 V ↔ 3.3 V auto-direction translator shows occasional SPI bit-slip at high speed
Likely cause: auto-direction edge detection mis-triggers under fast push-pull edges, heavy load (Cin/trace), or Hi-Z release on MISO, causing brief contention or wrong direction.
Quick check: scope A/B nodes at SCLK = X MHz; look for mid-level plateau, double-threshold crossings, or skew change near the failing burst; log “bit-slip per 10⁶ bits”.
Fix: split SPI into uni-direction paths (recommended) or use DIR/OE controlled family; add source series-R = X Ω to damp ringing; ensure MISO Hi-Z truly releases before another device drives.
Pass criteria: bit-slip rate ≤ X ppm over X minutes; contention events = 0; A↔B skew ≤ X ns at worst load.
2) I²C works at low speed but fails (NACK / arbitration loss) at higher speed
Likely cause: open-drain rise time too slow (RC too large) or edge-accelerator/strong pull-up causes overshoot/ringing that creates false edges through the translator.
Quick check: measure SCL/SDA rise time (30–70%) at max bus load: tR = X ns; look for overshoot > X V or double crossings near VIH.
Fix: adjust pull-ups to meet target tR; remove/disable edge accelerators in mixed buses; segment the bus (buffer/switch) and keep open-drain semantics on each segment.
Pass criteria: tR ≤ X ns at Cbus(max); arbitration loss ≤ X per 10⁶ transactions; NACK rate ≤ X ppm in a stress test.
3) A device is “ghost-powered” after VDD is off and the system cannot fully power down
Likely cause: back-power path through input clamp/ESD structures or translator internal paths when VDD=0 and an IO is driven high.
Quick check: force VDD_B = 0, drive VIN = High; measure injection current Iinj = X mA and rail lift Vlift = X V at the “off” rail.
Fix: require Ioff / partial power-down support; gate translation with OE until rails are valid; add series-R = X Ω to limit injection; avoid pull-ups to an unpowered rail.
Pass criteria: Iinj ≤ X mA; Vlift ≤ X V; off-state system current ≤ X µA; power cycles X times with 0 lockups.
4) Large current and heating when both sides are push-pull and drive simultaneously (contention)
Likely cause: contention caused by auto-direction mis-detect or incorrect DIR/OE sequencing, leading to simultaneous opposite drive.
Quick check: measure supply transient or series sense resistor: Icc_peak = X mA; scope the IO showing a flat mid-level “fight” plateau lasting X ns.
Fix: move to deterministic DIR/OE or uni-direction split; enforce “OE=0 → wait tDIS → change DIR → wait tEN → OE=1”; add series-R to limit fight current if contention cannot be fully avoided.
Pass criteria: contention events = 0 across stress; Icc_peak ≤ X mA; no sustained mid-level > X ns.
5) A glitch appears at OE enable and triggers an external device unexpectedly
Likely cause: OE turn-on edge couples into outputs or the translator output stage briefly drives before inputs/DIR are stable.
Quick check: scope output during OE rising edge; quantify Vglitch = X V and tglitch = X ns; check whether the glitch crosses VIH/VIL thresholds of the receiver.
Fix: assert OE only after DIR and inputs are stable; add RC delay on OE (τ = X ms) or use a supervisor-gated OE; add series-R close to the driver to tame the enable edge.
Pass criteria: glitch does not cross VIH/VIL; Vglitch ≤ X V and tglitch ≤ X ns at worst load; 0 false triggers in X enable cycles.
6) Long traces / large capacitance slow edges and even the logic analyzer decode looks wrong
Likely cause: excessive RC and reflections distort edge timing; thresholds are crossed late or multiple times (ringing), breaking sampling assumptions.
Quick check: measure tR/tF at the receiver node: tR = X ns; check overshoot Vov = X V and settling time tset = X ns.
Fix: add source series-R, shorten stubs, reduce speed to X; use a stronger/cleaner uni-direction buffer for high-speed nets; keep auto-direction out of heavy-load paths.
Pass criteria: tR/tF within target; Vov ≤ X V; tset ≤ X ns; decode error rate ≤ X ppm over X minutes.
7) “5 V tolerant” seems OK, but some lots show abnormal input leakage
Likely cause: tolerance condition is not met (e.g., only valid in certain power states) or the input structure allows measurable leakage/injection under VDD=0 or near brown-out.
Quick check: bench-test IIN at VIN=5.0 V for VDD=0 and VDD=on; record IIN = X µA at X °C; compare against datasheet corner spec.
Fix: require fail-safe/Ioff behavior (explicitly specified for VDD=0); add series-R = X Ω to limit injection; add incoming inspection limits for leakage and rail-lift behavior.
Pass criteria: IIN ≤ X µA at corner; Iinj ≤ X mA with VDD=0; 0 units exceed limit in sample size X per lot.
8) After DIR switching, the first frame is off by one bit (timing / enable sequence)
Likely cause: DIR changes while the bus is not idle or OE is still enabled; tDIS/tEN requirements are violated, causing a transient drive or sampling misalignment.
Quick check: capture DIR, OE, and data; verify the sequence “OE low → wait → DIR flip → wait → OE high”; measure actual waits: tDIS = X ns, tEN = X ns.
Fix: enforce deterministic switching only in an idle gap; gate OE low during direction changes; if the protocol does not guarantee idle gaps, avoid mid-stream DIR switching (use fixed uni-direction split).
Pass criteria: first-frame errors = 0 over X direction toggles; no output glitch crossing VIH/VIL; waits meet or exceed datasheet limits (≥ X ns).
9) I²C rise time fails after adding a translator — how to quantify quickly?
Likely cause: added capacitance and pass elements increase effective RC; pull-ups are too weak or placed only on one side, stretching tR beyond the bus target.
Quick check: measure tR (30–70%) and estimate bus capacitance: Cbus ≈ tR / (0.85 · Rpull); compare estimated Cbus to the load budget X pF.
Fix: reduce Rpull (while checking static sink current), segment the bus with a buffer/switch, or move pull-ups to each domain rail (preserving open-drain behavior on both sides).
Pass criteria: tR ≤ X ns at worst-case Cbus; static pull-up current ≤ X mA during low; NACK rate ≤ X ppm in a stress test.
10) Same circuit, different translator vendor makes EMI worse (edge / overshoot)
Likely cause: different output impedance/edge rate changes ringing and high-frequency content; faster edges produce larger overshoot and stronger coupling.
Quick check: compare time-domain proxies at the same node: edge rate dV/dt = X V/ns, overshoot Vov = X V, settling tset = X ns.
Fix: add source series-R = X Ω; choose a translator with controlled slew/stronger damping; reduce stubs and tighten return path around the translated net.
Pass criteria: Vov ≤ X V; tset ≤ X ns; dV/dt ≤ X V/ns; no functional errors under worst-case traffic for X minutes.
11) For open-drain, should pull-ups be on the high-voltage side or the low-voltage side?
Likely cause: a single-side pull-up can violate open-drain domain semantics or create injection when one rail is off; RC budget may be met on one side but fail on the other.
Quick check: evaluate each power state; with VDD_A on / VDD_B off, check Iinj and rail lift; measure tR on both sides: tR_A = X ns, tR_B = X ns.
Fix: use pull-ups to each domain rail (A to VDD_A, B to VDD_B) to preserve open-drain semantics; avoid pull-ups to an unpowered rail; segment if Cbus is large.
Pass criteria: both sides meet tR ≤ X ns; VDD-off injection ≤ X mA; static low-level sink current ≤ X mA at worst corner.
12) Different reset/power order across voltage domains causes occasional lockups (partial power-down)
Likely cause: partial power-down is not supported or OE/DIR are not gated during brown-out; floating IO sits near thresholds, causing unintended toggles or back-powering.
Quick check: run a matrix of power/reset sequences (X permutations); monitor OE/DIR state, rail lift, and any unexpected IO toggles; record lockup rate per 10³ cycles.
Fix: hold translation disabled (OE=0) until both rails are valid; add supervisor gating for OE; require explicit partial power-down support and Ioff behavior for mixed-power operation.
Pass criteria: 0 lockups over X power cycles across all sequences; Iinj ≤ X mA; outputs remain Hi-Z until rails valid for ≥ X ms.
