• Included: connectors, headers, test points, cable entry points, and any I/O that can be touched by humans, cables, fixtures, or field wiring.
• Excluded: protocol semantics (I²C arbitration rules, SPI mode negotiation, UART framing logic). Those belong to the bus-specific pages.
• Practical boundary: from the connector pin to the interface IC pin (including the “protect + damp + route” region).

• ESD: fast edge, high peak current, extremely sensitive to return-path inductance.
• EFT: repetitive bursts that often trigger resets/lockups rather than immediate damage.
• Surge / Over-voltage: higher energy; clamp capability and thermal handling dominate.
• Hot-plug: insertion bounce and ground shift; can generate overshoot and brownout coupling.
• Miswire / Reverse / Ghost-power: wrong wiring, back-power paths through I/O clamps, and rail lift from external sources.

• IEC level: IEC 61000-4-2 contact ±X kV (and/or air ±X kV), as required by the product environment.
• Functional hold: no latch-up; if reset occurs, auto-recover within ≤ Y ms; no stuck I/O lines after stress.
• Link integrity: error count ≤ Z per minute (or dropout ≤ Z per day) under defined stress/handling conditions.

Note: bus timing budgets (rise-time, sampling windows, baud tolerance) remain on the bus-specific pages; this page focuses on the port’s physical protection layer.

• Classify by signature: “fast edge” vs “energy” vs “repetitive burst” vs “insertion/miswire path.”
• Choose the energy exit: clamp to ground, clamp to rails, or limit-and-disconnect (each has different failure paths).
• Control the return loop: placement + vias define inductance; inductance defines clamp effectiveness for fast events.
• Budget side effects: added capacitance/leakage and edge slowing must remain within the bus timing margin (handled on bus pages).
• Define pass metrics: “no latch-up,” “auto-recover ≤ Y ms,” “error ≤ Z” under the chosen stress set.

1. Stress signature: fast edge (ESD), burst (EFT), energy (surge/OV), or path-driven (hot-plug/miswire).
2. Primary knob: choose the variable that actually controls failure (C, Rdyn, Vclamp, leakage, τ, I-limit).
3. Side effects: added capacitance/leakage and edge slowing must remain within timing margin (timing details live on bus-specific pages).

• This section: classification and “when to use” each tool, plus trade-offs and failure paths.
• Not here: detailed part selection tables (covered in H2-12) and layout deep-dive (covered in H2-8).
• Not here: bus timing budgets (rise-time, sampling windows, baud tolerance) — those live on the I²C/SPI/UART pages.

• Series-R start: X Ω (validate on waveform; adjust until ringing and overshoot meet criteria).
• Added capacitance budget: ≤ Y pF per line (maintain timing margin; bus specifics live on bus pages).
• Clamp placement goal: connector → clamp distance ≤ Z mm (minimize return-loop inductance).

• ESD is a current event: fast edges produce high peak current; the board’s loop inductance can dominate the clamp voltage.
• Clamps win by being “close + low impedance”: the best part still fails if current must travel deep into the board first.
• Port robustness includes “no harm at rest”: leakage and coupling can destabilize low-level or low-power states even without stress.

• Edge shape: added C slows edges and increases threshold-crossing time, reducing noise immunity under interference.
• Crosstalk sensitivity: extra shunt capacitance can increase coupling, especially when multiple adjacent lines switch.
• Most sensitive victims: high-impedance nodes, comparator-like thresholds, and open-drain lines can show “works on bench, fails in field.”

• Do not stop at VRWM: VRWM indicates non-conduction in normal operation, not clamp behavior at ESD peak current.
• Rdyn drives the damage path: higher Rdyn typically implies higher Vclamp at the same peak current, pushing stress into the IC.
• Read the right evidence: prefer curves or test conditions that show Vclamp under current (not just “ESD level”).

• Open-drain and low-level states: leakage can bias the line, causing false lows/highs or stuck-bus symptoms.
• Low-power sleep: leakage can dominate standby current budgets and create temperature-dependent failures.
• High-impedance sensing: leakage can appear as an offset, leading to intermittent mis-detection under humidity/temperature shifts.

• Passive crosstalk path: shared silicon and package parasitics can couple noise between adjacent protected lines.
• When it shows up: long cables, dense connectors, and multiple lines switching during burst noise events.
• Mitigation direction: keep symmetry, avoid mixing ultra-sensitive and noisy lines in the same array when possible, and control return routing.

• Loop inductance dominates fast events: extra millimeters of current path can raise the clamp voltage meaningfully.
• Placement rule: clamp at the entry; avoid letting the transient travel through narrow traces before being clamped.
• Boundary: detailed layout tactics (via stitching, plane splits, chassis/logic return strategy) are covered in the layout-focused section.

1. Limit peak current into clamps and IC structures during fast transients.
2. Increase effective source impedance to reduce reflections and edge “bounce.”
3. Damp ringing so the waveform settles quickly instead of repeatedly crossing thresholds.

• Best for: glitch suppression, burst-noise hardening, and reducing repeated threshold crossings.
• Knob: τ = R×C (time constant) defines how aggressively the edge is slowed.
• Risk: too much τ increases threshold-crossing time and can create new sensitivity to slow-slew noise.

1. Start with Series-R = X Ω (placeholder) and keep C unchanged.
2. Measure consistently: same cable/fixture, same probe method, same trigger reference.
3. Adjust R toward Y Ω until overshoot and ringing meet pass criteria; stop once margin begins to collapse.
4. Only then consider RC if glitches persist and there is timing headroom.

• Near driver: shapes the launched edge and reduces source-end reflection effects.
• Near connector: intercepts entry-side energy and limits what propagates into the board.
• Decision rule: place damping at the segment where the unwanted energy is injected or where reflection is initiated.

• Overshoot: < X% of nominal (placeholder).
• Ringing decay: settles to < Y% within Z ns (placeholder).
• No false crossings: waveform does not re-cross critical thresholds after the initial transition.
• Repeatability: results stay consistent across temperature/fixtures and repeated disturbances.

• External cable exposure: long cabling, field wiring, or environments with inductive loads and switching transients.
• Energy dominates: events that can sustain current or repeat with significant amplitude (surge-like, miswire-like).
• Observed symptoms: VDD rail lift, repeated resets, lockups, or parts that “pass once” but become more fragile later.
• Rule of thumb (conceptual): ESD arrays target fast edges; TVS devices must handle energy and heat.

• Path: External OV → connector → IO pin → clamp/diode path → VDD rail → board loads.
• Outcome: VDD lift can trigger brown-out loops, undefined peripheral states, and “unplug fixes it” intermittent failures.
• Design target: control injection current and ensure energy returns to a path that does not back-power logic rails.

• Strength: avoids lifting the logic rail when the return path can absorb the current.
• Primary risk: ground bounce and sensitive-domain contamination if the return loop is long or crosses quiet areas.
• Layout direction: keep the clamp and its return loop short and confined to a dedicated protection zone.

• Strength: can keep IO within a safe window in some cases.
• Primary risk: rail lift / ghost-power if the rail cannot sink injected current.
• Required condition: define an absorption path (sink) or isolate/disconnect so injected current cannot energize the full board.

• Tools: series-R/PTC, eFuse/load switch, controlled disconnect, and staged protection.
• Best for: sustained over-voltage, miswire, and repeated stress where thermal energy accumulates.
• Design target: keep fault energy out of the board rails and force recovery into a known safe state.

• Tolerance ≠ infinite energy: it does not mean unlimited injected current or thermal survival.
• Tolerance ≠ hot-plug immunity: insertion transients can still forward-bias paths into rails.
• Tolerance ≠ no back-power: clamp/diode paths can still lift VDD without a sink or disconnect strategy.

• Connector Zone: external entry; allow “dirty” energy, keep it from spreading.
• Protection Zone: TVS/ESD, limit, disconnect; provide the shortest return loop and via stitching.
• Quiet IC Zone: sensitive domain; prevent large transient return currents from crossing this area.

• Shortest loop wins: a longer return path increases effective inductance and raises peak clamp voltage.
• Confine the loop: route high-current returns so they close inside the protection zone.
• Avoid sensitive crossings: do not allow clamp return currents to traverse quiet reference regions.

• Fast current + inductance → extra voltage: the board loop adds voltage on top of the device clamp behavior.
• Layout review view: check loop geometry (distance, detours, plane gaps) before changing part numbers.
• Target behavior: clamp engages early at the entry; minimal energy propagates into the quiet zone.

• Keep returns symmetric: uneven return length creates uneven clamp behavior and cross-coupling.
• Minimize shared parasitics: avoid routing that forces multiple channels through a single narrow return neck.
• Prefer clean topology: entry → clamp → then fan-out to IC pins.

• Do: entry → protection (clamp/limit) → IC.
• Avoid: letting a transient run into the board interior before it sees the clamp.
• Reason: internal detours increase loop area and raise peak stress at the IC pin.

• Connector → TVS/ESD distance: ≤ X mm (placeholder).
• TVS/ESD → return vias: ≥ Y stitched vias (placeholder).
• High-current loop confinement: close inside protection zone; avoid crossing quiet-zone reference.
• Multi-channel symmetry: matched return length and via strategy across channels.

• Symptom patterns: “false-low” idle, intermittent NAKs, a bus that appears stuck after stress or hot-plug.
• Likely protection causes: leakage biasing an open-drain node, added capacitance slowing edges and increasing threshold sensitivity, clamp-to-rail injection lifting a sleep/off rail.
• Quick checks: measure idle level at the port node, compare edge shape before/after the protection node, observe rail lift during disturbances.
• First fixes (port-layer): reduce leakage and unwanted C at the entry, prefer a return strategy that avoids back-powering, keep the entry clamp loop short.

• Symptom patterns: works at a lower rate but fails at the top rate; intermittent bit slips; errors increase after changing the ESD array.
• Likely protection causes: added capacitance blunting edges, series-R/RC shrinking the effective sampling margin, return-path noise coupling into SCLK/MISO.
• Quick checks: compare SCLK overshoot/ringing vs edge slowing; compare series-R near driver vs near connector; check MISO integrity at the receiver pin.
• First fixes (port-layer): low-C / low-leakage clamps on sensitive lines, small-R damping with correct placement, keep clamp returns confined to the protection zone.

• Symptom patterns: framing/parity errors in bursts, failures on long cables, errors correlated with external switching or plug/unplug.
• Likely protection causes: common-mode stress forcing return currents through sensitive areas, clamp paths injecting into rails, unclear division of labor between port protection and RS-232/RS-485 front ends.
• Quick checks: correlate errors with common-mode events, observe rail lift during disturbances, verify that port-side energy stays near the entry.
• First fixes (port-layer): contain energy at the connector, choose clamp/disconnect strategy to avoid back-powering, keep high-current returns out of quiet reference regions.

• Benefit: extra damping can reduce ringing and false triggers under noise.
• Cost: edges become slower, thresholds are crossed for longer, and timing margin becomes tighter.
• Goal: apply only the minimum damping needed to meet robustness targets without consuming critical margin.

• Waveform: overshoot, ringing decay time, clamp behavior (peak at the protected node), and recovery to steady state.
• System: reset/lockup events, rail lift during stress, and recovery time to normal operation.
• Bus stats: error/NAK/frame counters, burstiness, and correlation to stress triggers.

• Oscilloscope: consistent probing method; capture at the port node and at the IC-side node to see what the protection changes.
• Differential/common-mode probes: use when long wiring or common-mode stress is suspected (avoid misleading single-ended views).
• Logic/protocol analyzer: trigger on error bursts, NAK sequences, framing/parity spikes, or lockup signatures.
• Event correlation: align waveforms with logs (timestamps) to avoid “looks fine” measurements that miss the true trigger.

1. Bring-up stable: confirm normal operation; ensure counters/logging are working.
2. Baseline waveforms: record port-node and IC-node behavior under a fixed load/cable setup.
3. Apply one change: add/adjust protection or placement (one variable at a time).
4. Step-up stress: apply repeatable stress steps; log stats and system events at each step.
5. Evaluate: pass/fail against criteria and proceed to root-cause split if needed.

• Waveform still rings/overshoots: revisit damping value and placement; check return loop size.
• Clamp peak still high: revisit loop inductance and clamp dynamic behavior; verify return stitching.
• System resets/locks: look for rail lift/ghost-power paths; verify clamp-to-rail sink/disconnect strategy.
• Errors burst in clusters: look for common-mode coupling and entry-zone energy spreading into quiet reference.

• Loopback/BIST: deterministic self-test path to validate IO integrity at power-on and after stress.
• Event counters: error counts, reset/lockup counts, and “recovery completed” markers.
• Test points: port node, IC node, VDD rail, and clamp return reference for fast debug.
• Logging discipline: timestamped records aligned with stress steps for correlation.

Template map (IDs referenced by this decision tree)

• T1: Single-ended, ESD array + series-R (general purpose)
• T2: Edge-sensitive, ultra-low-C ESD + small R + strict return-path
• T3: Differential, diff-ESD at port + optional CMC (connector-side only)
• T4: Two-stage, connector-stage + IC-stage protection (harsh cabling)
• T5: OV/miswire, clamp + current-limit/disconnect (avoid back-power)
• T6: Isolation boundary, protect both sides (no isolation deep dive here)

Selection logic (decision tree inputs → outputs)

1. Threat tier: ESD-only vs EFT vs Surge vs Miswire/OV (defines required energy handling).
2. Line type: short internal trace vs external cable (defines where staged protection is needed).
3. Sensitivity: low-capacitance need vs allowed edge slowing (defines ESD device class + damping).
4. Clamp strategy: clamp-to-GND vs clamp-to-rail vs limit/disconnect (avoids back-power).
5. Layout feasibility: return path and loop size must be realizable; otherwise change template.

Concrete reference BOM bundles (example material numbers)

Notes: SMBJ-series TVS examples above show the series and two concrete voltage options. Final selection must match the port’s maximum working voltage and allowed clamp level. For ESD arrays, confirm the capacitance class needed and the V_clamp@I_pk behavior rather than relying on stand-off voltage alone.