Line-Scan Camera (1D/2D-TDI): TDI, Sync, and 10GigE Data Path
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Core idea: A line-scan camera is a motion-synchronized imaging system—image failures (banding, missing lines, stretch, ghosting) are solved by proving which link breaks first: clock, trigger/encoder timing, data-path buffering/packets, or power/EMC.
This page turns those symptoms into a measurable evidence chain (two measurements → discriminator → first fix), so issues can be isolated and corrected quickly on the production line.
H2-1. Definition & System Boundary
Featured answer: A line-scan camera forms an image line-by-line while the target moves, so geometry and clarity are governed by line timing (line period/line rate) and deterministic sync (encoder/trigger/clock). A 2D-TDI line-scan integrates the same feature across multiple stages during motion to boost SNR—its success depends on motion-to-shift alignment and low-jitter clocks, not only bandwidth.
What this page covers (owned problem set)
This page is scoped to “motion-coupled imaging.” The focus is: how timing, trigger/encoder inputs, buffering, and GigE/10GigE packetization create (or prevent) stripes, missing lines, stretching, and jitter-driven artifacts.
Line rate limit
Sync drift
Striping / banding
Missing lines
Stretch / scale error
Jitter sensitivity
Drop vs packet-loss evidence
System boundary (inputs → outputs → constraints)
- Inputs (determinism sources): encoder A/B/Z (position/velocity quantization), TRIG_IN (line/frame/exposure gate), clock reference (XO/TCXO or external ref), and optional STROBE sync (timing alignment only).
- Outputs (verifiable results): pixel/line stream, counters/logs (LINE_CNT, FIFO_LVL, DROP_CNT, CRC_ERR), and network packets (GigE/10GigE).
- Constraints (why line-scan is different): line period must match motion; encoder/trigger edges must remain clean over long industrial cabling; clock jitter converts directly into repeatable stripes or phase slip; buffer depth determines whether bursts/resends become missing lines.
Typical applications (why line-scan is chosen)
- Web inspection: continuous motion demands stable line timing across long runs; tiny jitter becomes visible as periodic banding.
- AOI / PCB / FPD: fixed-pattern artifacts (column/FPN, shading) and timing misalignment can look like real defects; deterministic capture is critical.
- Barcode / logistics: speed changes and vibration amplify encoder quantization and trigger integrity issues, often causing stretch or intermittent line drops.
Out of scope (intentionally not expanded here)
- Depth pipelines (stereo/ToF/structured-light) and any depth algorithm tuning.
- Platform/gateway architecture; host software stack deep dives.
- Full interface “survey” and system time distribution (PTP/1588 design is external; only “external optional” references appear in diagrams).
- Lighting driver topology and PCIe frame-grabber DMA deep dives.
H2-2. Architecture Stack (Light → Lines → Packets)
The fastest way to debug a line-scan system is to assign every symptom to a layer and then collect two pieces of evidence per layer. This section defines the layer stack, the “knobs” that change behavior, and the observation points that separate camera-side line loss from network packet loss.
How to use this stack: pick the observed symptom, then check (1) the closest counter/TP and (2) one upstream discriminator. If evidence does not move with the layer, stop and switch layers.
Layer map (each layer has knobs + observables + failure signatures)
- L1 — Sensor / TDI core: line period, TDI stages, effective exposure, saturation margin.
- L2 — ROIC / ADC: CDS/black level, column behavior, fixed-pattern components (PRNU/DSNU).
- L3 — Clock & timing: ref source, PLL conditioning, pixel/line clock jitter budget.
- L4 — Line builder & buffer: FIFO/DDR depth, packet scheduling, counters (LINE_CNT/FIFO_LVL/DROP_CNT).
- L5 — Sync I/O: TRIG_IN and ENC_A/B/Z integrity, programmable delay, debounce/hysteresis (wiring robustness).
- L6 — Network: MAC/PHY, packetization, CRC errors, resend/flow behavior (GigE/10GigE).
Deep layer notes (what matters, what to check first)
L1 — Sensor / TDI core (motion-coupled imaging)
What matters: line period and motion-to-shift alignment dominate sharpness and geometry. In 2D-TDI, a small timing mismatch accumulates across stages and becomes repeatable ghosting or blur.
- Key knobs: line period, TDI stage count, integration window (effective exposure), gain/saturation margin.
- First 2 checks: verify LINE_CNT monotonic stability under constant speed; compare artifacts vs speed change to confirm motion coupling.
- Signature failures: ghosting that scales with speed; blur without bandwidth saturation; stage-count dependent striping.
L2 — ROIC / ADC (readout fingerprints)
What matters: black level stability and column behavior decide whether “vertical stripe” is sensor/readout or timing/network.
- Key knobs: CDS timing, black clamp / offset, analog gain, ADC range.
- First 2 checks: dark/flat-field capture to separate PRNU/DSNU; verify column-related artifacts stay fixed across line rate changes.
- Signature failures: fixed-position stripes (column FPN), offset drift with temperature, clipping on bright lines.
L3 — Clock & timing (low-jitter determinism)
What matters: ref jitter and PLL conditioning translate into phase uncertainty; periodic banding often matches a clock-related spur or beat condition.
- Key knobs: ref source (XO/TCXO/external), PLL bandwidth, clock routing discipline.
- First 2 checks: swap/lock ref source to see if banding frequency moves; scope TP2 for stability of ref/clock domain edges.
- Signature failures: periodic banding tied to ref; temperature-dependent degradation; intermittent phase slip at high line rates.
L4 — FPGA line builder & buffer (line loss vs packet loss)
What matters: if FIFO/DDR underflows or overflows, lines are dropped before networking; if CRC/resend explodes, the link is failing after packetization.
- Key knobs: FIFO watermark, DDR burst policy, packet pacing, internal queue sizes.
- First 2 checks: observe FIFO_LVL trend during stress; correlate DROP_CNT with visible missing lines.
- Signature failures: missing lines with stable CRC; burst-related drops; errors that appear at certain packet sizes.
L5 — Trigger / encoder I/O (stretch, scale, and intermittent sync)
What matters: long cables, ground shifts, and ringing can turn clean edges into false triggers; encoder quantization can look like geometry distortion or periodic jitter.
- Key knobs: input hysteresis/filtering, programmable delay, encoder decode mode, debounce window.
- First 2 checks: TP1 on TRIG_IN edge integrity under machine motion; verify encoder phase (A/B) stability and Z reference behavior.
- Signature failures: stretch/scale drift with speed; intermittent line start errors; failures that worsen with cable length or EMI events.
L6 — Network (GigE/10GigE packetization)
What matters: bandwidth may be sufficient, yet packet loss/resend and CRC errors create “effective” line loss; evidence must separate PHY errors from camera-side drops.
- Key knobs: packet size, pacing/inter-packet gap, resend behavior, flow/queue settings.
- First 2 checks: track CRC_ERR and resend stats; compare with DROP_CNT—if CRC rises without DROP, the loss is downstream of packetization.
- Signature failures: intermittent tearing linked to CRC/resend spikes; performance collapse under burst; cable/connector sensitivity.
Critical separator (camera-side drops vs network loss):
- If DROP_CNT increases while CRC_ERR stays stable, loss is likely before packetization (buffer/line builder side).
- If CRC_ERR or resend stats increase while DROP_CNT stays stable, loss is likely after packetization (PHY/cable/NIC path).
- If both increase together, start at L5 cabling/ground integrity and L3 clock stability, then re-test under speed/EMI stress.
H2-3. 1D vs 2D-TDI — The Time Mechanics of TDI / Phase Accumulation
Core principle: A line-scan image is a time-ordered sequence of lines. 2D-TDI improves SNR by integrating the same moving feature across multiple stages, but only if shift timing stays matched to motion. Any mismatch converts directly into spatial error (ghosting/blur/banding).
Practical discriminator: when artifacts change predictably with speed, the root cause is usually motion-to-shift alignment rather than network throughput.
TDI stages (N)
Line period (Tline)
Effective exposure
Saturation margin
Encoder quantization
Line/trigger jitter
1D line-scan vs 2D-TDI: what changes in time-domain
- 1D line-scan: each exposure produces one line; geometry is controlled by line period and motion speed. Timing errors appear as stretch/scale or line-to-line wobble.
- 2D-TDI: the same feature is sampled multiple times (stages) while moving; correct operation requires stage-to-stage shift to track motion. A small error repeats every line, becoming visible as ghosting or periodic banding.
Phase/charge accumulation vs digital accumulation (high-level only)
- Charge/phase accumulation (analog domain): can yield higher SNR when aligned, but misalignment is also accumulated—errors can become more obvious and can push bright regions into saturation earlier.
- Digital accumulation: alignment remains critical; benefits depend on stable black level and consistent per-line sampling. Misalignment still becomes spatial blur/ghosting.
Key parameters and where SNR gain stops helping
- TDI stages (N): ideal SNR improvement trends with √N, but only while motion alignment stays within a small fraction of a pixel and saturation margin remains.
- Line period (Tline): sets the shift cadence; higher line rates reduce timing margin and make jitter/quantization dominate earlier.
- Effective exposure: grows with accumulation; benefits depend on illumination stability and motion smoothness.
- Saturation margin: more stages increase the chance of clipping/drag in highlights; saturation can look like “banding” but is driven by accumulation, not link errors.
Mismatch mechanisms → artifact signatures (evidence-first)
- Speed drift (v changes): shift no longer matches motion. Signature: ghost spacing or blur severity scales with speed; repeating at fixed speed is stable.
- Encoder quantization / edge integrity: position updates become “grainy” or false edges appear on long cables. Signature: banding worsens in certain speed bands, cable-length sensitive, or appears with nearby EMI events.
- Line/trigger jitter (Δt): sampling instant uncertainty. Signature: periodic banding with a fixed frequency or spur-like behavior, often temperature/ref-source sensitive.
One conversion to remember: time error becomes spatial error under motion. If the motion speed is v, then a timing uncertainty Δt produces a position error roughly proportional to v×Δt. In 2D-TDI, repeated misalignment across stages makes the artifact more visible.
H2-4. Timing & Clocking — Why Low Jitter Determines Banding and Ghosting
Cause chain (engineering view): ref jitter → PLL phase noise → pixel/line edge uncertainty → timing error (Δt) → line-to-line phase error → periodic banding / phase slip / ghosting.
Low jitter is not “nice to have.” Under motion and high line rate, Δt quickly turns into visible spatial error and repeated patterns.
What to translate in practice: jitter (ps) → phase error per line
- Jitter budget is meaningful only after mapping to the system: line rate, motion speed, and TDI staging define how much Δt can be tolerated before spatial artifacts appear.
- Time uncertainty becomes spatial uncertainty under motion: the same Δt is more damaging at higher speed and higher staging because misalignment repeats and becomes more visible.
- Evidence-first test: when banding is fixed-frequency and survives scene changes, suspect clock/ref path before network throughput.
Clock tree elements (local camera view only)
- XO/TCXO: provides the reference; TCXO is often selected for better temperature stability. Focus is on stability and phase-noise behavior over temperature.
- Jitter-clean PLL: conditions the ref into multiple low-jitter domains; key purpose is to prevent ref noise from leaking into line sampling edges.
- Clock domains that matter: sensor_clk (sampling edges), fpga_clk (line building/buffer pacing), phy_ref (SerDes/CDR margin). These domains leak differently into artifacts and link robustness.
- External optional: external ref or external timestamp can be used as a comparison anchor; system time distribution is out of scope here.
Symptom mapping (frequency fingerprints)
- Periodic banding / fixed-frequency stripes: often tied to ref/PLL spurs or edge uncertainty. Fingerprint: the stripe frequency is stable and may shift when the ref source changes.
- Ghosting / phase slip near high line rate: appears as repeated misalignment events. Fingerprint: sensitivity increases with line rate and temperature.
- Worse after warm-up: points to temperature sensitivity in ref/PLL routing. Fingerprint: banding strength or frequency drifts with temperature.
First checks:
- TP2 ref/clock stability comparison: change/lock the ref and observe whether banding/ghosting changes meaningfully.
- Domain correlation: if artifacts track the sensor clock domain, focus on ref/PLL/sensor routing; if link CRC sensitivity rises with clock changes, check phy_ref integrity and cabling margin.
H2-5. Trigger & Encoder I/O — Line-Rate Closure and Deterministic Acquisition
Goal: convert external motion/scene events into repeatable line timing. Trigger defines when acquisition starts (frame/line start, exposure gate). Encoder defines how far the object moved between lines. The camera’s line generator turns both into line_valid and (for TDI) shift cadence.
Boundary: internal camera I/O conditioning and determinism only (no timing hub distribution systems).
Input hysteresis
Debounce / glitch filter
Programmable delay
Timestamp latch
Latency determinism
Long-cable SI
Ground bounce / CM noise
Trigger-in semantics: frame/line start and exposure gate
- Frame/Line start: defines the line sequence origin and counter reset points (where “missing line” becomes measurable).
- Exposure gate: defines the integration window; instability here shows up as brightness non-uniformity and banding-like patterns.
- Determinism requirement: the relevant metric is not average latency, but the distribution of trigger-to-sample delay.
Encoder A/B/Z: displacement quantization → line_valid generation
- A/B quadrature: provides direction and incremental displacement; quantization and edge integrity set the “granularity” of spatial sampling.
- Z index: anchors absolute alignment (useful for repeating scan windows). Keep it as a local reference point.
- Line_valid rule-of-thumb: generate each line when accumulated encoder counts cross a programmable threshold, then apply a controlled phase delay to align with exposure/sample.
Programmable delay & filtering: the trade-offs that matter
- Trigger-to-exposure delay: aligns sampling to mechanics; wrong values produce consistent position offset or repeating ghost-like edges.
- Strobe-to-sample alignment: ensures illumination and sampling overlap; treat it as a local timing relationship.
- Debounce/glitch filter: too weak → false triggers; too strong → missing short pulses at high line rates.
Key measurable indicators (evidence-first)
- Input hysteresis / threshold margin: immunity to small noise bursts on long cables.
- Debounce statistics: count filtered edges and rejected pulses to validate configuration.
- Timestamp latch: correlate trigger/encoder edges with internal line_start events.
- Latency determinism: log min/max/percentiles of trigger→line_start and encoder→line_valid timing.
Common pitfalls and signatures
- Ground bounce false edges: correlated with nearby load switching; trigger_count jumps without real motion.
- Long-cable reflections: double edges or ringing; problems appear only for certain cable lengths or terminations.
- Common-mode interference: A/B phase inconsistency and sporadic direction flips; artifacts worsen near high-power equipment.
Fast discriminator: If line_counter breaks continuity, the issue is upstream (trigger/encoder/line generator). If line_counter is continuous but the host misses data, the issue is downstream (buffer/link/host queue) — covered in H2-6.
H2-6. Data Path & Bandwidth — GigE/10GigE “Missing-Line Evidence” for Line-Scan
Key idea: average link bandwidth can look sufficient while burst behavior and buffer/queue limits still cause missing lines. The goal is to prove whether lines were lost before packetization (sensor/FPGA) or after (MAC/PHY/host).
Data rate estimation (universal template)
- Throughput template:
DataRate ≈ pixels_per_line × bits_per_pixel × line_rate × lanes/taps × (1 + overhead) - Overhead sources (line-scan relevant): headers, inter-packet gap, resend traffic, flow-control pauses, and burst packetization.
Why “bandwidth is enough” still fails: burst + buffering
- Burstiness: lines are packed into packets; packet timing (IPG, packet size) creates instantaneous peaks.
- DDR/FIFO limits: missing lines often coincide with
fifo_levelcrossing thresholds (overrun/underrun). - Host queueing: NIC/driver queue saturation can drop packets while the camera’s internal counters remain clean.
GigE/10GigE knobs that matter for line-scan (only)
- Packet size: efficiency vs latency/burst amplitude.
- Inter-packet gap (IPG): pacing control; too small can create bursts that overflow host queues.
- Resend: recovers loss but can create secondary bursts that look like random missing lines.
- Flow control: can prevent downstream collapse but may introduce pacing pauses that must be accounted for.
Evidence workflow: prove link-loss vs front-end line-loss
- Step 1 — FPGA line continuity: if
line_counteris not continuous, the loss happened upstream (trigger/encoder/TDI/readout). - Step 2 — Buffer health: correlate missing events with
fifo_level,overrun,underrun. - Step 3 — MAC/PHY integrity: rising
crc_errandlink_errsuggests physical margin / EMI / cable issues. - Step 4 — Host evidence:
rx_dropandqueue_depthspikes with clean camera counters indicate host-side packet loss.
Hard conclusion rules:
- FPGA line_counter breaks → not a network problem.
- FPGA line_counter continuous but host misses → not a sensor generation problem.
- crc_err + resend increase → physical link margin / interference likely.
- fifo overrun/underrun flags → burst/pacing/buffer strategy issue (even if average bandwidth is fine).
H2-7. Image Quality & Calibration — Black Level, FPN, Shading, and TDI Alignment Tables
Goal: convert fixed-pattern artifacts into measurable, repeatable calibration tables. Line-scan systems are especially sensitive to column-related errors and illumination geometry, so the workflow must be table-driven and regression-friendly.
Boundary: only calibration & coupling directly tied to line-scan acquisition (no deep ISP algorithm expansion).
Offset / Black table
DSNU / PRNU
Column FPN
Flat-field table
TDI align table
Speed bins
Temp drift table
Residual metrics
Black level and bias: black clamp + dark reference (measurable and regression-ready)
- Black clamp: stabilizes the low-frequency baseline so that downstream correction tables stay valid across time.
- Dark reference capture: collect a shuttered/blocked-light dataset to fit a repeatable offset map (per-column or per-pixel, depending on implementation).
- What matters: track offset mean/sigma and drift versus temperature and operating time to ensure the table remains valid.
DSNU/PRNU and column FPN: where vertical banding comes from
- DSNU (dark signal non-uniformity): appears as fixed texture in dark or low-light conditions; strongly linked to offset mismatch.
- PRNU (photo response non-uniformity): appears under uniform illumination; scales with signal level (gain mismatch).
- Column FPN (line-scan signature): repeated column patterns create vertical stripes; common contributors include column readout and per-column gain/offset mismatch.
Shading / flat-field: illumination geometry and telecentric imperfection
- Why it shows up: long-bar illumination and edge fall-off produce row-direction non-uniformity; optical geometry can amplify systematic gradients.
- Correction artifact: a flat-field (gain) table derived from uniform targets, stored with validity conditions (working distance / illumination mode).
- Regression check: compare edge-to-center residual after correction to catch slow drift and setup sensitivity.
TDI calibration (line-scan unique value): stage alignment + speed + temperature tables
- Stage alignment: align shift cadence so the same moving feature is integrated consistently across stages.
- Speed calibration: encoder scale and line period define the effective displacement per line; errors convert into blur/ghosting.
- Temperature drift tables: store best alignment parameters across temperature ranges to prevent gradual degradation.
- Speed bins: use segmented validity (low/nominal/high speed ranges) when a single table cannot cover the full operating span.
Calibration regression: keep tables traceable and comparable
- Minimal capture set: dark + uniform bright + edge target (or equivalent) to separate offset, gain, shading, and alignment effects.
- Residual metrics: column standard deviation, shading residual, and alignment score (edge sharpness / ghost energy proxy).
- Versioning: table versions must include conditions (temperature window, speed bin, illumination mode) for repeatable field analysis.
Fast discriminator: if artifacts stay fixed to the same columns across speeds, suspect column FPN / calibration tables. If artifacts worsen with speed bins or drift with temperature, suspect TDI alignment validity.
H2-8. Motion + Optics + Illumination — Coupling Constraints for Line-Scan Acquisition
Boundary reminder: only coupling constraints that directly affect line-scan capture. No lighting-driver circuits and no lens actuator control loops.
Speed ↔ Exposure
Strobe ↔ Line period
Beat-frequency banding
Telecentric constraint
Fast discriminators
Motion blur versus line exposure (engineering view)
- Blur grows with: higher speed and longer integration windows.
- Practical mitigation knobs: shorten exposure window, increase line rate, and reduce speed ripple.
- What to observe: if blur scales strongly with speed at fixed illumination, the limiting factor is likely exposure-time coupling.
Illumination synchronization: strobe alignment to line period
- Aligned case: each line’s sampling window overlaps the strobe pulse consistently → stable brightness and repeatable texture.
- Mismatched case: slight frequency/phase mismatch causes beat-frequency banding where stripes drift slowly over time.
- Evidence signature: band position drifts with time and changes when strobe/line settings change.
Optics constraint: telecentric as geometric consistency (high-level)
- Role: improves magnification stability and geometry consistency across the field, which stabilizes calibration validity.
- If imperfect: edge/center differences become harder to correct and can interact with shading/flat-field tables.
Fast discriminators (where to look first)
- Column-fixed stripes (not speed-dependent): suspect FPN / calibration tables (H2-7).
- Slowly drifting bands over time: suspect strobe–line beat mismatch (this chapter).
- Blur scales with speed/exposure: suspect motion–exposure coupling (this chapter).
H2-9. Power, Grounding & EMC for Line-Scan — Symptoms, Evidence, and First Measurements
Purpose: show how power/ground/EMC issues become line-scan-visible failures (random missing lines, FPN rise, false triggers) and what evidence proves each root cause.
Boundary: no PoE / isolation topology deep dive; focus on symptoms and evidence capture.
random missing lines
FPN rise
false trigger
ground bounce
I/O common-mode
shield / chassis
thermal drift
How supply noise shows up: drops, FPN inflation, and trigger mistakes
- Random missing lines: transient rail dips can break timing margins, buffer integrity, or SerDes stability, producing holes that appear “random”.
- FPN rises: noisy reference/ground can modulate offsets and column behavior, making fixed texture stronger and harder to correct.
- False triggers: noisy thresholds and unstable input reference can create extra edges, causing spurious line/frame starts.
Evidence chain A — “Random missing lines”
First 2 measurements: (1) FPGA/PHY core rail transient during burst traffic, (2) DDR/IO rail dip at the same moment a drop counter increments.
Discriminator: drop events that correlate with rail dips or brownout-like behavior point to power/return-path; drop events without rail movement push investigation to data path (H2-6).
First fix direction: improve transient margin and return path, reduce high di/dt loop area, isolate noisy loads from sensitive rails (conceptual guidance only).
Evidence chain B — “FPN / banding gets worse when the system is ‘busy’”
First 2 measurements: (1) ground bounce between analog reference and digital ground during high activity, (2) black-level residual (after correction) versus activity level.
Discriminator: if stripe strength changes with I/O/traffic state, suspect reference contamination and return-path coupling; if stripes are stable regardless of activity, suspect pure column mismatch and table limits (H2-7).
First fix direction: tighten reference routing and return paths, review shield/chassis bonding strategy, and limit common-mode injection at I/O boundaries.
Evidence chain C — “Trigger/encoder false edges”
First 2 measurements: (1) input waveform at the receiver pin (overshoot/reflection/common-mode), (2) input counters (debounce hits, glitch count, timestamp jitter).
Discriminator: failures tied to cable length, shielding, or ground reference indicate I/O coupling; failures tied to temperature or supply drift indicate threshold/rail instability.
First fix direction: stabilize input reference, enforce clean edge conditioning (hysteresis/debounce), and reduce long-line susceptibility (termination/shield reference).
I/O protection and long-line robustness (placement-level)
- ESD/TVS: placed at connector entry to clamp events before they reach sensitive input thresholds.
- Common-mode choke (CMC): placed on external differential lines to reduce common-mode injection that can corrupt reference and edges.
- Shield/chassis reference: define a stable return reference to avoid “floating shield” behavior that turns into antenna-like coupling.
Thermal drift: timing and offset drift that couples to calibration validity
- Sensor/FPGA temperature drift: can shift offsets and timing margins, changing banding and residual texture over temperature.
- Evidence signature: symptoms appear only after warm-up; calibration residuals (offset/shading) exceed limits at high temperature points.
- Engineering implication: temperature bins in calibration tables and drift tracking become part of the debug evidence set (no thermal hardware deep dive).
Fast triage: “drops + rail dip” → power/return-path first; “stripe strength changes with activity” → reference/ground coupling; “false triggers with long cables” → I/O common-mode and edge conditioning.
H2-10. Validation Plan — Make “Runs” Become Quantifiable and Reproducible
Deliverable style: checklist with observation points and pass/fail gates. The plan links tests to counters/metrics so failures map back to chapters.
line rate sweep
encoder emu
trigger stress
jitter injection
packet loss
temp regression
Group A — Line rate sweep and motion input robustness
- Test: sweep from low to max line rate; include speed bins relevant to TDI alignment.
- Observe:
line_counter,drop_counter,fifo_level_min/max, and alignment score proxy. - Pass: no missing lines; no FIFO underflow; banding metric stays under limit across the sweep.
Group B — Encoder emulation and trigger stress
- Test: emulate encoder A/B/Z patterns and stress trigger edges (edge rate, cable length variants, common-mode disturbance).
- Observe:
glitch_count,debounce_hits,timestamp_jitter, false start events. - Pass: zero false triggers in the defined stress window; jitter remains within deterministic bound.
Group C — Jitter injection (ref changes or perturbation)
- Test: swap reference sources or introduce controlled perturbation to expose banding sensitivity.
- Observe: banding metric, CRC error bursts, line-to-line phase error proxy.
- Pass: metrics stay below limits within the defined jitter budget; record the first fail point as the margin boundary.
Group D — Packet loss / throttling to validate resend and buffering
- Test: apply controlled loss or throttling to verify resend behavior and buffer robustness.
- Observe:
resend_count,rx_drop,crc_err,fifo_level, host NIC queue behavior. - Pass: system recovers without permanent holes; buffer never hits the floor; logging proves whether loss is link-side or front-end.
Temperature-point regression for calibration tables (DSNU/PRNU/flat-field/TDI)
- Test: capture dark/uniform targets at multiple temperature points across the operating range.
- Observe: residual metrics (
column_std,shading_resid,offset_drift, align score). - Pass: residual metrics stay within limits; otherwise add temp bins or adjust validity conditions and re-run.
Failure-to-chapter mapping: banding↑ → H2-4/H2-8; false trigger → H2-5/H2-9; holes/drops → H2-6/H2-9; residual FPN↑ → H2-7/H2-9.
H2-11. Field Debug Playbook — Symptom → Evidence → Isolate → First Fix
Use case: fast on-site isolation for line-scan failures with minimal tools. Every symptom follows the same 4-line SOP: Symptom → First 2 measurements → Discriminator → First fix.
Root-cause buckets: Clock / Trigger / Encoder / Data-path / Power & EMC.
Clock
Trigger
Encoder
Data-path
Power & EMC
SOP-1 — Periodic vertical banding (frequency-stable stripes)
Symptom: vertical stripes repeat at a stable spatial frequency; may change with line rate or temperature.
First 2 measurements:
- Scope point: probe REF_CLK or SENSOR_CLK quality (edge uncertainty/phase wander) and compare “good vs bad” conditions.
- Counter/log: record banding_metric (or per-column FFT peak) + crc_err bursts; log temperature at the same time.
Discriminator: if banding moves with clock source / jitter conditions, classify as Clock. If banding correlates with I/O activity or long cables, escalate to Power & EMC coupling.
First fix:
- Stabilize the sensor reference clock and reduce phase noise seen by the pixel/line clock domain.
- Use a jitter cleaner / clock generator with suitable RMS phase jitter for imaging clocks.
Example MPNs (Clock / Jitter Cleaner):
- Analog Devices AD9545 (multi-output clock generator / jitter cleaner class)
- Silicon Labs Si5341 / Si5345 (jitter attenuator class)
- Renesas 8A34001 (jitter attenuator / timing device class)
- Crystek CCHD-957 (low-phase-noise oscillator family example)
Selection depends on required output frequencies, jitter budget, and sensor clocking scheme.
SOP-2 — Random missing lines / holes (non-repeating gaps)
Symptom: random line gaps appear; gaps do not repeat at fixed positions; may worsen under higher bandwidth or higher temperature.
First 2 measurements:
- Scope point: probe FPGA_CORE rail or PHY_CORE rail during bursts; trigger on the moment drop_counter increments (if possible).
- Counter/log: compare drop_counter, fifo_floor, resend_count, rx_drop (host) in the same time window.
Discriminator: if fifo_floor hits near-zero before drops, classify as Data-path (buffer/packetization/host). If drops align with rail dips or brownout-like resets, classify as Power & EMC.
First fix:
- Data-path first: increase line buffering margin and tune packet parameters (packet size / inter-packet gap / resend strategy).
- Power first: reduce transient droop at the FPGA/PHY domain and improve return paths around high di/dt loops.
Example MPNs (DDR / Buffer / Ethernet):
- Micron MT40A512M16LY (DDR4 component example for buffering class)
- Intel 82599ES (10GbE controller family example on host/bridge side)
- Marvell 88X3310 (10GBASE-T PHY family example, if copper is used)
Exact PHY/DDR choice depends on interface type (SFP+/RJ45), FPGA, and thermal constraints.
SOP-3 — Stretch / scale distortion (geometry changes with speed)
Symptom: features appear stretched or compressed along motion direction; distortion changes with conveyor speed or encoder settings.
First 2 measurements:
- Scope point: probe encoder A/B at the receiver pin: duty, edge integrity, and phase stability under speed changes.
- Counter/log: log line_rate, encoder_count, line_per_mm (derived) and compare against a known calibration target.
Discriminator: if distortion tracks encoder quantization or missing pulses, classify as Encoder. If pulses are clean but line rate varies with trigger timing, classify as Trigger.
First fix:
- Fix encoder scaling: verify counts/mm, filter strategy, and “line-valid” generation.
- Improve edge conditioning and reduce long-line susceptibility (termination / hysteresis / shielding reference).
Example MPNs (Encoder / Receiver / Isolation):
- Broadcom HEDS-5500 (incremental encoder family example)
- Texas Instruments SN65HVD1781 (RS-485 transceiver example for industrial encoder transport class)
- Analog Devices ADuM1201 (digital isolator family example for noisy environments)
SOP-4 — Ghosting / double edges (motion-direction “repeat”)
Symptom: edges appear duplicated along motion direction; ghosting increases at certain speeds or after mechanical changes.
First 2 measurements:
- Scope point: check relative timing between ENCODER-derived line_valid and TDI shift (or line clock) for delay drift and jitter.
- Counter/log: log align_score (or correlation-based alignment metric), line_jitter, and speed estimate stability.
Discriminator: if ghosting peaks at specific speeds and alignment metric collapses, classify as Encoder or Clock (shift mismatch). If ghosting appears only with trigger gating, classify as Trigger.
First fix:
- Re-tune programmable delays (trigger-to-sample / encoder-to-shift) and lock the shift schedule to a stable reference.
- Re-run TDI alignment calibration across speed bins and temperature points.
Example MPNs (Programmable delay / Timing):
- Renesas 8T49N241 (programmable clock / delay device class example)
- Texas Instruments LMK04828 (clock distribution / jitter-cleaning class example)
SOP-5 — Worse after warm-up (temperature-dependent degradation)
Symptom: image quality or drops degrade after warm-up; banding, offset drift, or link errors appear only at higher temperature.
First 2 measurements:
- Scope point: repeat the same waveform captures at cold vs hot: REF_CLK integrity and key rails (FPGA_CORE, PHY_CORE).
- Counter/log: log banding_metric, drop_counter, and calibration residual (offset_resid, shading_resid) versus temperature.
Discriminator: if clock-related metrics drift first, classify as Clock. If rails lose margin and drops appear, classify as Power & EMC. If residuals exceed limits but rails/clocks are stable, classify as Calibration validity (H2-7 linkage).
First fix:
- Improve thermal stability of timing-critical blocks and update calibration tables with temperature bins.
- Verify airflow / heatsink contact for FPGA/PHY hot spots and re-check link stability at hot corners.
Example MPNs (Temp sensing / Fan control):
- TI TMP117 (high-accuracy temperature sensor example)
- Maxim/ADI MAX31760 (fan controller class example)
SOP-6 — False triggers / double line-start events
Symptom: unexpected extra line/frame starts; the issue correlates with cable length, nearby switching loads, or specific fixtures.
First 2 measurements:
- Scope point: capture TRIG_IN at the receiver pin: overshoot, ringing, reflections, and common-mode bounce.
- Counter/log: log glitch_count / debounce_hits / false_start timestamps and correlate with external events.
Discriminator: if waveform shows ringing/threshold crossings, classify as Trigger. If waveform is clean but false starts coincide with power noise, classify as Power & EMC.
First fix:
- Add edge conditioning (hysteresis / debounce), improve termination, and enforce a stable shield/chassis reference at the connector boundary.
- Upgrade ESD protection and reduce common-mode injection on long lines.
Example MPNs (ESD/TVS / CMC / Input conditioning):
- TI SN74LVC1G17 (Schmitt-trigger buffer example)
- ST ESDA25P35-1U1M (ESD protection example)
- TDK ACM2012-900-2P (common-mode choke example)
Minimum on-site kit: 200+ MHz oscilloscope, differential probe for rails/clock if available, known-good cable set, temperature readout, and access to counters/log export (drop/resend/glitch/fifo/banding/temp).
MPN note: The part numbers above are example BOM references to make the playbook actionable. For production selection, match interface type (CoaXPress/GigE), required clock jitter, temperature range, and EMC constraints.
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H2-12. FAQs (Accordion) — Evidence-first, Scope-locked
Each answer is evidence-driven: two measurements (one scope point + one counter/log), a clear discriminator, and a first fix that stays inside the camera-side chain (H2-1~H2-11).
Answer template used: Symptom → First 2 measurements → Discriminator → First fix.
Stripes appear only at certain line rates — is it jitter or strobe beat?
First 2 measurements: scope
REF_CLK/SENSOR_CLK edge stability and strobe-to-line alignment; log banding_metric vs line_rate.
Discriminator: if stripe frequency locks to strobe/line phase and disappears with strobe disabled, it is beat-coupling. If it persists across strobe settings but changes with clock source, it is clock jitter/phase noise.
First fix: re-phase strobe to line period, avoid near-harmonic ratios, and stabilize the sensor clock (lower jitter, cleaner PLL profile).
Bandwidth looks sufficient, but lines still drop — check sensor FIFO or network drop counters first?
First 2 measurements: log camera-side
fifo_floor/buffer_level and link-side drop_counter/resend_count; scope the DDR/FPGA burst activity if available.
Discriminator: if fifo_floor hits near-zero before drops, it is internal underrun (front-end pacing). If FIFO stays healthy while drop_counter/resend spikes, it is packet loss / host/NIC queue behavior.
First fix: increase buffering margin, tune packet size and inter-packet gap, and validate resend behavior under burst load.
After changing the mounting position, images stretch — encoder quantization or trigger reflections?
First 2 measurements: scope encoder
A/B edges at the receiver pin (missing pulses, duty/phase), and scope TRIG_IN for ringing; log encoder_count and derived line_per_mm.
Discriminator: if counts/mm drifts or pulses disappear at speed, it is encoder quantization/transport. If encoder is clean but glitch_count rises with cable length, it is trigger integrity/reflection.
First fix: re-calibrate counts/mm, tighten input conditioning (hysteresis/debounce), and fix termination/shield reference on long I/O lines.
FPN grows after warm-up — black-level drift or clock phase noise?
First 2 measurements: capture a dark reference (lens covered) and a flat-field at cold/hot; log
offset_resid/DSNU and banding_metric vs temperature.
Discriminator: if dark frames show offset shifts and column patterns without strong periodicity, it is black-level/offset drift (cal table validity). If a stable-frequency band appears and tracks clock conditions, it is clock phase noise coupling.
First fix: add temperature-binned offset tables and reduce clock jitter/PLL spurs seen by the readout timing.
2D-TDI looks blurrier than expected — how to prove speed mismatch with evidence?
First 2 measurements: log
align_score (correlation-based alignment metric) and speed stability derived from encoder; scope the phase between line_valid and TDI shift/line clock.
Discriminator: if align_score collapses at specific speed bins while encoder-derived speed jitters, the shift-to-motion match is broken (encoder/line generator). If speed is stable but shift phase wanders with clock conditions, clock jitter dominates.
First fix: tighten encoder filtering and re-tune programmable delays; re-run TDI alignment calibration across speed and temperature bins.
Random holes happen only when nearby motors/drivers switch — network issue or power/EMC coupling?
First 2 measurements: scope
FPGA_CORE/PHY_CORE rail for dips/bounce during switching events; log drop_counter, glitch_count, and timestamp correlation to external switching.
Discriminator: if drops align with rail dips or trigger glitches, it is power/EMC injection. If rails and trigger are clean but resend_count spikes with traffic bursts, it is data-path/host behavior.
First fix: improve return paths and shielding reference, reduce common-mode injection on long cables, then re-test packet loss with controlled traffic.
Resend spikes on the host, but the camera shows no internal drops — what proves host-side loss?
First 2 measurements: compare camera counters
drop_counter/fifo_floor to host NIC stats (rx_drop, ring overflow) within the same time window; scope link activity only if needed.
Discriminator: if camera FIFO never under-runs and camera drop counters stay flat while host rx_drop increases, loss is host/NIC/driver queue. If both sides show FIFO starvation, camera buffering/packet pacing is insufficient.
First fix: tune packet size/jumbo frames, increase host ring buffers, and adjust inter-packet gap to reduce burst pressure.
Banding pitch stays constant even when speed changes — clock spur or illumination effect?
First 2 measurements: log
banding_metric + spatial FFT peak position while sweeping line rate; scope the reference clock for spur-like modulation and compare across clock sources.
Discriminator: if banding pitch is invariant to speed and follows a stable spur signature that changes with clock source/PLL settings, it is clock spurs. If it shifts with strobe phase or disappears without strobe, it is illumination beat-coupling.
First fix: remove spur sources in PLL configuration, improve reference clock quality, and avoid strobe/line ratios that create beating.
Flat-field correction is applied, but vertical stripes remain — column FPN or shading/optics?
First 2 measurements: capture dark frames and uniform flat frames; log
DSNU/PRNU and per-column residual after correction.
Discriminator: if stripes persist in dark frames, it is column FPN/offset mismatch (sensor/readout). If stripes appear mainly in flat frames and vary with illumination geometry, it is shading/optics coupling (non-uniform illumination / telecentric limits).
First fix: refresh per-column offset/gain tables and validate flat-field targets and illumination stability across temperature and line rate.
Trigger occasionally double-fires on long cables — what is the fastest proof and fix?
First 2 measurements: scope
TRIG_IN at the receiver pin for overshoot/ringing crossing the threshold; log glitch_count/false_start timestamps.
Discriminator: if the scope shows ringing that re-crosses the threshold, it is reflection/termination. If waveform is clean but glitches correlate with switching noise, it is common-mode injection / grounding.
First fix: add termination and hysteresis/debounce, enforce a stable shield/chassis reference at the connector boundary, then re-verify with stress toggling.
Ghosting is worst at specific speeds — encoder quantization or clock jitter?
First 2 measurements: log
align_score vs speed bins and encoder-derived speed jitter; scope encoder A/B and line shift timing for phase drift at those speeds.
Discriminator: if ghosting peaks coincide with speed quantization bins or missing pulses, it is encoder quantization/transport. If encoder is clean but phase drift changes with clock source/PLL profile, it is clock jitter/phase noise.
First fix: increase encoder resolution or improve transport robustness, and lock shift timing to a cleaner reference with tighter jitter budget.
The link is stable at low line rates but fails at maximum throughput — buffer margin or thermal corner?
First 2 measurements: sweep line rate and log
fifo_floor, drop_counter, resend_count plus temperature; scope rails at peak throughput to detect droop under bursts.
Discriminator: if failures appear immediately at peak rate with fifo_floor collapsing, it is buffer/pacing. If it runs initially but fails after warm-up and rails/PHY errors grow, it is thermal/power margin.
First fix: increase buffering and tune packet pacing, then verify hot-corner stability with temperature-soaked validation.
