Why this chapter exists

A SWIR/InGaAs front-end is accepted by engineering evidence: repeatable noise floor, predictable drift, stable temperature control, and a clean digital boundary that downstream blocks can trust. “Looks good” is not a requirement; measurable KPIs are.

Acceptance KPIs (what must be measured)

Use these KPIs as the page-wide checklist. Each KPI must map to a test condition, an observable signal, and a pass/fail rule.

A practical rule: if a KPI cannot be tied to one waveform or one statistics plot, it is not ready for acceptance.

Minimum evidence per KPI (condition → measurement → discriminator)

The page later expands on “how to fix,” but acceptance starts with “how to prove.”

Fastest two measurements (first response debug)

• TP1: Bias/Reference integrity — measure ripple, spikes, and slow wander on the critical analog bias/ref rail(s).
• TP2: Dark baseline stability — capture dark codes and track mean + σ over time and temperature setpoints.

Quick discriminator logic: rail ripple ↔ banding suggests power/return coupling; baseline step ↔ TEC PWM suggests cooler-drive injection; baseline slope ↔ temperature suggests dark current + thermal gradient.

Figure F1 — Front-end boundary & evidence hooks

Engineering translation: physics → constraints → symptoms

InGaAs SWIR arrays are often limited by dark current, leakage sensitivity, and temperature-driven baseline motion. These are not “nice-to-have” considerations; they directly shape ROIC topology, bias strategy, and the need for stable cooling.

Pixel equivalent model (what the ROIC actually sees)

The front-end input node is a sensitive summing junction. Small leakage currents or surface contamination can look like signal, and pixel capacitance sets the kTC floor and integration behavior.

• Iph: photo-generated current (useful signal)
• Idark: dark current (temperature-sensitive baseline lift)
• Cpd: pixel/input capacitance (integration slope and kTC noise)
• Rsh: shunt/leakage path (humidity/contamination/ESD device leakage can reduce effective Rsh)

Temperature sensitivity: why “baseline” becomes the main enemy

As temperature rises, Idark typically increases rapidly (often perceived as a near-exponential trend on a linear plot). Two practical consequences dominate front-end work:

• Noise floor lifts because dark-related shot components increase with baseline current.
• Non-uniformity worsens when temperature gradients exist (local baseline differences across the array).

Practical acceptance framing: a stable thermal setpoint is not only about “cooler performance” — it is about keeping baseline + noise statistics inside a repeatable envelope.

Leakage sensitivity: invisible paths that behave like “ghost signal”

The sensitive node can be corrupted by leakage paths that change with humidity, surface films, bias voltage, or temperature. Leakage often presents as slow drift, corner anomalies, or “sparkle” pixels that do not correlate with illumination.

Design actions forced by detector realities (bridge to next chapters)

• Dark current & temperature → requires TEC loop design, sensor placement discipline, and stability proof.
• Cpd & kTC → requires appropriate ROIC readout (CTIA/TIA/integrator) and CDS-compatible sampling.
• Leakage & Rsh → requires guarding, cleanliness, humidity strategy, and bias network discipline.

The next chapters will formalize a noise budget and show how each circuit choice reduces a specific term on that budget.

Figure F2 — InGaAs pixel equivalent model (sensitive node)

Goal: a “noise ledger” that justifies every design choice

A SWIR/InGaAs front-end must treat noise as a ledger: each term has a source, an injection point, a suppression knob, and a measurement method. Without this ledger, improvements are not repeatable and root-cause isolation becomes guesswork.

Engineering grouping: which knob suppresses which term

Noise ledger (source → suppression → how to measure → fingerprint)

Use this as a fixed “acceptance table header.” Each row must be tied to at least one observable waveform or statistics plot.

Practical separation rules: temperature correlation → dark-dominated; phase correlation → reset/CDS/clock coupling; banding at switch freq → reference/power injection.

Figure F3 — Noise flow map (sources → injection → suppression hooks → SNR/DR)

What this chapter decides

Readout topology determines how the sensitive node behaves, how linear the current-to-code transfer is, and how well CDS and reset strategies can suppress kTC/1/f terms from the noise ledger.

CTIA (capacitive feedback amplifier)

• Advantage: strong input node control, good linearity for charge integration, CDS-friendly behavior.
• Cost: requires stable amplifier behavior and well-defined feedback capacitor; dynamic range ties to Cf and swing.
• Best fit: low current / high sensitivity regimes where node stability and linearity are critical.
• Common pitfall: reset feedthrough or sampling phase errors appear as repeatable offsets/ghost patterns.

Noise-ledger link: CTIA choices usually target kTC/reset artifacts and linearity control while keeping CDS effective.

TIA (resistive/active transimpedance)

• Advantage: direct current-to-voltage conversion, bandwidth-friendly for faster readout needs.
• Cost: input stability depends on loop gain and parasitics; more sensitive to coupling and reference/clock injection.
• Best fit: scenarios that prioritize bandwidth or require continuous conversion behavior.
• Common pitfall: oscillation/peaking or coupling shows up as deterministic banding or frequency-linked patterns.

Noise-ledger link: TIA decisions often trade bandwidth against coupling sensitivity; reference/clock integrity becomes mandatory.

Integrator (switched integration / sample-and-hold readout)

• Advantage: integrates small currents naturally; can improve effective SNR by extending integration time.
• Cost: highly sensitive to leakage paths and drift; reset and CDS timing must be disciplined.
• Best fit: ultra-low signal regimes where integration time is the main lever.
• Common pitfall: slow baseline motion (leakage/drift) dominates after longer integration, masking improvements.

Noise-ledger link: integrator choices amplify the need to control leakage and drift before expecting gains from longer Tint.

Selection rules (text decision tree)

• If low-light performance is limited by kTC/reset artifacts → prioritize topologies with robust CDS compatibility (often CTIA-style behavior).
• If requirements push for higher bandwidth/frame margin → consider bandwidth-friendly paths (often TIA-style), but treat coupling control as a first-class constraint.
• If the dominant lever is longer integration time → integrator-style readout can help, but only after leakage/drift controls are proven.
• If anomalies shift with sampling phase → suspect reset/CDS timing, not illumination or “random noise.”

Figure F4 — Topology comparison (same template, three columns)

Why SWIR front-ends fail “silently”

In SWIR/InGaAs readout, the most damaging errors often come from invisible leakage currents rather than incorrect calculations. When the input node is high-impedance and the signal current is small, leakage can masquerade as dark current, baseline drift, or slow “ghost” motion that looks like sensor behavior but is actually board-level physics.

Six leakage classes (path → trigger → symptom)

• Surface residue (flux/cleaning): leakage grows with humidity and can change after handling. Symptom: drift improves after drying or cleaning.
• Connector/line leakage: motion/pressure changes the baseline. Symptom: touching or re-seating cables shifts offsets.
• Protection leakage (ESD/TVS): temperature-dependent leakage. Symptom: worse at higher temperature, often slow recovery.
• Bias networks: high impedance resistors create a leakage amplifier. Symptom: baseline changes strongly with bias voltage.
• Humidity film: thin water layer forms a resistive path. Symptom: “good in lab, bad in rainy season.”
• Guard discontinuity: guard exists but is ineffective. Symptom: local region behaves like a leakage antenna.

Fast discriminators (evidence fingerprints)

Mitigation blocks: Guard ring drive + Clean/Conformal/Sealing

A guard ring is not “a ring of copper.” It is a driven or referenced shield that reduces the surface potential difference around the sensitive node, lowering the leakage driving force. Any discontinuity or wrong reference makes the guard ineffective.

• Guard continuity: avoid breaks, vias-to-nowhere, and unguarded “gaps” around the node.
• Guard reference: keep guard potential close to the sensitive node potential (minimize ΔV on the surface).
• Clean / conformal / sealing: remove ionic residue, prevent moisture films, and isolate connector leakage points.

Verification must be paired with the same drift test: dark baseline vs time, plus humidity/bias/temperature sensitivity checks.

Figure F5 — Leakage path map (center node → 6 arrows → 2 countermeasures)

Front-end boundary: ADC is part of the noise ledger

ADC selection is not only a datasheet choice. In SWIR readout, ADC and sampling define how well CDS works, whether quantization becomes visible at low signal, and whether deterministic artifacts appear when clock/reference integrity is insufficient.

ADC families (front-end view)

• SAR: clear sampling moments and throughput-friendly conversion; requires disciplined reference and sampling integrity.
• ΣΔ: strong low-frequency resolution behavior; tradeoffs include bandwidth and latency envelopes that must fit the readout schedule.
• Column-parallel: short analog path and massive parallelism; requires careful column-to-column consistency verification.

Practical rule: if “code granularity” is visible at low signal, quantization/ENOB is too close to the noise floor or full-scale mapping is inefficient.

On-ROIC column ADC vs off-chip ADC (when each becomes rational)

ENOB vs bandwidth: what “enough bits” means in SWIR

“Enough” effective bits means the quantization term stays below the target noise floor with margin. If low-signal histograms show step-like granularity, or if σ stops improving as expected while the analog chain is stable, quantization or code-domain artifacts may be dominating.

Evidence approach: compare (a) σ vs integration time and (b) histogram smoothness at low signal. Quantization dominance leaves persistent code steps even when temperature and leakage controls are proven.

Sampling + CDS timing: where artifacts enter

SWIR readout commonly uses paired samples to suppress reset and low-frequency components. Sampling must be treated as part of the analog chain: sample phase and hold behavior can turn into deterministic patterns if clock edges or reference integrity inject energy into the sampling moment.

• Reset → Integrate: defines charge accumulation window.
• Sample1: captures baseline reference condition.
• Sample2 (CDS): captures signal condition; subtraction suppresses kTC and low-frequency components when timing is consistent.
• Convert: conversion must preserve the paired-sample intent (avoid coupling at conversion edges).

Figure F6 — Sampling timeline + ADC location options (clock cleanliness highlighted)

What power noise becomes inside a SWIR front-end

In a SWIR/InGaAs chain, power and reference issues rarely appear as “random noise only.” They can translate into false signal (baseline shift), slow drift (offset/gain walk), and deterministic stripes (row/column-correlated artifacts).

Three coupling channels to watch (front-end boundary)

• Bias coupling: ripple on analog bias rails can modulate the sensitive node and show up as baseline wobble or pattern noise.
• Reference coupling: Vref drift maps directly into code space; even a stable ROIC output can look like “gain change.”
• Return coupling: shared impedance between analog and digital returns can inject switching currents into sampling moments.

Minimum probing: the first two measurements

Optional tie-breakers when ambiguity remains: ADC Vref node (to confirm code-domain drift) and AGND↔DGND delta near the single-point connection (to expose return coupling).

Correlation criteria (fast discriminators)

• Ripple frequency ↔ stripe signature: if stripe strength changes when a ripple tone changes, the coupling is power-related.
• Temperature ↔ bias drift: if baseline drift tracks bias voltage drift across temperature, the bias/reference chain is dominant.
• Load state ↔ baseline jump: if enabling a load (digital burst, TEC PWM state) causes synchronous baseline steps, suspect return coupling.

Stabilization priorities (repair order)

Fixes should follow the coupling path hierarchy. Start with the simplest local corrections and validate with the same two-probe evidence: bias rail ripple and ROIC baseline stability.

• Local decoupling / filtering at the bias injection point (minimize impedance where the sensitive block draws current).
• Return discipline: keep analog return clean; enforce single-point tie between AGND and DGND where intended.
• Reference isolation: treat Vref as a precision signal (buffering/RC isolation as appropriate, and verify drift behavior).

Figure F7 — Power & reference coupling paths (bias, Vref, and returns)

Why TEC drive is a top contamination source

TEC/Peltier control is a high-current power stage. Its switching edges and return currents can inject energy into the SWIR front-end as ripple, ground bounce, and near-field coupling. The result is often deterministic artifacts rather than random noise.

TEC stage options (risk-focused view)

• PWM H-bridge: supports bidirectional heat pumping; risk centers on large switching loops and return complexity.
• Synchronous buck (single-direction): simpler current path; risk centers on ripple tones and shared impedance into sensitive returns.

The front-end question is not the controller brand. It is whether switching energy finds a clean exit path without sharing impedance with analog bias and reference nodes.

Switching frequency selection (principles that prevent visible artifacts)

Isolation essentials (layout & returns)

• Separate return: TEC high-current return must not share impedance with ROIC analog return.
• Loop area minimization: reduce magnetic coupling from inductor and switching loops into sensitive traces.
• Switch node distance: keep dv/dt nodes physically away from the ROIC input neighborhood and Vref routing.

Filtering & shielding blocks (where they matter)

• LC filter: place and tune to reduce the ripple component that correlates with artifacts (verify by frequency correlation).
• Shielding: treat the power inductor/switch loop as a field source; reduce coupling into the ROIC/ADC region.

Any mitigation should be validated by repeating the same minimal probes: (1) TEC rail ripple / PWM signature and (2) ROIC baseline or artifact metric.

Figure F8 — TEC drive & isolation map (risk arrows + countermeasures)

What “temperature control pass” means in a SWIR front-end

Temperature control is a closed-loop system: sensor placement, thermal lag, controller behavior, and plant dynamics together decide whether the detector stays stable. A stable setpoint alone is not sufficient; acceptance must be based on measurable loop behavior and repeatable evidence.

Front-end linkage: temperature ripple and drift typically map into dark current behavior and baseline stability. Verification should correlate temperature evidence with a stable dark baseline statistic where applicable.

Sensor placement: 3 rules that prevent “measuring the wrong temperature”

• Close to the controlled object: place the sensor on the cold plate / near the detector thermal path, not near switching heat sources.
• Minimize thermal lag: keep the heat path to the sensor predictable (controlled contact, controlled interface material).
• Make placement repeatable: define position, pressure, and attachment process so the loop behaves similarly across builds.

Thermal lag & hidden instability traps

The thermal plant has inertia and delay. If the sensed temperature lags the actual detector temperature, the controller can over-correct. Saturation (current limit / PWM limit) can also accumulate integral action and later release it as overshoot.

• Lag-driven oscillation: delayed feedback makes corrective action arrive late, creating repeated over/under correction.
• Integrator windup: output saturation hides error, integral term grows, then causes overshoot when saturation clears.
• Placement mismatch: sensor reads a local hot/cold spot instead of the detector thermal state.

How to prove loop stability (evidence template)

Practical discriminator: change sensor placement A↔B or adjust the plant boundary condition and verify whether the stability evidence remains consistent. A robust loop should not be “stable only in one mounting configuration.”

Figure F9 — Thermal plant + sensor placement + PID loop (with acceptance bubbles)

Why dew and packaging issues look like “mysterious image failure”

SWIR systems often operate with a cold plate and a window close to the cold region. When the window or internal surfaces fall below the dew point, condensation can form as a thin film, causing rapid contrast loss and scattering. Packaging and contamination can also create slow drift and recurring defects that resemble electronics problems.

Dew risk logic (dew point and temperature margin)

• Core condition: if window/cold-surface temperature drops below the dew point, condensation risk is active.
• Margin mindset: evaluate how far the window temperature is from the dew point (“temperature margin”).
• Evidence capture: log ambient conditions plus window/cold-plate temperature during failure reproduction.

Anti-dew countermeasures (what they solve and what they trade)

Contamination and “invisible” window issues

Not all field failures are liquid droplets. Window haze, molecular contamination, and cold-surface deposition can build up slowly and show up as persistent contrast loss or changing fixed-pattern behavior. These issues often improve temporarily after cleaning, which is a strong diagnostic clue.

• Clue: slow degradation over days/weeks, sensitive to cleaning or enclosure opening.
• Action boundary: focus on sealing, clean handling, and internal humidity control mechanisms.

Environmental edge cases: drift and defect recurrence

Thermal cycling and mechanical stress can shift alignment and contact conditions, creating repeatable drift signatures and defect recurrence. Validation should include temperature transitions and dark statistics checks to separate “environmental drift” from pure electronics noise.

Figure F10 — Dew risk and countermeasure blocks (window, cold plate, humidity)

Boundary definition: what this page covers (and what it does not)

This chapter defines the calibration / NUC data assets the front-end must support at the hardware/firmware boundary: what must be captured, stored, versioned, and proven in validation. It does not describe ISP math or NUC algorithm internals.

Minimum dataset: what must be stored (deliverables)

• Dark offset: stabilizes baseline and prevents “false signal” under dark conditions.
• Gain map: reduces fixed-pattern brightness differences across pixels/columns at a defined operating mode.
• Temp-drift table: maintains calibration validity across cold-start and ambient shifts without requiring algorithm detail here.
• Bad pixel map: provides a controlled defect list with traceable lifecycle (generated/updated/expired).

Optional extension (still boundary-safe): multiple calibration sets keyed by integration time / gain mode / readout mode, each with a dataset ID.

Data must be structured (header + payload), not “loose files”

The most common calibration failure mode is not “bad math,” but using the wrong dataset under the right-looking conditions. The boundary should define a rigid dataset structure.

Mode keys should include only what the front-end truly controls (example: gain mode, integration time, readout mode). Avoid embedding ISP-only concepts here.

Temperature drift table: why the boundary must support it

SWIR/InGaAs behavior is temperature sensitive. Even with a stable setpoint, the system experiences cold-start transients, mounting variation, and environmental disturbances. The boundary must therefore support:

• Temperature readout used as a key (sensor location and meaning must be defined).
• Lookup behavior (select a drift table entry or bracket range).
• Correction hook (apply a pre-defined drift adjustment block without specifying ISP math).

Proof target: drift behavior vs temperature should remain bounded when the correct table is applied, and should degrade predictably when mismatched.

Bad pixel map lifecycle: versioning is part of the deliverable

• Generation event: factory calibration, rework, or controlled service procedure.
• Update trigger: after thermal cycling, long runtime, or controlled self-check (policy-defined).
• Version meaning: the same sensor SN can legitimately have multiple bad-pixel map versions over time.

Traceability block: minimum fields that must be stored and readable

Practical requirement: field logs must be able to answer “which dataset was used” without inference.

Evidence: what must be proven (proof, not promise)

• Dark repeatability: dark baseline statistic remains stable after applying the correct offset dataset.
• Temperature sweep: drift remains bounded across the defined temperature range when using the drift table.
• Version replay: loading a prior dataset version reproduces expected behavior (traceability works).
• NVM integrity: CRC/consistency checks pass across power cycles and controlled brownout scenarios.

Concrete MPN examples (calibration storage + temperature readout)

The part numbers below are examples commonly used for calibration dataset storage and temperature measurement. Selection should follow capacity, endurance, operating temperature grade, and interface availability.

Figure F11 — Calibration dataset flow (capture → store → runtime lookup)