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Machine-Vision Interfaces: CoaXPress, 10GigE, USB3, MIPI, SLVS-EC

Machine-Vision Interfaces: CoaXPress, 10GigE, USB3, MIPI, SLVS-EC

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Machine-vision interface “determinism” is earned by controlling three things: recovered/reference clocks, lane alignment/deskew, and every hidden buffer that can add variable latency. The fastest path to stable links is evidence-based: correlate PHY counters with clock/trigger waveforms and EMC events, then apply the smallest first fix (cabling/EQ, refclk cleanup, trigger hardening, or low-parasitic protection) and re-verify with the same metrics.

H2-1. Interface landscape: where determinism really comes from

Determinism is not a protocol slogan; it is the ability to keep latency, alignment, and timing predictable under real noise. Across CoaXPress, 10GigE, USB3, MIPI CSI-2, and SLVS-EC, determinism is governed by three engineering enemies: clock domain behavior, lane timing, and hidden buffers.

Determinism “3-enemy model” (engineering consequences)

  • Clock domain (Refclk vs CDR): recovered clocks can lose lock or wander; refclks can inject jitter via supply/ground noise. Both can turn a “stable link” into a “random-event link”.
  • Lane timing (bonding/deskew): multi-lane transports rely on skew tolerance. Temperature drift, connector wear, and crosstalk can push a marginal system over the deskew cliff.
  • Hidden buffers (variable latency zones): any queue/FIFO/host scheduler/switch can convert fixed delay into variable delay, even when the physical channel is clean.

Controlled vs uncontrollable points (what can be engineered vs what must be mitigated)

Controlled points (typical):
  • PHY/SerDes margin controls (EQ settings, retimer/redriver placement, refclk quality, impedance/return path).
  • Lane integrity controls (skew management, connector/cable QA, layout symmetry for short-board links).
  • Trigger integrity controls (threshold stability, isolation, edge conditioning, receiver-side capture).
Uncontrollable points (typical):
  • USB host scheduling and OS-level buffering variability (shows up as bursty latency even when the cable is fine).
  • Ethernet queueing through switches/routers, mixed traffic, PAUSE/backpressure behaviors (variable delay segments).
  • Environmental coupling (ground potential differences, EMI bursts, connector micro-motion) that changes channel behavior in the field.

Determinism scorecard (risk checklist, not parameter trivia)

Use the scorecard below to choose an interface based on risk surfaces and diagnosability. Each cell indicates what tends to break first and what evidence is easiest to obtain.

Interface family Where determinism is strong Typical uncontrollable variability Best evidence to log
CoaXPress (CXP) Point-to-point transport and clear physical boundary; timing can be engineered around stable CDR behavior and clean cabling. Channel loss/connector aging causing margin collapse; CDR lock events (if retimed segments exist). Link errors vs temperature/cable stress; retrain/lock events; CRC/stream error counters.
10GigE / GigE Vision Robust ecosystem and diagnostics; transport works well when bandwidth and queueing are constrained. Switch queueing and mixed-traffic congestion creating variable delay zones. Packet/CRC statistics, PHY error counters, drop/retransmit indicators, correlation to network topology changes.
USB3 Vision High throughput over short links; physical layer can be solid with good cable/connector control. Host scheduling and buffering variability; port-to-port behavior differences. Link state/error/retry metrics (where available), negotiated speed stability, dropouts correlated to host load.
MIPI CSI-2 Short-board determinism with controllable layout and clocking; predictable when lane timing is kept inside margin. Deskew sensitivity to skew/crosstalk/jitter; temperature drift pushing lanes over threshold. Lane error/deskew events, refclk jitter checks, failure rate vs temperature and data rate.
SLVS-EC Deterministic high-speed multi-lane transport when lane bonding and clocking are engineered tightly. Multi-lane consistency sensitivity (skew, connector/cable variance, supply noise into PHY). Deskew/bonding failure counts, error bursts vs EMI events, margin vs cable length/temperature sweep.
Practical rule: if the application requires repeatable trigger-to-frame alignment, prioritize designs that keep variable latency zones out of the critical timing path, or force determinism using timestamps + calibration at known points.
F1 — Interface Determinism Map Clock / Lane / Buffer risk markers and trigger side-path Sensor Pixel Source Serializer / PHY SerDes + EQ Medium Coax / UTP / Cable Receiver PHY CDR + Deskew Bridge / FIFO PCS / Buffers Host Scheduler / Stack CLOCK LANE BUFFER variable latency variable latency Trigger / Genlock Timing Side-Path Families (engineering view) CoaXPress 10GigE USB3 Vision MIPI CSI-2 SLVS-EC
Cite this figure — Figure F1 (Interface Determinism Map). Suggested caption: “Link determinism is governed by clock behavior, lane alignment, and hidden buffers; trigger/genlock must avoid variable-latency zones.”

H2-2. SerDes margin: eye/BER/EQ and why it fails only in one factory

“Works in the lab, fails in the factory” usually means the link is operating near a margin edge. The fix starts by turning vague symptoms into measurable evidence: error shape (random vs burst), margin controls (EQ/CDR), and correlation to environment (EMI, ground return, temperature, cable motion).

Evidence taxonomy: what each metric is really telling

  • BER / PRBS failures: indicates the physical channel is losing symbols. Slow drift with temperature often signals shrinking eye margin.
  • CRC errors: shows the stream is corrupted at the data layer. A low, steady CRC rate behaves like random noise; sharp spikes behave like burst interference.
  • FEC corrected vs uncorrected: “corrected rising” means margin is thinning but still recoverable; “uncorrected rising” means the system has crossed a cliff.
  • Retrain / deskew / lock events: not a bit-error symptom—this is link structure instability (clock recovery or lane alignment failing).
Discriminator (fast): if errors arrive in bursts aligned to switching events (motors/VFD, strobes, relay clicks), suspect common-mode injection / return-path discontinuity. If errors rise smoothly with temperature or cable loss, suspect eye margin thinning.

EQ knobs that actually move the needle (and their failure modes)

  • TX pre-emphasis / de-emphasis: compensates channel loss but can amplify reflections when connectors/cables are marginal.
  • RX CTLE: boosts high-frequency content; too aggressive settings can pull in noise and reduce timing margin.
  • RX DFE: corrects ISI but can become unstable if the channel changes with temperature or if burst interference dominates.
  • CDR bandwidth: too narrow risks lock sensitivity; too wide can pass jitter/noise through. Stability is validated by lock events + error counters, not by “it seems fine”.

First 2 measurements (locked, repeatable)

Measurement #1 — Counters + operating-condition log (time correlation):
  • Log: CRC, FEC corrected/uncorrected (if present), retrain/deskew failures, and any CDR lock events, alongside temperature and a simple “EMI stress marker” (motor start / relay click / strobe on).
  • Read the shape: spikes imply burst coupling; slow ramps imply margin shrink (loss, temperature, refclk jitter, connector aging).
Measurement #2 — Margin probing (prefer PRBS/loopback, otherwise rate-vs-errors sweep):
  • If PRBS/loopback exists: sweep EQ presets and capture the stable region (settings that keep errors flat across temperature and cable stress).
  • If eye sampling exists: compare margin before/after protection parts or cable changes; record which change shifts the eye boundary.
  • If neither exists: sweep data rate and cable length and plot errors vs rate; a “cliff” behavior identifies where margin collapses.

First-fix ladder (from cheapest to structural)

  1. Confirm a margin cliff: reduce data rate / swap cable / shorten path; if the problem disappears, the issue is margin-based, not “random software”.
  2. Tune EQ safely: change TX pre-emphasis and RX CTLE/DFE in small steps and verify with counters; avoid “max EQ” as a permanent fix without stability logs.
  3. Attack common-mode + return path: validate shield termination continuity, connector bond, and differential pair return path; look for burst correlation to EMI.
  4. Check clock integrity: verify refclk jitter at the PHY/retimer pins (or correlate lock events with supply noise/temperature).
  5. Escalate topology: add redriver/retimer only after the error shape is understood; otherwise a middle box can hide the symptom while worsening timing predictability.
F2 — SerDes Margin Toolbox Knobs + counters to turn “field mystery” into measurable margin TX Pre-emphasis / Swing pre-emph swing CHANNEL Cable / Connector / PCB insertion loss reflection step crosstalk common-mode EMI bursts motors / VFD / relays RX CTLE / DFE / CDR CTLE DFE CDR bandwidth Counters / Logs BER FEC CRC retrain / lock Error shape discriminator random errors margin thinning burst errors common-mode / return path
Cite this figure — Figure F2 (SerDes Margin Toolbox). Suggested caption: “Use EQ knobs (TX/RX) and counters (BER/FEC/CRC/retrain) to separate random margin loss from burst interference driven by common-mode injection.”

H2-3. Retimer vs redriver: cleaning jitter without breaking latency expectations

A stable link is not only about passing bits. Interface determinism depends on whether the chain preserves latency semantics (fixed or calibratable) while maintaining sufficient SerDes margin. Retimers (with CDR) can recover eye margin by re-clocking, but may introduce state-dependent behavior such as lock/relock and holdover. Redrivers strengthen amplitude/EQ without re-timing, helping reach longer channels while keeping timing expectations closer to the original path.

What changes when a retimer is inserted (CDR state is part of the system)

  • Lock → stable phase relationship: when locked, output timing follows the recovered clock model and remains predictable within margin.
  • Relock → phase/latency step: when the CDR loses lock and reacquires, the output phase can shift. This can appear as a “rare timing jump”.
  • Holdover / free-run → timing semantics change: during input disturbance, the retimer may maintain output using internal reference behavior, breaking assumptions about input-output timing.
  • Elastic buffering risk: some implementations add buffering to absorb rate differences, turning a fixed delay into a piecewise variable delay segment.

Retimer (with CDR)

Improves eye opening by re-clocking, filters certain jitter components, and can extend reach. Must be validated for lock stability and delay behavior under temperature and EMI events.

Redriver (EQ / gain)

Boosts amplitude and equalizes loss without re-timing. Preserves timing semantics better but does not remove jitter originating upstream. Best when the main problem is loss/reflection, not clock instability.

Where re-timing must be treated as “high risk”

Do not treat re-timing as a default fix when the application relies on tight timing semantics, such as:
  • Trigger / Genlock critical paths: timing is edge/event-based; state-dependent phase steps are unacceptable unless proven bounded and calibratable.
  • Lane-alignment sensitive chains: multi-lane bonding/deskew margin can be affected by asymmetry or buffering behaviors.
  • Fixed-latency expectations: calibration assumes stable delay. Any lock-driven step must be measured and bounded.

First 2 measurements (locked and repeatable)

Measurement #1 — Lock/relock events vs temperature and stress:
  • Log: retimer lock state, relock count (per hour), holdover entry (if exposed), board/retimer temperature.
  • Correlate: relock bursts aligned to EMI stress (motors/relays) indicate susceptibility to common-mode or power noise injection.
  • Pass indicator: lock remains stable across temperature sweep and cable stress with no step-like events.
Measurement #2 — Before/after insertion comparison (margin vs timing semantics):
  • Compare counters: BER/FEC/CRC, retrain events, and any lane alignment failures (deskew).
  • Compare timing: measure latency distribution (or timestamp delta where available) and look for widening or discrete jump clusters.
  • Decision: if errors fall but timing distribution widens or becomes multi-modal, the retimer may “fix data but break determinism”.
Practical decision rule: choose redriver when loss dominates and timing semantics must remain stable; choose retimer only when jitter/noise requires re-clocking and lock/holdover behavior has been proven bounded under stress.
F3 — Retimer vs Redriver Decision Tree Pick the minimum intervention that preserves timing semantics Channel loss length / insertion loss Jitter shape random vs burst events Latency expectation fixed / calibratable Loss dominant? Need jitter filter? Fixed latency? NONE / Layout first fix return path / shielding REDRIVER gain + EQ, preserves timing Best when loss dominates RETIMER (CDR) re-clock + jitter filtering Validate lock / holdover Check latency steps low loss loss-dominant needs jitter filter fixed latency?
Cite this figure — Figure F3 (Retimer vs Redriver Decision Tree). Suggested caption: “Select the minimum intervention that meets channel loss and jitter needs while preserving fixed or calibratable latency.”

H2-4. Deterministic clocks: refclk distribution, CDR behavior, jitter budget

Clock quality is the root of link stability. When SerDes margin gets thin, the most common field signature is not “bandwidth limit” but lock sensitivity: training failures, intermittent relock, and error counters that jump with temperature, power noise, and EMI coupling. A deterministic interface starts with a refclock chain that is measurable at the PHY/retimer pins.

How refclk quality impacts CDR lock margin (engineering view)

  • Refclk sets the jitter floor: noisy reference raises phase noise seen by PLL/CDR blocks, shrinking the eye’s timing margin.
  • Noise couples through power/return paths: switching regulators, ground bounce, and poor return paths translate into clock phase modulation.
  • CDR behavior becomes event-driven: near the margin edge, small disturbances trigger relock bursts, which then appear as “random” link dropouts.

SSC tradeoff: compatibility vs margin

Spread-spectrum clocking (SSC) can reduce EMI peaks and help coexistence, but it also spreads energy across frequency, which may reduce margin in tight links or change how specific PHY/retimer implementations behave. SSC must be treated as a measurable knob: validate with counters (CRC/FEC/retrain) and lock stability under stress, not by assumption.

Jitter budget: allocate by segments and validate at the pins

  • XO (source): defines baseline phase noise; poor XO sets a limit no downstream cleaning fully fixes.
  • PLL / jitter cleaner: may improve or worsen depending on loop bandwidth; validate by lock stability and error slopes.
  • Fanout: adds additive jitter and can pick up crosstalk; routing and return paths matter.
  • Power coupling: clock parts are sensitive to supply noise; PSRR and placement determine real pin jitter.
  • Routing/return: discontinuous return path creates edge modulation and skew; treat clock routing like a high-speed interface.

First 2 measurements (with practical substitutes)

Measurement #1 — Refclk jitter/TIE at PHY/retimer pins (measure where it matters):
  • Preferred: measure phase noise / TIE at a probe point near the refclk pins.
  • Substitute: time-domain cycle-to-cycle jitter statistics at the pin-adjacent test point, plus correlation to load/EMI events.
  • Discriminator: if jitter at pins is worse than at the source, the problem is in distribution, power coupling, or return path—not the XO alone.
Measurement #2 — CDR lock stability + error counters vs jitter knob:
  • Toggle SSC, change refclk source quality, or enable/disable jitter cleaner (one knob at a time).
  • Observe: relock count, training failures, CRC/FEC slope, and any retrain events under temperature and EMI stress.
  • Conclusion: if small jitter changes create large counter jumps, clock margin is the limiting factor and must be fixed before adding retimers.
Engineering rule: treat “clock determinism” as a pin-level specification. Link robustness improves most when refclk distribution, power isolation, and return paths are validated by measurements at the PHY/retimer pins.
F4 — Deterministic Refclk Chain XO → PLL / Jitter Cleaner → Fanout → PHY/Retimer (noise injection + measure here) XO reference source PLL / Jitter Cleaner loop bandwidth Fanout distribution PHY / Retimer PLL / CDR refclk pins Power noise BUCK / LDO coupling Return path ground discontinuity Crosstalk / EMI data coupling into refclk Measure here TIE / jitter at pins SSC knob compatibility vs margin Jitter budget segments XO PLL / Cleaner Fanout Power / Return / EMI
Cite this figure — Figure F4 (Deterministic Refclk Chain). Suggested caption: “Clock determinism must be verified at PHY/retimer refclk pins; power/return/EMI injection can shrink lock margin and trigger relock events.”

H2-5. Trigger/Strobe/Genlock: making GPIO behave like a timing instrument

A trigger line is only “deterministic” if the receiver sees a clean edge that crosses the threshold once. In practice, trigger jitter is dominated by threshold-crossing time uncertainty: overshoot, ringing, slow edges, and common-mode noise shift the exact moment the edge crosses the input threshold. This chapter hardens the trigger chain so the GPIO behaves like a timing instrument—not a noise detector.

Signal options (TTL / LVDS / Isolated) — strengths and failure modes

TTL / single-ended

Simple and common, but highly sensitive to return-path noise and ground potential differences. Long cables amplify ringing/slow edges. Mis-triggers often appear as “random” until pin waveforms are checked.

LVDS / differential

Better immunity to common-mode interference. Requires correct termination/biasing and consistent cabling. Failure often shows as burst errors during EMI events or connector wear.

Isolated trigger (digital isolator / opto / magnetic): reduces ground potential problems and injected common-mode noise, but adds propagation delay and temperature drift. Isolation does not remove jitter—it changes the dominant source and must be verified by histogram.

Why mis-triggers happen (convert “field mystery” into evidence)

  • Return path / ground bounce: shared return impedance moves the receiver reference, shifting threshold crossing time.
  • ESD/EFT injection: connector transients create overshoot and ringing near the input threshold, producing multiple crossings.
  • Inductive load events: relay/solenoid/motor switching pushes common-mode currents into the trigger reference path.

Calibration and acceptance: trigger → frame-start delta histogram

Acceptance output: a trigger-to-frame Δt histogram (distribution, not just mean delay). Look for:
  • Width growth: wider distribution means threshold uncertainty or capture instability.
  • Long tails: rare events often correlate with ESD/EFT or load switching.
  • Multi-modal steps: discrete clusters indicate multiple capture paths or domain-crossing quantization behavior.

First 2 measurements (locked and repeatable)

Measurement #1 — Receiver-pin waveform quality:
  • Measure at the receiver input pin vicinity (threshold crossing happens here).
  • Record: overshoot/undershoot, ringing near threshold, edge rate (slow edges amplify time jitter), and reference noise.
  • Discriminator: ringing that crosses the threshold multiple times explains double triggers and histogram multi-peaks.
Measurement #2 — Trigger-to-frame Δt histogram:
  • Preferred: timestamp latch in the same clock domain for both trigger edge and frame-start event.
  • Substitute: capture trigger and a frame-sync/frame-start marker on an oscilloscope for long runs, then build Δt statistics.
  • Decision: if waveform is clean but histogram is stepped, the root cause is likely capture/clock-domain behavior—not cable noise.
Connector entry protection TVS to correct return Optional CMC (common-mode) Level shift Schmitt/buffer Isolation (if needed) Timestamp latch Histogram acceptance
F5 — Trigger/Strobe/Genlock Hardening Chain Make threshold crossing stable and timestampable Connector trigger in TVS at entry CMC optional Level Shift TTL/LVDS Schmitt threshold hardening Isolator if needed Timestamp Latch same clock domain FPGA / SoC frame-start event Δt histogram Noise sources return / ESD-EFT / inductive load controlled return path (shield/chassis reference) threshold
Cite this figure — Figure F5 (Trigger Hardening Chain). Suggested caption: “Treat trigger determinism as threshold-crossing stability plus timestampable capture; validate with receiver-pin waveform and Δt histogram.”

H2-6. Cable/connector/grounding: return path is the “hidden interface”

Many “swap the cable and it works” cases are not magic. The cable and connector define the return path for shield/common-mode currents. If shield/drain/chassis bonding is uncontrolled, the interface effectively changes with location, equipment, and aging—showing up as burst errors, relock events, or trigger threshold jitter. This chapter turns cable/grounding into an measurable qualification item.

Shield / chassis / signal ground bonding: practical Do / Don’t

Do

Use controlled bonding: 360° shield termination to chassis where applicable, short return paths, and intentional connection between chassis and signal ground. Keep shield current out of sensitive signal ground regions.

Don’t

Avoid long pigtails for shield grounding (high HF impedance), random multi-point bonds that create loops, or routing shield/drain currents through signal ground. These create “hidden antennas” and unstable references.

Ground potential difference: isolate trigger or data (interface-level consequences only)

  • Isolate trigger first when the symptom is threshold drift or mis-triggering that correlates with equipment bonding or load switching.
  • Consider data-side isolation / common-mode control when burst errors track ground shifts and exceed receiver common-mode tolerance.
  • Rule: isolate the path that carries the unstable reference. Confirm using pin waveform quality and error-counter correlation.

Cable & connector qualification: acceptance methods that survive the field

Qualification checklist:
  • TDR / impedance consistency: find connector reflection points; compare before/after bend and after mating cycles.
  • Insertion-loss trend: track loss changes across temperature and cable lots; watch for “only one batch fails”.
  • Bend stress test: repeatable bend radius cycles while logging error counters and trigger histogram changes.
  • Mating-cycle risk: connector wear raises contact resistance and degrades shield bonding, increasing common-mode injection.
Placement rule (interface consequence): TVS must return to the correct reference near the connector. CMC is optional and should be placed to control common-mode current paths without degrading edge integrity. The “correct part” is less important than the correct return path.
F6 — Return-Path Map (Hidden Interface) Shield/drain/chassis bonds define common-mode current paths DO — controlled bonding DON’T — long pigtail / loops Icons: Shield / Drain / Chassis bond / SGND / TVS (entry) / CMC (optional) / Current path arrows Connector Shield / Braid 360° bond Chassis TVS entry return CMC optional SGND Controlled bond Connector Shield / Braid Long pigtail SGND Multiple random bonds → loop shield current through SGND TVS wrong return Chassis Qualification TDR / bend / mating cycles Qualification TDR / bend / mating cycles
Cite this figure — Figure F6 (Return-Path Map). Suggested caption: “Return path and bonding convert cable/connector choices into interface behavior; qualify by TDR, bend stress, mating cycles, and counter correlation.”

H2-7. Bring-up & interoperability: training, deskew, counters you must expose

Interoperability is not a “protocol debate”; it is an observable bring-up process. A link that cannot be explained by states + counters cannot be debugged in the field. This chapter defines a practical bring-up state machine and the minimum log/counter schema that must be exposed to turn “works in Lab A, fails in Factory B” into measurable evidence.

Bring-up states (engineering view): detect → lock → train → deskew → ready → stream

Goal: map every failure to a state boundary and a small set of counters. Avoid “replug-and-pray”.
  • Detect: physical presence and remote presence are confirmed.
  • Clock/CDR Lock: recovered clock is stable enough to proceed.
  • Train/EQ: equalization/training converges and is repeatable.
  • Align/Deskew: lane mapping and skew alignment succeed with margin.
  • PCS/FEC Ready: error protection/thresholds are consistent and understood.
  • Stream: counters become low-slope and predictable (no hidden oscillation).

Interoperability traps (symptom → state → evidence → first fix)

Lane mapping / polarity / swap

Symptom: detect OK but deskew fails or multi-peak behavior appears. Evidence: deskew_fail, lane_bitmap, align_reason. First fix: verify lane map matches routing; log the mapping hash.

Default EQ policy mismatch

Symptom: retrain bursts only on certain peers/cable lots/temperatures. Evidence: retrain_count + retrain_reason vs temperature; FEC corrected slope. First fix: log EQ profile ID and training attempt outcomes.

FEC threshold differences

Symptom: “runs but freezes sometimes” vs “never starts” across peers. Evidence: corrected high but uncorrected spikes; CRC bursts. First fix: expose/record thresholds and uncorrected events as stop-signals.

Retrain strategy differences

Symptom: stream interruptions on one peer, silent error accumulation on another. Evidence: retrain timeline + link up/down timestamps. First fix: bucket retrain reasons (loss-of-lock / BER / deskew drift).

Mandatory counters and logs (minimum field-debug schema)

Must expose (no excuses):
  • CRC failures (rate and bursts).
  • FEC corrected and FEC uncorrected (both are required to separate “recoverable margin” from “data loss”).
  • Retrain count + retrain reason bucket (loss-of-lock / BER-threshold / deskew-drift / manual).
  • Deskew fail count + lane bitmap + fail reason.
  • Temperature (board/PHY/retimer vicinity) and link up/down timestamps.
Recommended additions (high ROI, still interface-scoped):
  • CDR lock-loss count and lock-loss duration (separates clock instability from training/deskew issues).
  • Cable/port ID and a configuration hash (mapping/EQ/FEC/retrain settings) for reproducibility.
  • Error slope over time (e.g., per minute) rather than only cumulative totals.

First 2 measurements (locked and repeatable)

Measurement #1 — Bring-up timeline log:
  • Record state transitions with timestamps (detect/lock/train/deskew/ready/stream).
  • Attach a snapshot of the mandatory counters at each transition.
  • Discriminator: if failures cluster at lock, suspect clock/CDR margin; if at deskew, suspect lane mapping/skew.
Measurement #2 — Counter correlation sweep:
  • Run temperature and cable-bend sweeps while logging retrain/deskew_fail/CRC/FEC (corrected & uncorrected).
  • Discriminator: burst errors + retrain spikes correlated with events indicates margin/return-path issues, not software stack.
State transitions CRC / FEC corr/uncorr Retrain + reason Deskew fail + bitmap Temp + timestamps Config hash
bringup_event { ts_ms, port_id, cable_id, config_hash state: DETECT | LOCK | TRAIN | DESKEW | READY | STREAM counters: { crc_fail, fec_corrected, fec_uncorrected, retrain_count, retrain_reason_bucket, deskew_fail, lane_bitmap, deskew_reason, temp_c, link_up_ms, link_down_ms, cdr_lock_loss_count, cdr_lock_loss_ms } }
F7 — Bring-up State Machine + Mandatory Observability Every failure must map to a state boundary + counters DETECT link present LOCK CDR stable TRAIN / EQ converge ALIGN / DESKEW lane map FEC READY thresholds STREAM stable Log port_id, cable_id link_present remote_present Log cdr_lock lock_loss_cnt lock_loss_ms Log eq_profile_id training_attempts retrain_reason Log deskew_fail lane_bitmap deskew_reason Log fec_corrected fec_uncorrected crc_fail Log temp_c uptime error slope Interoperability rule Expose counters + reasons + config hash, or the field becomes guesswork.
Cite this figure — Figure F7 (Bring-up State Machine + Observability). Suggested caption: “Map failures to state boundaries and counters; log reasons and configuration hashes to make interoperability reproducible.”

H2-8. Latency & jitter: separating transport variability from timing control

End-to-end latency is not one number; it is a waterfall of segments. Determinism improves when the variable segments (elastic buffers, queue points, retries, host handoff) are either controlled or made explicit via timestamps. This chapter decomposes latency, shows where variability is born, and provides measurement point placement without stepping into system-wide time governance.

Latency decomposition (what is fixed vs what can be random)

Segments (interface-scoped):
  • Serialize / line encoding: typically fixed (rate-defined).
  • Channel propagation: near-fixed (cable length).
  • PCS/FEC processing: often fixed, but policy/threshold behavior can create effective variability under stress.
  • Elastic buffer / FIFO: common variable source (rate mismatch, deskew drift, retrain side effects).
  • Bridge / DMA to host: may be variable depending on buffering and bus contention.
  • Host stack handoff: highly variable (treated as variable zone, not tuned here).

How to measure (marker / loopback / HW timestamps — choose the strongest available)

A) HW timestamp insertion/extraction (preferred)

Insert a frame marker timestamp at TX, extract at RX. Build Δt histograms and correlate tails with retrain/lock events. This separates true transport variability from later processing variability.

B) Marker + internal loopback (strong discriminator)

Loopback isolates the “pure transport” distribution. If loopback is tight but end-to-end is wide, variability is downstream (FIFO/bridge/host).

C) External observable pins (fallback)

Capture trigger/marker and a frame-start/frame-sync indication on a scope for long runs. Use it to reveal long tails and multi-peak behavior.

Decision rule

Wide loopback distribution points to link-internal buffering/retrain behavior. Tight loopback + wide end-to-end points to bridge/host variability.

Mitigation (control variable buffers first, then compensate)

Priority order:
  • Control variable buffering: avoid hidden queue points; keep elastic buffers in predictable modes when configurable.
  • Make variability explicit: timestamp insertion/extraction allows downstream compensation without guessing.
  • Treat long tails as failure signals: correlate tails with retrain/lock/deskew counters (closes the loop to H2-7).

First 2 measurements (locked and repeatable)

Measurement #1 — Latency histogram at two cut points:
  • Build Δt histograms for “transport-only” (loopback or early RX) and “end-to-end”.
  • Discriminator: the difference between the two reveals where variability is introduced.
Measurement #2 — Tail correlation with counters:
  • Tag histogram outliers (e.g., top 0.1%) and correlate with retrain/lock-loss/deskew events and temperature.
  • Decision: tails that line up with events indicate link-level instability rather than “random host scheduling”.
F8 — Latency Waterfall (Fixed vs Variable) + Timestamp Points Control variable segments; make the rest explicit End-to-end path Serialize Channel PCS / FEC FIFO / Elastic VARIABLE Bridge / DMA VARIABLE Host VAR TS TX insert TS RX extract Interpretation Fixed / near-fixed segments Variable segments (buffers/queues/retries) Use TS points to expose variability and correlate tails with retrain/lock events. Distribution view Wide tails often align with retrain/lock-loss events
Cite this figure — Figure F8 (Latency Waterfall + Timestamp Points). Suggested caption: “Decompose latency into fixed and variable zones; place timestamps to expose variability and correlate long tails with link events.”

H2-9. EMC/ESD/Surge hardening without killing the eye

Hardening is a margin trade: divert ESD/EFT/surge energy to the right return path while keeping the differential channel inside the eye/BER budget. This chapter explains why “protection parts kill the eye”, how placement and parasitics create measurable failures, and how to validate protection effectiveness without guesswork.

Symptom signatures: ESD vs EFT vs Surge (what the link “looks like”)

ESD (single, fast)

Typical signature: short, isolated CRC bursts or brief link flaps tied to touch/plug events. Evidence: bursty counters, not a steady slope; may coincide with trigger glitches if return paths are poor.

EFT (repetitive pulse train)

Typical signature: repeatable retrain spikes and frequent link flaps aligned with switching events (contactors, motors, VFD). Evidence: strong time correlation on the event timeline.

Surge (higher energy)

Typical signature: PHY reset, brownout-style interruptions, or permanent margin degradation after the event. Evidence: resets and power/health logs align; uncorrected errors may appear as a hard stop.

Fast discriminator

If errors are bursty and tied to human interaction → ESD-like. If errors cluster as repeatable trains near switch events → EFT-like. If resets/brownouts dominate → surge-like or power integrity coupling.

Why protection kills the eye: parasitics and placement

Key mechanism: TVS/ESD arrays add capacitance and discontinuities that reduce eye height/width and tighten the BER margin.
  • Array capacitance (CESD): behaves like an additional load; higher C reduces high-frequency content and can increase reflections.
  • Stub + pad inductance: turns “good parts” into resonant structures; placement and routing length decide severity.
  • Placement trade: closer to the connector improves energy capture, but routing/stub mistakes can amplify channel discontinuities.
Failure pattern to recognize:
  • Eye shrinks after protection; FEC corrected slope rises even without external events.
  • Deskew margin becomes sensitive to temperature/cable bends; retrain rate increases.
  • Protection “works” for ESD but silently forces operation near the BER cliff.

CMC selection: reduce common-mode, avoid differential damage

What a CMC helps: reduces common-mode current and improves immunity to coupled EMI. What a CMC can break: adds insertion loss / phase distortion that reduces differential eye margin and can worsen deskew sensitivity.
  • Use a CMC when failures correlate with external EMI sources and common-mode coupling signatures.
  • Validate that the CMC does not create new retrain behavior or a worse corrected-error slope under baseline conditions.
  • Prefer “evidence-first”: do not add a CMC just because it is common in reference schematics.

First 2 measurements (locked and repeatable)

Measurement #1 — Before/after protection: eye/BER (or best available proxy)
  • Compare eye/BER (PRBS/loopback if available) before and after adding TVS/ESD/CMC.
  • If direct eye tools are not available, compare: FEC corrected slope, CRC burst rate, retrain rate under identical conditions.
  • Decision: if baseline margin becomes worse without external stress, the protection network is overloading the channel.
Measurement #2 — Event correlation: ESD/EFT injection vs counters and retrain
  • Inject events and align the event timeline with CRC/FEC/retrain/lock-loss counters.
  • Decision: protection is effective only if event-triggered bursts reduce without increasing baseline error slopes.
CRC bursts FEC corrected/uncorrected Retrain + reasons Lock-loss events Chassis bond Before/after A/B
F9 — EMC/ESD Hardening Chain (Protect Energy, Preserve Eye) Parasitics and placement decide whether protection helps or hurts Connector coax / RJ45 TVS / ESD Array C adds load CMC CM↓, DM? PHY / SerDes eye / BER Parasitic C Chassis / Shield Bond Bond Bond Divert ESD/EFT energy to chassis Eye impact checks Before/after eye or BER proxy Corrected slope + retrain rate
Cite this figure — Figure F9 (Protection chain + parasitic impact). Suggested caption: “Place TVS/ESD/CMC to divert energy into chassis while minimizing parasitic C and discontinuities that shrink the differential eye.”

H2-10. Practical validation plan: stress matrix for links & triggers

This chapter converts the entire interface discussion into a reproducible validation matrix. Each stress axis has defined observables (counters + waveforms), and pass/fail criteria are expressed as baseline-relative limits plus hard stop conditions (uncorrected bursts, repeated flaps, excessive trigger jitter tails).

Stress axes (apply, log, decide)

Stress dimensions:
  • Temperature: cold/room/hot points with dwell long enough to stabilize counters.
  • Cable length & bends: shortest/nominal/longest; controlled bend radius and repeated flex cycles.
  • EMI sources: motor/VFD proximity, switching transitions, and repeatable event timing.
  • Supply ripple/noise: controlled ripple injection or load steps; correlate with lock-loss/retrain.
  • ESD/EFT: injection points and levels, aligned to an event timeline.

Evidence packs (what to record every time)

Link evidence pack
  • CRC, FEC corrected/uncorrected
  • Retrain count + reason buckets
  • Deskew fail + lane bitmap (if applicable)
  • CDR lock-loss count + duration
  • Temp + link up/down timestamps + config hash
Trigger evidence pack
  • Receiver pin waveform (edge, ringing, overshoot)
  • Trigger-to-frame Δt histogram (p95/p99 + tail)
  • Event timeline alignment (EMI switching, ESD/EFT injection)
  • Fail markers: multi-peak histograms, long tails, missed triggers

Pass/Fail framing (baseline + stress limit + hard stops)

Baseline (required): measure at room temperature, nominal cable, quiet EMI environment. Record histograms and counter slopes.
  • Counter slope: corrected/CRC/retrain per time unit (not just totals).
  • Trigger jitter: p95/p99 and tail behavior (single-peak vs multi-peak).
Hard stop conditions (fail immediately):
  • Repeated link flaps that prevent stable streaming.
  • Uncorrected bursts that exceed the application’s data loss tolerance.
  • Retrain storms (dense clusters) under a single stress step.
  • Trigger Δt distribution becomes multi-peak or develops long tails beyond the defined limit.
Stress limits (baseline-relative):
  • Allowable CRC/FEC increases are defined as a multiple of baseline slope (and must remain stable over dwell).
  • Allowable retrain count is defined per hour under each stress; reasons must be logged.
  • Trigger jitter limit is defined with p99 + tail constraint (no rare long-latency spikes).

First 2 measurements (locked and repeatable)

Measurement #1 — Stress step run with synchronized logging
  • For each stress step: record evidence packs + event timeline + configuration hash.
  • Output: per-step summary including counter slopes and histogram parameters.
Measurement #2 — A/B comparison across mitigations
  • Compare baseline and stress behavior before/after a single change (e.g., protection placement, CMC selection, grounding bond).
  • Decision: accept only if stress robustness improves without degrading baseline eye/BER proxies.
F10 — Validation Stress Matrix (Links + Triggers) Rows = stress axes, Columns = observables + pass/fail Stress Counters Eye / BER Proxy Waveform / Hist Pass / Fail Temperature Cable length Cable bend / flex EMI (motor / VFD) Supply ripple ESD / EFT events Baseline + limit Baseline + limit Baseline + limit Baseline + limit Baseline + limit Hard stops Record → Correlate → Decide Log packs Event correlation Pass/Fail criteria
Cite this figure — Figure F10 (Stress matrix + record-to-criteria pipeline). Suggested caption: “A reproducible validation matrix: apply stresses, log standardized evidence packs, correlate events, and decide using baseline-relative limits plus hard stop rules.”

H2-11. Field debug SOP: symptom → evidence → isolate → first fix

This SOP is optimized for “minimum tools, maximum certainty”: each symptom is handled with 2 measurements, 1 discriminator, and 1 fastest first-fix. The goal is to turn “link weirdness” into measurable evidence (counters + waveforms) without drifting into OS/driver tutorials.

Suggested logging cadence: counters every 1–5 s + event logs on retrain/relock/CRC burst + temperature snapshot.
2 measurements first 1 discriminator 1 first-fix MPN examples included 
Copy/Paste SOP template (per incident)
1) Symptom:
2) Environment (cable length, temp, EMI sources, host model, power source):
3) Measurement #1 (counters/time-series):
4) Measurement #2 (waveform/eye/PRBS/trigger histogram):
5) Discriminator (single sentence: if X then Y):
6) Isolation step (swap/move one variable):
7) First fix (fastest reversible change):
8) Result (before/after counters + screenshot IDs):

Symptom A — Dropped frames / stutter (stream continues, but cadence breaks)

Treat this as a “margin + buffering” problem until proven otherwise. The fastest way to stop guessing is to correlate frame drop events with link-layer counters and retrain events.

First 2 measurements (must do)

  • Time-series counters: CRC / FEC corrected / FEC uncorrected / retrain / deskew-fail vs time, plus temperature.
  • Margin probe: PRBS/loopback margin sweep if available; otherwise “eye/BER proxy” (e.g., error-burst density vs EQ setting changes).
Discriminator If dropped frames align with CRC/FEC bursts or retrain/deskew events, it is transport integrity. If drops occur with clean counters, suspect buffer/FIFO thresholds or host ingestion variability (still measured via timestamps, not OS tuning).

Isolate (change only one variable)

  • Swap to a known-good shorter cable; keep the same endpoints.
  • Force a conservative EQ preset; keep the same cable.
  • Move the camera/host away from EMI sources (VFD/motor drive) without changing cable routing yet.

First fix (fastest reversible action)

  • Stabilize channel loss/EQ: insert a suitable redriver (linear EQ) when attenuation/ISI dominates.
  • Stabilize recovered clock: insert a retimer when jitter/clock recovery margin dominates (but verify latency expectations in H2-3).
  • Reduce connector-side parasitics: replace over-capacitance protection parts; keep the eye intact.
Example MPNs (selection depends on lane count/data rate)
  • 10.3 Gbps quad redriver (EQ + de-emphasis): TI DS100BR410.
  • 9.8–12.5 Gbps 2-ch retimer: TI DS125DF111.
  • Low-capacitance high-speed ESD array (up to ~10 Gbps class): TI TPD4E02B04.
Note: treat these as “known-good reference parts” for prototyping; final choice must match protocol electrical specs and channel budget.

Symptom B — Link frequently reconnects / retrains (stream resets)

Reconnect loops almost always have a “trigger”: refclk quality, power integrity at PHY/retimer, or harsh EMI/ESD events causing CDR unlock or resets. The key is logging why the link re-entered training.

First 2 measurements (must do)

  • Event log: lock → unlock → retrain timestamps, reason flags (if available), plus temperature.
  • Refclk check at the pin: measure refclk jitter/TIE at the PHY/retimer input (or a practical proxy: phase noise/jitter at the clock output feeding that pin).
Discriminator If retrain events rise with temperature or vibration while refclk remains stable, suspect channel margin (cable/connector/EQ). If retrain events track refclk degradation or supply noise, suspect clocking or rail noise into the CDR path.

Isolate

  • Lock refclk source to a known-clean generator path; keep everything else unchanged.
  • Hold temperature constant (or step it) while logging counters and lock stability.
  • Temporarily reduce link rate (if supported) to see if the failure is margin-limited.

First fix

  • Add/upgrade a jitter-cleaning clock device feeding PHY/retimer refclk.
  • Reduce noise injection: tighten decoupling and keep refclk routing isolated from fast switching return paths.
  • If reconnect is ESD/EFT-correlated, harden connector front-end (see Symptom C) without adding excessive capacitance.
Example MPNs
  • Low-jitter clock generator / jitter attenuator family: Si5341 (Skyworks/SiLabs).
  • High-speed ESD for SuperSpeed USB class links: TI TPD4EUSB30.
  • High-speed redriver option (when margin is the root cause): TI DS100BR410.
Practical rule: “retrain storms” require refclk + counters correlation; do not swap random cables repeatedly without evidence.

Symptom C — Fails only in one venue / one factory (same design, different place)

“Works everywhere except Site X” is usually a common-mode + return-path story: ground potential, EMI coupling, ESD/EFT events, or cable routing differences that collapse margin.

First 2 measurements (must do)

  • Correlation: counters (CRC/FEC/retrain) vs machine state (motor/VFD on/off, welders, contactors, lighting strobe, etc.).
  • Front-end waveforms: at connector-side shield/chassis bond + trigger pin waveform integrity (overshoot/ringing/slow edges).
Discriminator If failures align with switching events (motor start, relay click, ESD touch), suspect common-mode injection and return-path bonding. If failures scale with cable length/bend radius only, suspect insertion loss / impedance discontinuity.

Isolate

  • Route cable away from power conductors and VFD outputs; keep endpoints unchanged.
  • Temporarily bond chassis/shield at the recommended point; verify whether counters improve.
  • Swap protection/CMC footprint options (if designed-in) and compare eye/BER before/after.

First fix

  • Use low-capacitance ESD arrays placed correctly; avoid “big TVS” that collapses the eye.
  • Add an appropriately chosen common-mode choke (CMC) only when it improves common-mode without harming differential mode.
  • Isolate trigger/aux I/O when ground potential differences are present.
Example MPNs (connector hardening references)
  • USB3-class ESD array: TI TPD4EUSB30.
  • Ultra-low-C multi-line ESD array (high-speed links): TI TPD4E02B04.
  • Single-line low-leakage ESD diode: Nexperia PESD5V0S1UL.
  • 2-line common-mode choke example: TDK ACM2012D-900-2P (ACM2012D-900-2P-T00 variant).
  • Small CMC alternative: Murata DLM11SN900HY2.
  • Trigger/aux isolation example: TI ISO7721 (dual-channel digital isolator).
Do not blindly add CMC/TVS: validate with eye/BER (or best available proxy) before declaring victory.

Symptom D — Trigger false events / trigger jitter (GPIO must behave like an instrument)

A trigger line is an analog waveform with a threshold. “False trigger” is usually a threshold-crossing problem: ringing, slow edges, ground bounce, or ESD/EFT coupling.

First 2 measurements (must do)

  • Pin waveform: at the receiver pin (not at the source). Capture edge rate, overshoot, ringing, and ground reference movement.
  • Trigger-to-frame histogram: measure Δt(trigger edge → frame-start timestamp) and plot jitter/percentiles.
Discriminator If the pin waveform shows ringing that crosses the threshold multiple times, harden the edge (Schmitt/buffer/termination). If Δt histogram widens only during EMI events, treat it as return-path/EMC coupling, not “software timing”.

Isolate

  • Switch trigger level standard (TTL ↔ LVDS) if supported; compare jitter and false rates.
  • Insert a buffer/Schmitt stage at the receiver side; verify histogram tightening.
  • Temporarily isolate the trigger path if ground potential differences are suspected.

First fix

  • Use a Schmitt-trigger buffer close to the receiver pin to eliminate slow-edge threshold chatter.
  • Use LVDS receivers/drivers for robust trigger distribution when cable runs are long/noisy.
  • Use digital isolation when trigger reference ground is unstable across machines.
Example MPNs
  • Schmitt trigger buffer (TTL hardening): TI SN74LVC1G17.
  • Single LVDS receiver (one trigger pair): TI DS90LV018A.
  • LVDS line receiver option: TI SN65LVDS2 (and related SN65LVDS family).
  • Digital isolator for trigger/aux lines: TI ISO7721 or ADI ADuM1100.
For false triggers, “buffer at the receiver pin + histogram proof” is usually the fastest credible win.

Figure F11 — Field debug decision tree (symptom → evidence → first fix)

F11 • Field Debug Tree: Symptom → Evidence → First Fix Use 2 measurements + 1 discriminator to avoid random part swaps. SYMPTOM OBSERVED Dropped frames stutter / cadence breaks Link flaps retrain / reconnect storms Site-only failure one factory / one venue Trigger issues false / jittery trigger Evidence 1: Counters CRC / FEC / retrain vs time Evidence 2: Margin PRBS sweep / eye-proxy Evidence 1: Event log lock/unlock reason + temp Evidence 2: Refclk jitter/TIE at the pin Evidence 1: Correlation CRC bursts ↔ machine events Evidence 2: Front-end shield bond + pin waveform Evidence 1: Pin edge ringing / slow edges / bounce Evidence 2: Histogram Δt(trigger→frame) percentiles First fix Redriver/Retimer + verify DS100BR410 / DS125DF111 First fix Clean refclk + log proof Si5341 (example) First fix Low-C ESD + CMC + bond TPD4EUSB30 / ACM2012D… First fix Buffer/Schmitt + LVDS/ISO SN74LVC1G17 / ISO7721 Tip: Always capture “before/after” counters + one waveform screenshot ID per fix.
Cite this figure: ICNavigator · Machine-Vision Interfaces · H2-11 · Figure F11  · #fig-f11

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H2-12. FAQs ×12 (Accordion; evidence-based; no scope creep)

Each answer is constrained to the on-page evidence chain: PHY counters, clock/jitter evidence, trigger waveforms, EMC correlation, and logging discipline. Every FAQ includes: 2 evidences → 1 discriminator → 1 first fix.

1Dropped frames: is it BER, or buffering/backpressure?

Evidence 1: trend CRC/FEC corrected/uncorrected and retrain events over time. Evidence 2: plot inter-frame Δt histogram (p95/p99 + tail), or run PRBS/eye-proxy if available. Discriminator: if Δt tails align with CRC/FEC bursts or retrains, it is margin/BER; otherwise it is buffering/backpressure. First fix: shorten/upgrade cable and lock a conservative EQ preset; add a redriver/retimer only with before/after proof (e.g., TI DS100BR410 or DS125DF111).

Maps to: H2-2, H2-7, H2-8, H2-11
2It fails only in one factory: how to quickly falsify common-mode/return-path?

Evidence 1: correlate CRC/FEC bursts and retrain storms with site events (VFD/motor start, contactor switching, touch/ESD). Evidence 2: do a minimal A/B change in chassis/shield bonding and re-log the same counters (plus one connector-side waveform snapshot). Discriminator: if bursts move with events and improve with bonding A/B, the return-path/common-mode is dominant. First fix: use low-cap ESD at the connector and correct chassis bonding; add a CMC only after eye/BER-proxy stays intact (e.g., TI TPD4E02B04/TPD4EUSB30 + TDK ACM2012D-900-2P).

Maps to: H2-2, H2-6, H2-9, H2-11
3A retimer fixed data errors but sync got worse: where does uncertainty enter?

Evidence 1: compare lock/relock counts and Δt(timestamp) histogram before vs after inserting the retimer (watch p99/tail and multi-peak). Evidence 2: measure refclk quality (jitter/TIE at the retimer/PHY pin, or a practical refclk proxy) and log any temperature-linked relocks. Discriminator: if errors drop but Δt widens and tracks relock events, retiming is introducing variable phase/latency. First fix: prefer a redriver when fixed latency is required; if a retimer is mandatory, clean/lock refclk and freeze configuration (e.g., Si5341-class jitter cleaner + TI DS125DF111).

Maps to: H2-3, H2-4, H2-5, H2-8
4Same cable batch, some units fail: how to pin it down with TDR / insertion loss?

Evidence 1: keep endpoints constant and log CRC/FEC/retrain slope per cable (same temperature, same routing). Evidence 2: measure TDR to locate impedance discontinuities (connector/crimp/bend point) and compare insertion/return loss across the batch. Discriminator: if one cable shows a fixed-location discontinuity and consistently higher error slope, the cable is the root cause, not the host. First fix: enforce a cable acceptance gate (TDR signature + loss threshold + bend-radius rule) and quarantine outliers; retimers/redrivers are only temporary band-aids when the channel is out of spec.

Maps to: H2-6, H2-2
5Trigger jitter looks like drift: how to prove it is threshold-crossing jitter?

Evidence 1: scope the trigger at the receiver pin and check for slow edges, ringing, overshoot, and ground-reference movement. Evidence 2: plot a trigger→frame-start Δt histogram (p95/p99 + tail, and whether it becomes multi-peak). Discriminator: if the pin waveform crosses the threshold multiple times and the Δt histogram becomes multi-peak, it is threshold-crossing jitter rather than “software timing.” First fix: harden the receiver edge with a Schmitt buffer and proper termination; move to LVDS or add isolation if needed (e.g., TI SN74LVC1G17 / DS90LV018A / ISO7721).

Maps to: H2-5
6Adding ESD protection made the link less stable: what parasitic is most common?

Evidence 1: compare baseline (no EMI events) CRC/FEC corrected slope and retrain rate before vs after adding the protection. Evidence 2: compare eye/PRBS/BER-proxy (or rate sensitivity to EQ presets) to see if margin shrank. Discriminator: if baseline errors rise and the link becomes more temperature/cable sensitive, parasitic capacitance/stubs are collapsing the eye. First fix: switch to lower-capacitance ESD parts, minimize stubs, and route discharge to chassis correctly; re-validate with the same eye/BER-proxy (e.g., TI TPD4E02B04 or Nexperia PESD5V0S1UL).

Maps to: H2-9, H2-2
7It fails only when hot: check retimer behavior first, or refclk first?

Evidence 1: log retrain/lock-loss (and any lock/relock flags) vs temperature with a consistent timebase. Evidence 2: measure refclk jitter/TIE at the PHY/retimer pin (or a practical refclk proxy) while stepping temperature. Discriminator: if lock-loss tracks refclk degradation, refclk/rail noise is primary; if refclk stays clean but errors rise with heat, channel loss/EQ drift is primary. First fix: stabilize refclk (jitter cleaner + layout/decoupling) before swapping retimers; only then consider retimer thermal margins (e.g., Si5341-class refclk conditioning; TI DS100BR410 for loss compensation).

Maps to: H2-3, H2-4, H2-7
8MIPI/SLVS-EC deskew fails intermittently: top three suspects?

Evidence 1: capture deskew-fail count plus lane bitmap/time-of-failure and correlate with temperature and cable/handling events. Evidence 2: check refclk stability (jitter/TIE or proxy) and a margin proxy (PRBS/eye-proxy if available) to see whether the sampling window is shrinking. Discriminator: if failures follow cable bend/connector touch, suspect lane skew/impedance discontinuity; if failures follow temperature/rail noise, suspect clock/noise margin; if failures appeared after protection/CMC changes, suspect added parasitics. First fix: lock lane mapping/skew budgets, clean refclk, and remove “eye-killing” parasitics one at a time with before/after counters.

Maps to: H2-2, H2-4, H2-7
910GigE periodic stutter: congestion/PAUSE, or PHY errors?

Evidence 1: log PHY/PCS error counters (CRC/FEC/align errors, link-down/up, retrain if available) alongside any flow-control indicators exposed by the interface. Evidence 2: build a latency waterfall or Δt histogram to see whether stalls are strictly periodic (queueing) or bursty and event-correlated (margin/EMI). Discriminator: if counters stay clean while stalls repeat with stable periodicity, it is transport variability (queue/PAUSE) rather than PHY margin; if CRC/FEC bursts coincide with stalls, it is PHY integrity. First fix: pin and log flow-control behavior (no “hidden buffers”), and in parallel validate PHY margin via PRBS/eye-proxy; do not change switching infrastructure without evidence.

Maps to: H2-7, H2-8, H2-2
10USB3 works on some hosts but not others: what evidence can this page provide?

Evidence 1: compare bring-up/training outcomes and error/reconnect counters across hosts using the same device and cable; record a configuration hash and temperature. Evidence 2: apply a margin proxy (short vs long cable A/B, EQ preset A/B, PRBS/eye-proxy if available) to see whether failures sit on a margin cliff. Discriminator: if the “bad” host shows sharply higher error slope and strong cable-length sensitivity, it is PHY margin; if errors stay clean but behavior differs at bring-up boundaries, it is an uncontrollable host-side point highlighted in the interface landscape. First fix: harden device SI (low-cap ESD + redriver where appropriate) and keep a host compatibility log (e.g., TI TPD4EUSB30 + DS100BR410).

Maps to: H2-1, H2-7, H2-2
11How to choose a CMC without killing the eye, and what is the validation path?

Evidence 1: measure counters before/after CMC insertion under two conditions: quiet baseline and a repeatable EMI stress (CRC/FEC slope, retrain count). Evidence 2: compare eye/PRBS/BER-proxy (or EQ sensitivity) before/after to ensure differential margin is not harmed. Discriminator: if EMI stress improves while baseline remains unchanged and eye/BER-proxy stays healthy, the CMC is helping; if baseline worsens or deskew sensitivity increases, the CMC/placement is hurting. First fix: try a smaller/less intrusive CMC or move it closer to the connector, and prefer correct chassis bonding + low-C ESD first (e.g., TDK ACM2012D-900-2P or Murata DLM11SN900HY2).

Maps to: H2-9, H2-2
12What is the minimum log set for field debugging with the fewest tools?

Evidence 1 (required counters): CRC, FEC corrected/uncorrected, retrain count + reason bucket, deskew-fail count, lock-loss duration, temperature, and a configuration hash, sampled every 1–5 seconds plus event-triggered snapshots. Evidence 2 (one “physics proof”): either refclk jitter/TIE proxy at the PHY pin, a trigger→frame Δt histogram, or one receiver-pin edge screenshot. Discriminator: if a log lacks timebase + reasons, correlation is impossible and the debug loop will not converge. First fix: expose counters and timestamps at the interface boundary and standardize the capture template used in H2-11.

Maps to: H2-7, H2-11
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