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Smart Door Lock Controller Hardware: Secure Boot & Motor Drive

Smart Door Lock Controller Hardware: Secure Boot & Motor Drive

← Back to: Security & Surveillance

A smart door lock controller is a trusted local hub that turns identity checks into safe actuation: it must keep power stable through short high-current bursts, enforce secure boot/update policy, and log every critical event in a recoverable way. The practical approach is evidence-first—rail minima, motor current signatures, RF retry correlation, and atomic audit logs—so field failures can be isolated and fixed quickly without scope creep.

H2-1 · Definition & Page Boundary

Definition & Page Boundary (What this controller is—and isn’t)

A smart door lock controller is the trusted hub that binds three realities into one verifiable loop: identity (who is allowed), actuation (what physically moves), and power (whether the system can complete the action safely). “Secure” here means hardware-integrated authorization: the actuator is enabled only when the identity decision is valid, critical assets are stored in protected memory, and every outcome leaves evidence (codes/counters/logs) for field diagnosis.

This page solves (engineering deliverables)

  • Block-level architecture that connects Secure Element / secure MCU, sensor front-ends, actuator drivers, power rails, radios, and NVM logs into one system.
  • Trusted actuation gating: how “authorization → enable → motion → log” is enforced at integration level (not a crypto lecture).
  • Actuation-burst power planning: where brownouts happen during unlock/lock, and what must be measured to prove margin.
  • HMI front-end integration constraints: keypad scan robustness, fingerprint/face module power sequencing, ESD hardening, and low-power wake models.
  • Field evidence mindset: minimal probe points (rails + current) and minimal log fields (reason codes + counters) that close the diagnosis loop.
  • NVM + audit trail fundamentals: what must persist (counters/events/templates metadata) and how to avoid corruption on low battery.

Not covered (explicit exclusions to prevent scope creep)

  • Mobile app UX, cloud/backend architecture, user management flows.
  • Wireless protocol tutorials (pairing/commissioning step-by-step); only hardware constraints and observability are discussed.
  • Access-control panel topology / building wiring practices / multi-door relay matrices.
  • CCTV/video pipeline security, NVR/VMS recording integrity, watermarking, or timestamp non-repudiation workflows.
  • Any bypass/exploitation or “how to defeat a lock” instructions.

Scope Guard (mechanical acceptance checklist)

Allowed: secure element (SE), secure MCU, secure boot integration, anti-rollback counter (behavior-level), keypad scan, fingerprint AFE, face/IR module (front-end), motor/solenoid driver, current sense, stall/jam detect, battery/PMIC/UVLO, sleep/wake, BLE/Thread/Sub-GHz (hardware constraints), tamper switch, NVM + event logs.

Banned: mobile app / cloud backend, protocol-stack tutorial, CCTV/VMS/NVR topics, PoE switching, PTP timing systems, and any bypass instructions.

Acceptance: Ctrl+F for “Banned” terms — any deep coverage is out of scope.
Smart Door Lock Controller — Top-Level Blocks Trust Core Secure MCU SE Auth decision Counters & reasons Protected assets Inputs / HMI AFEs Keypad Fingerprint Face / IR Module (Front-End) Wake sources • quality metrics Actuation Motor / Solenoid Driver Current Sense + Jam Detect Power Tree Battery PMIC UVLO / brownout flags Burst rails isolation Low-Power Wireless BLE / Thread / Sub-GHz Antenna keepout • EMI coexistence NVM & Evidence Event Log + Audit Trail Reason codes • sequence counters Tamper / Safety Inputs Case Switch Door State Accel / Vibration Bolt / Latch Sensor authorize → enable burst power
Figure F1. Top-level blocks and the two “must-not-break” paths: authorize→enable and burst power. · Cite this figure
H2-2 · System Architecture

System Architecture (Signal + power + trust paths)

The controller is best understood as three testable paths. This prevents “feature talk” and forces an evidence-based design: each path has its own constraints, probe points, and failure signatures.

Path A — Trust path (identity → authorization decision → actuator enable)

  • Inputs: keypad events, biometric capture quality flags, tamper/safety inputs.
  • Decision boundary: authorization must be computed inside the trusted boundary (secure MCU + SE support) with auditable reason codes.
  • Hardware gating: actuator enable is a controlled signal (driver EN / power switch / gate) that cannot be “always-on” by mistake.
  • Minimum evidence: auth result code, attempt counter, anti-rollback / policy state, tamper flag snapshot.

Path B — Power path (battery → rails → actuation burst → brownout protection)

  • Actuation burst: unlock/lock is a short, high-current event that stresses battery internal resistance and rail stability.
  • Risk: brownout/reset in the middle of motion can cause partial actuation, corrupted NVM updates, or “retry storms”.
  • Architectural rule: separate (or strongly isolate) logic rails from motor/solenoid rails, and define a UVLO policy for “no-write” zones.
  • Minimum evidence: min rail during burst, reset reason (brownout flag), motor current peak/shape, UVLO entry timestamp.

Path C — Data path (sensors → decision → logs)

  • Observability is part of the architecture: without logs/counters, field failures become “mystery returns”.
  • Logging principle: log the cause (reason codes), not just the symptom; include sequence counters to detect missing records.
  • Isolation principle: store enough state to distinguish power collapse vs mechanical jam vs input quality failure.
  • Minimum evidence: event ID, reason code, sequence counter, last-known state (sleep/wake/auth/actuate), last-good pointer (if used).

Evidence hooks (fastest field triage): measure (1) min battery/logic rail during actuation and (2) actuator current waveform; then read (3) last failure reason code and (4) retry/stall counters. This 4-item set usually separates “power” vs “jam/drive” vs “authorization/input” in minutes.

Architecture as 3 Testable Paths Trust Path Power Path Data Path Identity Inputs Authorize reason code • counters Actuator Enable EN / power gate Battery + PMIC Logic Rails sleep → wake Actuation Burst peak current • droop Brownout Policy UVLO / no-write zone Sensors + Status Decision State sleep/auth/actuate Event Log ID • reason • seq Field Triage 2 probes + 2 logs enable log ① Vbat ② Logic rail ③ Motor current ④ Reason code
Figure F2. Treating the lock as Trust/Power/Data paths makes every failure measurable: ① Vbat, ② logic rail, ③ motor current, ④ reason code + counters. · Cite this figure
H2-3 · Threat & Safety Goals

Threat & Safety Goals (Hardware-level requirements, not a crypto lecture)

This chapter defines engineering-acceptance goals that drive the architecture. Each goal is written as: what must be prevented / guaranteed + which block owns it + what evidence proves it. It avoids exploit details and focuses on measurable behavior.

High-level goals (what the hardware must guarantee)

  • Prevent unauthorized actuation: the actuator cannot be energized unless an authorization decision is valid and the system state allows motion.
  • Prevent rollback to insecure firmware (requirement): the boot chain must reject older/incompatible firmware states and record the reason.
  • Protect biometric templates as stored assets: templates and their metadata must be stored in a protected boundary with integrity checks and traceable lifecycle events.
  • Tamper awareness + safe behavior: tamper signals must drive policy actions (fail-secure vs fail-safe) with auditable event records.

Security & Safety requirement checklist (maps to later chapters)

Requirement (behavior) Owner block Evidence to capture Mapped chapters
Actuator enable must be gated by a valid authorization decision (default-off on reset/fault). Secure MCU + driver enable path Enable reason code, attempt counter, driver EN waveform aligned to auth event H2-4 / H2-6 / H2-12
Low-voltage “no-write zone”: forbid sensitive NVM writes during brownout risk; retry policy must be logged. PMIC policy + MCU firmware rules UVLO/brownout flag, min rail during burst, “write-block” reason code H2-7 / H2-9 / H2-12
Anti-rollback requirement: reject older firmware states and keep a monotonic counter. SE + secure boot flow Boot state code, monotonic counter readout, rollback-reject reason H2-4 / H2-10
Template asset boundary: store templates/metadata with integrity checks and traceable lifecycle events. Protected storage boundary Template schema/version, CRC/ECC status, add/remove event IDs + sequence counter H2-5 / H2-9
Tamper-driven policy: tamper inputs must trigger a defined action (fail-secure vs fail-safe) and be auditable. Tamper inputs + policy engine Tamper source code, duration, action code, snapshot of power/auth state H2-3 / H2-7 / H2-12

Policy knobs (explicitly configurable, always auditable)

Fail-secure vs fail-safe Tamper action level Retry / lockout thresholds Low-battery behavior Update allow/deny states
Goals → Blocks → Evidence Anchors Goals (Requirements) Unauthorized actuation must be prevented Rollback to insecure firmware must be rejected Biometric templates protected as stored assets Tamper awareness policy actions must be logged Owning Blocks SE + Secure MCU boot state • counter Actuator Enable Path EN • power gate Power Policy UVLO • no-write NVM + Audit Log ID • reason • seq Inputs (HMI + Tamper) → Policy Engine source code • action code Evidence Anchors ① Boot state code ② Monotonic counter ③ Reason + sequence
Figure F3. Requirements map directly to owning blocks and to three evidence anchors (boot state, counter, reason/sequence). · Cite this figure
H2-4 · Secure Element & Secure Boot Integration

Secure Element & Secure Boot Integration (Practical wiring + lifecycle)

This section focuses on what engineers actually integrate: bus choice, reset/IRQ wiring, rail strategy, and the device lifecycle from factory provisioning to normal operation and recovery. The goal is a boot/identity system that remains correct under sleep-heavy operation and actuation-burst power stress.

Physical integration checklist (wiring + rails)

  • Connectivity: choose I²C (fewer pins, shared bus) or SPI (clear timing, higher throughput) based on wake model and bus robustness needs.
  • RESET line: define a deterministic reset sequence that survives brownouts; ensure default states cannot enable actuation.
  • IRQ/INT line: allow the SE to signal completion/events without polling (saves power, improves determinism).
  • Rails: ensure the SE has a clean rail and known behavior during actuation bursts; if a backup/keep-alive rail exists, define what it preserves (conceptual).
  • ESD awareness: exposed keypad/metal housing increases transient risk; bus lines need protection and controlled return paths (details later in protection chapter).

Key material categories (conceptual, implementation-agnostic)

  • Device identity: the lock’s hardware identity used to attest “which unit” is making decisions.
  • Storage-protection assets: assets that protect sensitive stored data (e.g., template metadata boundary), with integrity outcomes that can be logged.
  • Update-authorization assets: assets that determine whether an update state is accepted or rejected (policy-driven outcomes, not algorithm discussion).

Provisioning flow (factory) + first-boot states

  • Unprovisioned: device starts in a restricted state (no actuation) until provisioning completes and is verified.
  • Provisioned: identity/policy assets are present; the system transitions to normal operation and initializes the audit chain (sequence counters).
  • First-boot checks: verify provisioning status flags, schema versions (if used), and monotonic counters before allowing actuator enable.
  • Failure policy: partial provisioning or verification failure forces a recovery path and emits a reason code for service tools.

Anti-rollback counters (behavior-level rules)

  • Where it lives: store the monotonic/anti-rollback counter in a protected boundary (e.g., SE-owned or protected record), not in an easily overwritten config region.
  • When it updates: update the counter only after a verified transition to a “good” state (two-step: write → verify → commit).
  • Low-voltage rule: if the system is inside a brownout-risk window, block counter updates and record “no-write” reason to avoid corruption.
  • What it proves: any attempt to boot a lower/incompatible state results in a reject/recovery boot state with an auditable reason code.

Evidence hooks (minimum set): read (1) boot state code, (2) provisioning status flag, and (3) monotonic counter value. If any indicates reject/recovery, actuator enable must remain blocked and the reason must be logged.

Lifecycle States + Safe Transitions Boot & Provisioning State Machine Unprovisioned actuation blocked status flag = 0 Provisioned assets present status flag = 1 Normal authorize → enable audit seq advances Update staging slot verify → commit Recovery reject / repair provision + verify first-boot checks enter update state verify OK → commit reject reasons: rollback / counter / verify fail / low-voltage NVM Slots (Concept) Slot A (Active) current known-good boot uses this Slot B (Staging) write + verify commit flag Protected Records monotonic counter provision flag ① Boot state code ② Provision flag ③ Monotonic counter
Figure F4. Lifecycle states and safe transitions with A/B slot concepts and protected records (provision flag + monotonic counter). · Cite this figure
H2-5 · Credential & HMI Front-Ends

Credential & HMI Front-Ends (Keypad + Fingerprint + Face Modules)

Treat every input as an AFE + interface + power-mode problem. The objective is stable capture under ESD/EMI and under actuator-burst power stress, with observable quality metrics and recoverable errors.

Keypad matrix scan (robustness under ESD/EMI)

  • Matrix scan reliability: define scan windows, debounce rules, and a deterministic wake behavior for low-power modes.
  • ESD entry point: keypad/housing are exposed; plan for transients that cause false presses, stuck lines, or spurious wake.
  • Ghosting control: detect illegal row/column combinations and record a specific error class (short/open/stuck).
  • EMI coexistence: avoid scanning during high-noise intervals (actuation, buzzer PWM, radio bursts) when feasible.

Fingerprint front-end (power sequencing + capture quality evidence)

  • Power sequencing: bring up sensor rail → interface ready → release reset → start capture. Brownout recovery must return to a known state.
  • Shield/guarding mindset: prioritize stable capture over maximum sensitivity; treat ESD and surface coupling as primary disturbances.
  • Template storage boundary: template lifecycle events (add/remove/update) must be traceable with a result code and a sequence counter.
  • Quality must be measurable: capture attempts must output a compact quality metric and a failure reason code.

Face / IR / depth module (power gating + illuminator sync)

  • Default-off: keep the module power-gated by default; wake only for an authenticated capture window to reduce leakage and attack surface.
  • Illuminator sync as a local driver: treat IR/LED illumination as a pulsed load; synchronize illumination to capture windows and log its state.
  • Privacy-by-design signals: drive local indicators (LED/buzzer) and emit a log bit when the sensor/illum path is active.

Local indicators (LED / buzzer / haptics)

  • Drive + EMI: PWM and switching edges can corrupt matrix scans and sensor captures; keep indicator timing and actuation windows well-defined.
  • Power cost: indicator bursts should not coincide with the most power-stressed events unless necessary.
  • Traceability: indicator actions should be correlated to the event reason (success / fail / tamper / low-batt).

Evidence hooks (minimum observability set)

Input Key metrics Error / reset evidence Waveform anchors
Keypad matrix scan success rate, debounce rejects, wake source scan error counter (open/short/stuck), ghosting counter ROW/COL lines, IRQ/wake pin
Fingerprint capture quality metric, attempt counter capture fail code, sensor reset reason sensor rail, reset/IRQ
Face/IR/depth capture window duration, illum state module timeout code, power-gate retry counter illum rail pulse, module rail
Indicators action code, duration rate-limit counter (if used), overlap flag PWM lines, supply droop during burst
Scan error counters Capture quality metrics Reset reason codes Power-gate retries Indicator overlap control
Input Front-Ends (AFE + Power Modes + Evidence) Credential & HMI Inputs Keypad Matrix ROW/COL scan • debounce ghosting detect • ESD entry IRQ / WAKE Fingerprint Module power seq • reset/IRQ shield/guard • ESD Quality metric Reset reason Face / IR / Depth power gating • capture window illum sync (local driver) ILLUM_DRV PRIV_IND Lock MCU / Policy Interfaces GPIO • I²C/SPI • IRQ Power Modes OFF • STBY • CAPTURE Evidence Counters scan_err • quality • reset_reason Rails VBAT battery input PMIC mode control HMI_RAIL keypad/LED SENS_RAIL finger/face ILLUM_RAIL IR/LED load Evidence Anchors ① scan_err / ghosting counters ② capture quality + fail codes ③ reset reasons + power-gate retries
Figure F5. Input front-ends as AFE + interface + power-mode, with explicit rails and evidence anchors. · Cite this figure
H2-6 · Actuator Drive

Actuator Drive (Motor / Solenoid / Latch) — Power Electronics Inside a Lock

Actuation is the most common failure hotspot: it combines high peak power, transients, EMI, and mechanical uncertainty. Design must be hardware-first with current-waveform evidence and auditable thresholds.

Actuator types (only what impacts the controller)

  • DC motor + gearbox: large start-up surge, strong coupling between VBAT droop and speed; current signatures are highly diagnostic.
  • Stepper motor: phase-current control dominates; missed steps/jam must be inferred from current/time behavior (conceptual).
  • Solenoid pulse drive: pulse energy and freewheel path define heat/EMI; timing must be bounded and logged.

H-bridge / driver topology (energy paths matter)

  • Enable gating: driver EN must be default-off and only asserted after authorization and interlocks are satisfied.
  • Freewheel paths: define where energy flows during PWM off-time (recirculation) and during shutdown (flyback behavior).
  • Current sensing: sample current where it can be trusted during transients; align sampling windows to PWM state and to motion phases.
  • Rail coupling: actuation bursts can pull rails into brownout; define a policy to avoid “reset → retry storm”.

Stall / jam detection (behavior-level, evidence-based)

  • Current signature check: compare the observed waveform to expected phases (startup peak → plateau → decay). Use minimal, auditable features.
  • Timeout bound: if end-stop/position is not reached within a defined window, abort and log the reason.
  • Back-EMF / speed sampling (if available): take a small sampling window to detect “energy without motion” behavior (conceptual).
  • Retry policy: limit retries, separate “recoverable friction” from “hard jam” by signature + counter.

Safety interlocks (do not energize blindly)

  • Door / bolt position sensors: verify state before and after actuation; record mismatch as a diagnosable code.
  • Clutch / end-stop feedback: treat end-stop as an interlock event, not as “normal overcurrent”.
  • Abort conditions: low-voltage, overcurrent beyond threshold, excessive duration, or inconsistent sensor states.

Evidence hooks (what to record + what to probe)

Evidence Log fields Waveform anchors Use case
Current golden patterns actuation_result_code, stall_detect_code, threshold_profile_id motor current vs time, driver EN Distinguish normal vs jam
Retry counters retry_counter, last_abort_reason VBAT droop during retries Prevent retry storms
Interlock mismatches door_state, bolt_state, mismatch_code sensor lines + EN edge Field diagnosis
Brownout interactions uvlo_flag, min_rail_during_burst, abort_code VBAT, 3V3/logic rail Root-cause reboots
H-bridge energy paths Current sensing windows Jam signature codes Interlock mismatch logs Brownout-safe abort
Actuator Drive + Sensing + Jam Detection (Evidence First) Lock MCU Control DIR • PWM • EN Interlocks door • bolt • end-stop H-Bridge / Driver Energy Paths HS_A HS_B LS_A LS_B LOAD motor / solenoid freewheel flyback Current Sense ADC / comparator EN Gate default-off Diagnostics Jam Detector signature + time + (EMF window) Logs stall_code • retry abort_reason Current “Golden Patterns” (Minimal Callouts) Normal peak → plateau → decay Jam / Stall high plateau + timeout Low Battery current + rail droop ① motor current + EN ② VBAT + logic rail ③ stall_code + retry
Figure F6. Driver energy paths + current sensing + jam detection with waveform-based evidence anchors. · Cite this figure
H2-7 · Power Tree & Low-Power Design

Power Tree & Low-Power Design (Battery Life Without Bricking During Unlock)

A door lock is a sleep system with rare high-power actuation bursts. The design goal is not only long battery life, but burst stability, no-write zones under low voltage, and an auditable safe-retry policy.

Battery sources & what matters electrically (AA vs Li)

  • Internal resistance drives burst droop: cold/aging increases droop risk even when “battery %” appears high.
  • Voltage platform differs: rail thresholds (warning / no-write / UVLO) must be defined per battery class.
  • Evidence-first health metrics: track voltage under burst + estimated internal resistance over time buckets.

Rail grouping (design for power gating and fault containment)

  • AON rail: minimal wake logic + time base + critical counters (kept stable across sleep).
  • AUTH / Secure rail: authentication chain and decision path (enabled only when needed).
  • HMI / Sensor rail: keypad + fingerprint + face/IR modules (power-gated by window).
  • ACT rail: motor/solenoid drive domain (short, high current; strongest EMI + droop coupling).

Peak power budgeting (actuation burst without resets)

  • Define the burst envelope: expected peak current, max duration, and a hard abort time bound.
  • Hold-up and soft-start: use controlled ramp + limited inrush so the battery does not collapse at the start edge.
  • Scheduling matters: avoid stacking high-current events (illumination + motor + radio TX) in the same window unless required.

Brownout strategy (UVLO + no-write zone + safe retry)

  • Three zones: warning (reduced writes) → no-write zone (write-protect active) → UVLO/abort (actuation stop).
  • Write-protect behavior: block all non-essential NVM writes during low voltage; log the reason code.
  • Safe retry policy: rate-limit retries, enforce minimum recover time, and stop retrying when IR estimate is too high.
  • Reset-to-retry storm prevention: if a brownout reset occurs during actuation, switch to a conservative mode with fewer bursts.

Fuel gauge & health metrics (what to log)

Metric / flag How it is used Captured when Anchor
min_rail_during_unlock Correlates failures to droop; validates hold-up and soft-start Actuation window ①
brownout_flag / uvlo_flag Separates “logic reset” from “mechanical jam” classes Any reset / abort ②
battery_ir_est Drives safe retry limits and cold/aging behavior During burst + temperature bucket ③
no_write_zone_reason Explains missing logs/templates updates under low voltage Before/after NVM operations ②
abort_code + retry_counter Proves policy decisions in field incidents Abort / retry loop ①
Rail grouping Burst budgeting No-write zones Safe retry policy Min-rail evidence
Power-State Timeline (Sleep System + Rare Burst) State Sequence SLEEP WAKE AUTHENTICATE ACTUATE LOG RETURN SLEEP Rails & Current (Conceptual) AON_RAIL AUTH/SENS_RAIL ACT_RAIL BURST CURRENT always-on (wake + timebase) windowed enable actuation burst peak → settle NO-WRITE UVLO ① min_rail_during_unlock ② no-write zone reason + brownout flags ③ battery_ir_est (bucketed) Policy Checklist • gate ACT_RAIL • hold-up for logging • no-write under low V • retry rate-limit • log min rails + abort codes • avoid stacking radio/illum/motor bursts
Figure F7. Sleep-to-burst timeline with rail windows, current burst, and evidence anchors (min rail, no-write, IR estimate). · Cite this figure
H2-8 · Low-Power Wireless & Coexistence

Low-Power Wireless & Coexistence (BLE/Thread/Sub-GHz as Hardware Constraints)

Wireless design is primarily a wake model + antenna environment + EMI coexistence problem. Inside a metal door, performance is dominated by placement constraints and actuation-noise coupling, not protocol features.

Radio choice matrix (power + latency + range + wake model)

Radio class Best fit Hardware constraints Evidence hooks
BLE Short-range + fast user interaction Windowed listening/advertising; TX bursts must not overlap motor noise RSSI, retry count, overlap flag
Thread / 2.4G mesh Always-on ecosystem, low duty-cycle operation Antenna detune in metal; scheduling and filtering against actuation bursts link margin proxy, retries vs motor markers
Sub-GHz Better penetration/range, sparse traffic Different antenna footprint; wake model must be explicit to avoid leakage RX/TX self-test flags, RSSI buckets

Antenna constraints inside metal doors (principles only)

  • Keepout zone: reserve a stable space around the antenna; avoid battery/motor/metal brackets in the near field.
  • Ground reference discipline: define where RF ground is “quiet” versus where motor return current flows.
  • Placement over tweaks: placement and routing typically outperform “more matching” when metal detuning dominates.

Coexistence with motor EMI (noise paths + mitigations)

  • Noise sources: H-bridge edges, commutation events, burst current ripple.
  • Paths: conducted (VBAT droop), ground return coupling, radiated into antenna zone.
  • Mitigations: scheduling isolation, rail filtering, shielding/partitioning, and return-path control.
  • Policy: define “radio quiet windows” during critical link events when actuation is active.

Commissioning modes vs normal modes (power gating + security posture)

  • Commissioning: longer scan/advertise windows are acceptable but must be time-bounded and explicitly logged.
  • Normal mode: short wake windows, strict rate limits, and clear gating conditions for radio power domains.
  • Mode flags: track commissioning flag, self-test flag, and the time budget applied.

Evidence hooks (link health correlated to motor activity)

Metric Meaning Correlate with Anchor
RSSI buckets Environment/placement sensitivity and detuning clues door type + install orientation ①
packet_retry / crc_fail Link stress (interference or coexistence failure) motor_activity_marker ②
coexistence_overlap_flag Radio windows overlapped by actuation bursts actuation timestamps ②
rf_self_test_mode_flag Installation/maintenance posture without protocol deep dive commissioning_mode_flag ③
Wake model Antenna keepout Motor EMI paths Scheduling isolation RSSI vs retries
RF + Motor EMI Coexistence (Paths → Mitigations → Evidence) Actuation Domain H-Bridge switch edges / PWM Motor Loop burst current path Noise Sources • conducted droop • ground coupling • radiated field Noise Paths Conducted VBAT droop → rails Ground / Common-mode return-path coupling Radiated field into antenna zone RF Domain Mitigations schedule • filter • shield return-path control Radio Module windowed RX/TX mode flags Antenna Zone keepout • metal constraints KEEP-OUT MATCH Evidence Hooks (Correlate Link Health to Motor Activity) ① RSSI buckets ② retries / crc_fail + motor_activity_marker ③ commissioning/self-test mode flags
Figure F8. Coexistence view: actuation noise paths → RF mitigations → antenna zone, with evidence hooks for correlation. · Cite this figure
H2-9 · NVM, Templates & Audit Logs

NVM, Templates & Audit Logs (What Must Persist, How to Avoid Corruption)

Door locks need durable, auditable storage: credentials and counters must remain consistent through resets, and audit logs must be appendable without corruption. This chapter focuses on traceability + atomic commit rather than media-style “recording integrity”.

Partitioning: classify assets by risk and write pattern

  • Credential metadata: user IDs, roles, validity windows, enrollment status (read-heavy, low write, must not drift).
  • Templates vault: fingerprint/face template assets stored encrypted-at-rest (concept) with explicit wipe semantics.
  • Monotonic counters: anti-rollback and accountability counters (must never go backward; write frequency managed).
  • Audit log ring: append-only event stream with sequence numbers (write-heavy; power-fail tolerant).

Atomic updates: A/B records + last-good pointer

  • A/B record rule: write the inactive record, validate with CRC/ECC, then flip a valid flag or update a last-good pointer.
  • Power-safe commit: commit steps are gated by a “power OK” condition; low voltage forces a no-write decision and logs the reason code.
  • Recovery behavior: on reboot, select the record with a valid flag + highest sequence, otherwise fall back to last-good.

Integrity checks: CRC/ECC (high level) + evidence counters

  • CRC: detects partial writes and corrupted payloads; failures increment a counter for field correlation.
  • ECC (if available): correctable vs uncorrectable counts separate “noise/soft errors” from “structural storage failure”.
  • Bad-record handling: never “guess”; select last-good and log the fault class.

Wear strategy (high level): avoid hot-spot writes

  • High-rate data (logs/counters): rotate records (ring) or spread updates to avoid burning a single address.
  • Counter policy: commit counters in bounded steps (or via aggregated updates) while keeping monotonic behavior.
  • Power linkage: storage writes must respect no-write zones defined by the power policy (brownout-safe).

Accountability: minimum audit event set

Event Minimum fields (concept) Why it matters Anchor
Unlock attempt event_id, seq, timestamp/tick, auth_result_code, method, power_marker Proves success/failure and reason under field disputes ①
Tamper event event_id, seq, sensor_source, state_change, mode_flag Separates physical tamper from normal service actions ②
Low-battery / brownout event_id, seq, min_rail, uvlo_flag, no_write_reason, retry_counter Explains aborted operations and missing writes ③
Failed actuation event_id, seq, stall/jam_code, current_signature_bucket, retries Separates mechanical jam from electrical reset ④

Evidence hooks (field correlation)

  • last_good_record_pointer: confirms the last completed atomic commit.
  • crc_fail_count / ecc_*_count: correlates storage faults vs power faults.
  • monotonic counters: prove non-regression and bind logs to an ordering chain.
  • audit log sequence: reveals gaps due to power gating or no-write zone decisions.
A/B commit Last-good pointer CRC/ECC counters Audit sequence Selective wipe semantics
NVM Map + Atomic A/B Commit (Traceable & Power-Fail Tolerant) NVM Partition Map (Concept) CRED META user index • roles • status version index map TEMPLATE VAULT encrypted-at-rest (concept) selective wipe MONO COUNTERS anti-rollback • audit seq monotonic_counter AUDIT LOG RING append-only • sequence log_seq + event_id Key hooks: last_good_ptr • crc_fail_count • audit_seq • monotonic_counter A/B Commit Flow SLOT A payload crc/ecc valid SLOT B payload crc/ecc valid Commit Steps (High Level) 1) write inactive payload 2) write CRC/ECC 3) set VALID flag (last) 4) update last_good_ptr 5) log seq + result_code power fail → fallback ① last_good_ptr ② crc_fail_count Audit Chain • audit_seq increments per event • monotonic_counter never decreases • gaps imply no-write or power-fail • templates stored as protected assets (encrypted-at-rest concept) with explicit wipe semantics
Figure F9. NVM partitioning and an atomic A/B commit model with last-good pointer and integrity counters for field traceability. · Cite this figure
H2-10 · Field Update & Serviceability

Field Update & Serviceability (Safe Update Without Scope Creep)

Field updates must be rollback-safe, power-gated, and observable. The focus is a device-local state machine: how updates are entered, how power conditions gate writes and commits, and how results are logged for audit.

Update entry points (different triggers, one state machine)

  • Local trigger: maintenance action inside the lock (time-bounded and logged).
  • Service tool trigger: controlled maintenance interface (policy-defined exposure, high level).
  • Radio-initiated trigger: update request that transitions into the same on-device update states (no backend discussion).

Rollback-safe slotting (concept) + commit rules

  • Inactive-slot write: write the non-active slot; verify integrity before switching.
  • Commit gating: switching active slot requires power OK + verified image + logged result code.
  • Post-boot self-check: after reboot, a minimal health check either confirms the new slot or triggers rollback.

Power gating rules during update (prevent bricking)

  • No actuation bursts during write/commit: the actuator domain must remain gated (or in a safe posture) while updating.
  • No-write zone linkage: low voltage immediately pauses or aborts update writes with a power-fail marker.
  • Resume policy: if permitted, resume from the last validated step using last-good pointers and result codes.

Service port exposure policy (high level) + reset semantics

  • Exposure policy: define when a service interface can be enabled (e.g., maintenance mode), and log entry/exit events.
  • Factory reset vs credential wipe: distinguish “configuration reset” from “credential/template removal” and audit both.
  • Credential wipe: must record a dedicated event code and update template vault metadata consistently.

Evidence hooks: what must be observable in the field

Signal / code Meaning Captured at Anchor
update_result_code Success/failure classification for audit and service triage End of update attempt ①
rollback_reason Why the device returned to the previous slot Post-boot check / recovery ②
power_fail_marker_during_update Indicates power gating stopped a write/commit step Write/commit gates ③
slot_state (active/inactive) Proves which image is active and which was being updated All state transitions ④
State machine Power OK gates Rollback-safe slots Result codes Reset vs wipe
Update State Machine (Power-Gated, Rollback-Safe, Observable) IDLE normal operation ENTER UPDATE local / service / radio VERIFY PRECONDITIONS power OK • posture OK WRITE INACTIVE slot A/B POWER_OK GATE (no-write if low V) VERIFY IMAGE integrity checks COMMIT SWITCH set active slot POWER_OK GATE (commit) REBOOT handoff to new slot POST-BOOT SELF CHECK pass → normal; fail → rollback ROLLBACK restore last-good slot RECOVERY MODE service posture + logs RETURN TO NORMAL OPERATION clear flags • resume policy fail → rollback_reason Logging Points & Evidence Hooks • log update_result_code at end of attempt • log power_fail_marker at write/commit gates • log rollback_reason when reverting • persist slot_state across transitions (active/inactive) • distinguish factory reset vs credential wipe with dedicated event codes ① update_result_code ② rollback_reason ③ power_fail_marker ④ slot_state
Figure F10. Update state machine with power OK gates, rollback path, and mandatory logging points for field observability. · Cite this figure
H2-11 · Validation Plan

Validation Plan (Test Matrix That Proves Reliability + Security Posture)

Validation is most useful when each test produces field-usable evidence: rail minima during unlock, actuator current signatures, RF retry statistics correlated with motor events, and storage counters that explain gaps. This plan is structured as Test → Instrument/Fixure → Pass/Fail → Logged evidence.

Reference parts (example MPNs used in validation & debug)

Use any equivalent parts; these MPNs are common, well-documented reference options.

Block Example MPNs (choose per design) Why useful in tests
Secure element Microchip ATECC608B · NXP SE050 · Infineon OPTIGA™ Trust M (SLM 9670/9672 family) Provisioning state checks, secure boot status codes, key storage lifecycle
Secure MCU/MPU ST STM32L5 / STM32U5 · NXP LPC55S6x · Renesas RA4/RA6 security-capable families Measured boot logs, update slot control, reset-reason taxonomy
BLE/Thread radio Nordic nRF52840 / nRF5340 · TI CC2652R · Silicon Labs EFR32MG21 RF retry/drop correlation with motor events, coexistence experiments
Sub-GHz option TI CC1312R · Silicon Labs EFR32FG23 Range vs battery profiling in installed environments
Motor / solenoid drive TI DRV8833 · Toshiba TB6612FNG · TI DRV8876 (DC) · TI DRV110 (solenoid) Current signature capture, stall/jam detection thresholds, retry behavior
Current sense TI INA180 / INA181 · ADI AD8418 (automotive-grade option) Actuation waveform evidence (peak/RMS bucket), stall discrimination
Buck/boost & load switch TI TPS62745 (ultra-low IQ buck) · TI TPS61099 (boost) · TI TPS2291x (load switch) Sleep current profiling, burst sag control, no-write zone gating
Fuel gauge ADI/Maxim MAX17048 / MAX17055 · TI BQ27441 Battery IR estimate, low-battery flag validation, retry budgeting
NVM Winbond W25Q32JV (SPI NOR) · Microchip 25AA1024 (SPI EEPROM) · Infineon FM24CL64B (FRAM) Power-fail write tests, CRC/ECC counters, last-good pointer recovery
ESD/Surge protection Nexperia PESD5V0S1UL (ESD) · Littelfuse SMBJ58A (TVS) · ST SMF05C (multi-line TVS array) Outdoor transients on keypad/sensor lines, reset reason + log continuity checks

Compact validation matrix (test → instrument → pass/fail → logged evidence)

ID Test Instrument / fixture Pass / fail (behavior) Logged evidence (must persist)
P1 Sleep current + leak sweep across temperature DMM + uA meter, thermal chamber, controlled battery emulator Sleep stays within budget; no unexpected wake sources sleep_current_bucket, wake_source_code, temperature_bucket
P2 Wake + authenticate + actuation burst power profile Scope + current probe + rail sense points No rail collapse; actuation completes without brownout min_rail_during_unlock, brownout_flag, actuation_time_ms
P3 Worst-case retries under low battery (policy verification) Battery emulator with programmable IR, mechanical load fixture Safe retry policy triggers; no bricking; no-write zone respected safe_retry_policy_code, no_write_reason, uvlo_trip_count
A1 Endurance cycles (temperature × load × speed) Cycle rig, torque/load fixture, thermal chamber Stable success rate; no runaway retries; no thermal cutouts unlock_success_rate_bucket, retry_counter, jam_code_count
A2 Stall/jam detection sensitivity (signature-based) Current sense capture + controlled jam fixture Jam detected consistently; safe stop; no damaging overdrive stall_or_jam_code, current_signature_bucket, stop_action_code
A3 Door-sensor interlocks (position/reed/hall) Sensor stimulus jig, event injection No unsafe actuation when sensors disagree sensor_consistency_flag, interlock_trip_code, event_seq
R1 RF range & retries in installed environments (metal doors) RF test walk, RSSI logger, install fixtures (door/frame) Commissioning succeeds; stable reconnect behavior rssi_bucket, pkt_retry_count, link_drop_count
R2 Motor EMI coexistence (RF during actuation bursts) RF logger + motor event marker correlation Retries do not spike beyond policy; no disconnect loops pkt_retry_count, motor_event_marker, coexistence_mode_flag
S1 Power-fail during log append (atomic A/B behavior) Power interrupt jig, repeated cut tests Reboot selects last-good; no silent corruption last_good_ptr, crc_fail_count, audit_seq_gap_count
S2 Power-fail during template/metadata update Power interrupt jig, template update stress Template vault remains consistent; wipe semantics preserved template_meta_version, update_result_code, crc_fail_count
S3 Update interruption (write/commit gating) Power cut at write/commit gates Rollback-safe; recovery path logged slot_state, power_fail_marker_during_update, rollback_reason
T1 ESD on keypad/fingerprint window + sensor lines ESD gun, monitoring scope, reset-reason capture No unauthorized actuation; controlled reset behavior reset_reason, tamper_event_code, unlock_denied_reason
T2 Surge/EFT-like disturbances on long lines (high level) Surge/EFT setup (as applicable), line coupling fixture System recovers; logs remain explainable audit_seq, watchdog_trip_count, crc_fail_count

Recommended instruments (example models)

  • Oscilloscope: Tektronix MDO3xxx / Keysight MXR/InfiniiVision class equivalents
  • Current probing: Tektronix TCP0030A + TCPA300 (or equivalent current probe/amplifier)
  • Power source: programmable supply or battery emulator with adjustable internal resistance
  • RF logging: BLE/Thread sniffer or test dongle + time-correlated motor markers
Test → Evidence Installed RF Power-fail recovery Actuation signatures Reset reason taxonomy
Validation Coverage Map (Power · Actuation · RF · Storage · Tamper) POWER P1 P2 P3 Evidence: min_rail • uvlo • no_write Focus: sleep current + burst sag ACTUATION A1 A2 A3 Evidence: current_sig • jam_code • retries Focus: endurance + stall discrimination RF (INSTALLED) R1 R2 Evidence: rssi • retries • motor_marker Focus: metal door + EMI coexistence STORAGE (NVM + LOGS) S1 S2 S3 Evidence: last_good_ptr • audit_seq • crc_fail Evidence: slot_state • power_fail_marker • rollback_reason Focus: power-fail tolerant commits + explainable gaps TAMPER & POSTURE T1 T2 Evidence: reset_reason • tamper_event • denied_reason Focus: no unsafe actuation + recoverable behavior Evidence Legend (short, field-friendly) min_rail · brownout_flag · current_sig · jam_code · rssi/retries · motor_marker · last_good_ptr · audit_seq · crc_fail · slot_state Rule: pass/fail is insufficient unless evidence persists in logs and is explainable after resets and power cuts.
Figure F11. Validation coverage map showing domain tests (P/A/R/S/T) and the mandatory evidence hooks that make results field-actionable. · Cite this figure
H2-12 · Field Debug Playbook

Field Debug Playbook (Symptom → Evidence → Isolate → Fix)

Fast diagnosis uses two measurements plus persisted evidence. This playbook prioritizes: rail minima during unlock, actuator current signatures, RF retries correlated with motor events, and storage counters that explain missing or inconsistent logs.

Quick evidence toolkit (minimal gear)

  • 1× rail capture: battery rail or actuator rail at a defined sense point
  • 1× actuator evidence: current signature (sense resistor + INA180/INA181 or current probe)
  • 1× RF evidence: retries/drop counters + motor event marker timestamp
  • 1× storage evidence: audit_seq, crc_fail_count, last_good_ptr, slot_state

Recommended debug parts (example MPNs)

  • Current sense amplifier: TI INA180 / INA181 (fast current signature capture)
  • Motor driver reference: TI DRV8833 / Toshiba TB6612FNG (repeatable waveform behavior)
  • NVM references: Winbond W25Q32JV (SPI NOR) · Infineon FM24CL64B (FRAM)
  • ESD protection references: Nexperia PESD5V0S1UL · ST SMF05C

Repeatable symptom recipes (copy/paste format)

Symptom First 2 measurements Discriminator (proves root class) First fix (high level)
Unlock fails only in cold min_rail_during_unlock + actuator current signature Rail droop + longer actuation time indicates battery IR + mechanical load Adjust UVLO/no-write gates; review hold-up; retune jam thresholds for temperature
Motor spins but latch does not move actuation_time_ms + current_signature_bucket High current plateau or repeated peaks indicates jam/overload vs control logic Update stall timeout; validate clutch/position sensor; cap retries; log jam_code
Random reboot during unlock battery rail droop + reset_reason Brownout reset aligns with peak current; storage gaps indicate no-write zone Raise rail margin (buck/boost policy); gate actuation under low V; enforce write-protect
BLE drops only during motor actuation pkt_retry_count + motor_event_marker Retry spikes aligned with motor marker indicates EMI/coexistence Improve return path/filtering; schedule RF windows; shielding/ground keepout review
Fingerprint reads degrade over time capture_quality_metric + sensor reset reasons Quality drops without power faults suggests contamination/ESD damage vs timing Verify ESD protection; validate sensor power sequencing; log quality + resets consistently
Auth success but actuator never enables enable_signal state + audit log event codes Log shows policy deny/interlock vs missing event implies storage/power gating Check interlocks (door sensor); confirm safe posture; ensure event logging survives reset
Logs missing or out of order after battery swap audit_seq + crc_fail_count Sequence gaps with crc failures indicate interrupted commits Strengthen atomic A/B commits; commit gating; increase last-good pointer robustness
Update sometimes bricks devices slot_state + power_fail_marker_during_update Power-fail marker at write/commit gate indicates insufficient update power budget Disable actuation during update; enforce power OK gates; implement rollback-safe switching

Evidence-first checklist (what must be captured before swapping parts)

  • Power: min_rail_during_unlock, brownout_flag, uvlo_trip_count
  • Actuation: current_signature_bucket, jam_code, retries, actuation_time_ms
  • RF: rssi_bucket, pkt_retry_count, link_drop_count with motor_event_marker correlation
  • Storage/update: audit_seq, crc_fail_count, last_good_ptr, slot_state, rollback_reason
Two-measurement rule Rail + current RF + motor marker Audit seq + CRC Rollback-safe updates
Field Debug Decision Tree (Unlock Fail → Evidence → Isolate → First Fix) UNLOCK FAIL / UNSTABLE capture: min_rail + current_sig + logs Rail droop / UVLO? min_rail_during_unlock Power class Evidence: brownout_flag • reset_reason First fix: power OK gates • hold-up • no-write Jam-like current? current_signature_bucket Actuation / load class Evidence: jam_code • retries • actuation_time First fix: stall timeout • interlocks • cap retries RF retries spike with motor? pkt_retry_count + motor_marker Coexistence / EMI class Evidence: retries • drops • coexist_mode First fix: return path • filtering • scheduling windows Logs consistent and explainable? audit_seq • crc_fail_count • last_good_ptr Storage / update integrity class Evidence: audit_seq gaps • crc_fail • slot_state • rollback_reason First fix: atomic A/B commit • power-fail markers • rollback-safe update min_rail current_sig retries + motor_marker audit_seq + crc_fail
Figure F12. Evidence-based decision tree that narrows unlock failures using rail droop, actuator signatures, RF retries, and storage integrity logs. · Cite this figure

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H2-13 · FAQs ×12

FAQs (Evidence-Based, Hardware-First)

Each answer uses a compact “what to check first” flow (rails, current signatures, retries, and persisted logs). It stays within this page boundary (no app/cloud/protocol tutorials) and maps back to chapters for quick navigation.

Secure boot enabled but unauthorized unlock still happens—where to look first?
Start with evidence, not assumptions. Verify the secure-boot state code and the authorization-to-actuation gate event (who asserted “enable”). Then confirm the actuator enable line is controlled by the intended trust domain (e.g., SE-backed decision) and that tamper/door-sensor interlocks can veto actuation. ATECC608B/SE050-style identity helps only if the enable path is strictly enforced and logged.
Maps to: H2-3 / H2-4 / H2-12
Battery shows “OK” but unlock reboots the lock—power tree or motor stall?
Measure two things: min rail during unlock and the motor current signature. If the rail dips or reset_reason indicates brownout, it’s power budgeting (battery IR, boost/buck limits, hold-up, UVLO policy). If rail is stable but current shows a long high plateau, it’s a stall/jam class (thresholds, timeouts, retry policy). Use INA180/INA181-style sensing to capture repeatable signatures.
Maps to: H2-7 / H2-6 / H2-12
Fingerprint works indoors but fails in winter—AFE noise, ESD damage, or condensation?
First compare capture quality metrics and sensor reset reasons across temperature. Condensation tends to produce unstable quality without consistent reset signatures; ESD damage often correlates with repeated interface faults or permanent quality degradation. Also confirm sensor power sequencing and shielding/guarding remain within spec at cold start. Add line ESD (e.g., PESD5V0S1UL) and log quality + resets to distinguish environment vs damage.
Maps to: H2-5 / H2-11 / H2-12
BLE pairing works, but commands time out during actuation—EMI or scheduling?
Correlate packet retries/timeouts with the motor_event_marker. If retries spike exactly during motor PWM or commutation, it’s EMI/coexistence (return paths, filtering, shielding, antenna keep-out). If retries drift unrelated to actuation timing, it’s wake/scheduling (radio duty cycle, host latency, power gating). Radios like nRF52840/CC2652 are robust, but motor loops can still inject noise unless layout and timing windows are enforced.
Maps to: H2-8 / H2-6 / H2-12
After firmware update, stored credentials seem “lost”—NVM map mismatch?
Check whether the new firmware reads the same NVM layout/version and selects the correct last-good pointer or slot. “Lost” often means metadata version mismatch or a failed commit that rolled back to a prior record set. Verify slot_state, update_result_code, and CRC fail counters. If using SPI NOR like W25Q32JV, prefer atomic A/B records with CRC and a monotonic audit sequence to keep recovery explainable.
Maps to: H2-9 / H2-10
Motor spins but latch doesn’t unlock—how to separate mechanical jam from drive weakness?
Capture the current signature + actuation time under the failing condition. A mechanical jam typically shows a sustained high current or repeated peaks with no position progress; weak drive/power limitation shows clipped current with rail sag or early cutoffs. Compare against a known-good “golden” waveform. With drivers like DRV8833/TB6612FNG (or higher-current DRV8876), tune stall thresholds and cap retries; always log jam_code and timeouts.
Maps to: H2-6 / H2-12
Random “tamper” alarms—switch bounce, EMI, or ground reference issues?
Start by logging tamper_event_code with timestamp plus a short window of related evidence: rail state and motor/RF activity markers. If alarms cluster during motor activity, suspect EMI coupling or ground bounce (return path, filtering, shield termination). If alarms occur at transitions without EMI, suspect debounce/thresholding or aging contacts. Add ESD/TVS on long lines and ensure tamper inputs have defined biasing; validate in H2-11 with repeatable injection.
Maps to: H2-3 / H2-7 / H2-12
Low sleep current in lab, high in the field—what are the top leakage culprits?
Field sleep current often rises from unexpected wake sources and leakage paths: moisture/contamination on keypad lines, misbiased sensors, radio scanning windows, or load switches not fully off. Log wake_source_code and sleep_current_bucket across temperature/humidity. Also check antenna/RF front-end biasing and any “commissioning mode” left enabled. Use a low-IQ buck (e.g., TPS62745) and hard power-gating where possible, but always verify by evidence, not design intent.
Maps to: H2-7 / H2-8
Audit log gaps after power loss—how should atomic logging work?
The log must be power-fail tolerant: write a new record to an alternate slot, include CRC, then flip a small “commit” pointer so reboot selects last-good_ptr. Gaps should be explainable via audit_seq and a power_fail_marker, not silent corruption. If CRC fails increase after swaps, tighten commit gating (no-write zone under low rail) and validate with repeated power-cut tests. FRAM (e.g., FM24CL64B) can reduce wear concerns, but atomicity still matters.
Maps to: H2-9
Anti-rollback fails after board swap—where should counters live?
First determine whether rollback depends on a device-bound monotonic counter and whether the swap changed the storage of that counter (SE vs MCU flash vs external NVM). After swap, a counter that “moves” or resets breaks the policy. Prefer storing rollback state in tamper-resistant storage (SE such as ATECC608B/SE050 family) or a well-protected secure domain with clear update semantics, and log monotonic counter reads/updates during every firmware lifecycle transition.
Maps to: H2-4 / H2-9
Keypad misreads only when RF is active—scan timing or EMC coupling?
Correlate keypad scan error counters with RF activity markers and motor/RF duty windows. If errors peak when the radio transmits, it’s often coupling into high-impedance keypad lines (routing, return path, shielding, pull strengths). If errors follow scan timing changes, it’s debounce/ghosting/matrix drive behavior (drive strength, sampling phase, filtering). Add ESD/RC as needed, and validate in H2-11 with controlled RF duty cycles while logging scan_error_count and timing mode.
Maps to: H2-5 / H2-8
Unlock works but is slow—authentication latency, radio wake, or motor ramp?
Break latency into three segments using timestamps: wake/auth (SE/MCU decision), radio command/ack, and actuation (motor ramp + load). If auth time dominates, check secure-domain handoffs and provisioning state; if radio dominates, check duty cycle and wake model; if actuation dominates, check current signature and ramp limits. Log per-stage timestamps and compare across battery levels—slowdowns often track rail margin and load, not “software feel.”
Maps to: H2-2 / H2-6 / H2-8
Evidence-first Two-measurement rule Rail + current signature Retries + motor marker Audit seq + CRC
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