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Low-Jitter Clock Isolator (100s fs) for JESD/ADC/DAC

Low-Jitter Clock Isolator (100s fs) for JESD/ADC/DAC

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Core idea

This page delivers a single, end-to-end answer for [TOPIC]: what it is, how it works, and how to design it so bring-up and production pass criteria are predictable. It focuses on engineering decisions (architecture, key specs, design hooks, verification gates) to reduce trial-and-error and shorten debug cycles.

Low-Jitter Clock Isolator
A low-jitter clock isolator transfers timing signals across an isolation barrier while keeping additive RMS jitter in the 100s-fs class, enabling clean sampling clocks and deterministic sync for ADC/DAC and JESD clock paths.
This page focuses on jitter metrics, timing budgets, layout/PI/EMI knobs, and verification. Protocol details and general PLL theory are intentionally out of scope.
On this page

H2-1. What is a Low-Jitter Clock Isolator?

A low-jitter clock isolator transfers a clock or timing reference across an isolation barrier while adding a controlled amount of additive RMS jitter (measured over a defined integration band). It is used when timing quality is part of the system’s performance budget, not merely a logic-level connection.

When it is required
  • Sampling clock paths where SNR/ENOB can be jitter-limited (ADC/DAC sampling and reconstruction).
  • Deterministic sync paths where channel-to-channel skew and drift must be bounded for timing alignment.
  • Noisy isolation environments where common-mode events must not translate into clock-edge uncertainty.
Do not use it for
  • Low-speed GPIO-style isolation where timing quality does not matter.
  • Replacing a jitter cleaner/PLL function (phase-noise shaping is a different problem).
  • Fixing protocol/bring-up issues (e.g., JESD link training); only the clock quality budget is addressed here.
Data checkpoints (placeholders)
Additive RMS jitter target: ≤ X fs (integration band must match).
Budget ownership: isolator contribution ≤ Y% of total clock jitter budget (system-defined).
Clock Source XO / PLL Optional Jitter Cleaner Low-Jitter Clock Isolator Isolation Barrier Additive Jitter (RMS) ADC DAC JESD Device Skew / Drift
Scope guard: protocol details (JESD), general PLL theory, and ADC/DAC architecture are not expanded here.

H2-2. Why Jitter Matters: From Phase Noise to ENOB

In sampling systems, clock jitter translates directly into amplitude uncertainty. At higher input frequencies, the same RMS jitter produces a larger phase error, lowering the achievable SNR and ENOB. A jitter budget converts this into a measurable pass/fail constraint.

A practical SNR limit from RMS jitter
SNRjitter ≈ −20·log10(2π·fin·tj)
where tj is RMS time jitter and fin is the effective input frequency of interest.
Engineering interpretation (no statistics)
  • Random jitter: raises the noise floor; tends to be supply-noise, thermal, or broadband-coupling driven.
  • Deterministic jitter: creates repeatable timing modulation (often linked to switching rails, crosstalk, or periodic interference).
  • Implication: reducing supply ripple and controlling coupling paths often improves measured jitter more than changing “logic speed”.
Targets by example (placeholders)
• At fin=X1, to hold SNR≥Y1, require tj≤Z1.
• At fin=X2 (higher), the allowed tj tightens proportionally.
• At fin=X3 (highest), reserve additional margin for distribution + isolation + measurement uncertainty.
When jitter is not the bottleneck
If the system is already limited by analog noise, distortion, or quantization at the operating frequency, lowering jitter below that floor offers diminishing returns. The budget should be sized to the real performance limit.
Input Frequency (low → high) Allowed RMS Jitter (loose → tight) Higher fin → tighter tj f1 / tj≤Z1 f2 / tj≤Z2 f3 / tj≤Z3 SNR ≈ −20log(2π·fin·tj)
Scope guard: the equation provides a practical limit; real SNR also includes analog noise and distortion.

H2-3. Key Jitter Metrics & How to Read Datasheets

“Low jitter” is not a single number. Datasheets may publish additive RMS jitter, phase noise plots, period jitter, cycle-to-cycle jitter, TIE, duty-cycle distortion (DCD), and channel-to-channel skew. Device comparisons are valid only when definitions and integration limits match.

Metrics that must be pinned down
  • Additive RMS jitter: integrated over [fL, fH]; comparison requires the same band.
  • TIE / phase noise: useful for spectral diagnosis; ensure analyzer settings map to the same RMS figure.
  • Period / cycle-to-cycle: often correlates with short-term timing noise; can be sensitive to measurement method.
  • DCD: duty-cycle error can break downstream dividers or sampling assumptions even with low RMS jitter.
  • Skew & drift: channel mismatch and temperature drift dominate multi-device sync.
Common comparison traps
  • Mixing jitter numbers with different integration limits or filters.
  • Using a scope-based jitter estimate without fixture and probe control.
  • Ignoring DCD or output-format constraints (CMOS vs differential requirements).
  • Comparing typ numbers without checking max over temp, voltage, and aging.
Additive RMS Jitter Integrated [fL, fH] TIE / Phase Noise Spectral diagnosis Period / C2C Short-term variation DCD Duty-cycle error Skew / Drift Sync matching over temp Compare only if definitions + integration band match
Scope guard: general oscillator theory is not expanded; only the metrics needed for isolation budgeting are covered.

H2-4. Where Jitter Comes From Across the Barrier

Across an isolation barrier, jitter is shaped by internal edge processing plus the external environment. Power noise, common-mode injection, and crosstalk can modulate edge timing even when the waveform “looks clean” on a scope.

Actionable sources (knobs)
  • Intrinsic additive jitter: internal modulation/encoding/retiming paths contribute a baseline.
  • Power-supply noise: ripple and transient droop translate into phase/timing modulation.
  • Common-mode injection: barrier capacitance and CM events perturb thresholds and timing.
  • Crosstalk / SSO: adjacent toggling channels or rails add deterministic jitter components.
  • Reflections: poor termination creates time-uncertainty at threshold crossings.
Data checkpoints (placeholders)
Supply ripple: ≤ X mVpp at the isolator pins.
CM stress: tolerate dv/dt ≥ Y kV/µs without timing discontinuity.
Crosstalk control: keep adjacent aggressor switching-induced jitter ≤ N fs (system-defined).
Clock Isolator Barrier Intrinsic Additive Jitter Supply Noise Ripple / Droop CM Injection dv/dt Events Crosstalk SSO / Neighbors Edge Timing
Scope guard: EMI compliance methods are not exhaustively covered; only coupling paths relevant to clock jitter are included.

H2-5. Isolation Architectures for Low-Jitter Clocks

Low-jitter clock isolation may use capacitive or magnetic coupling with internal timing reconstruction. The architecture choice impacts additive jitter floor, immunity to common-mode events, temperature drift, and the achievable output formats (single-ended vs differential).

Architecture selection notes
  • Retiming vs transparent: retiming can bound jitter transfer characteristics but may reshape phase-noise components.
  • Differential support: native differential outputs reduce threshold sensitivity and can improve robustness.
  • CM immunity: high dv/dt immunity reduces transient edge perturbation in switching environments.
  • Channel matching: multi-lane clock distribution requires tight skew + drift, not only low RMS jitter.
Capacitive Isolation Barrier Low Power High Speed Jitter floor + CM injection control Magnetic / Inductive Barrier Robust CM Wide Temp Skew/drift + transient immunity focus
Scope guard: this section compares architecture impact on clock metrics; it does not catalog all isolator families.

H2-6. Timing Budgeting: Additive Jitter, Skew, Drift, Sync

A workable budget assigns limits to each contributor (source, conditioning, distribution, isolation, and measurement). It prevents “chasing jitter” blindly and clarifies which knob improves the pass/fail margin.

Budget structure (placeholders)
  • Total allowed RMS jitter: ≤ X fs (system target).
  • Isolation additive jitter allocation: ≤ Y fs (or ≤ Y% of total).
  • Skew (lane-to-lane): ≤ Z ps; Skew drift: ≤ N ps over temperature.
  • DCD: ≤ D% (or ≤ D ps equivalent) when downstream logic is duty-cycle sensitive.
Sync-specific guidance
  • Multi-device sync: skew + drift often dominate before RMS jitter does.
  • Measurement consistency: budget numbers are valid only if integration band and fixtures match the verification setup.
  • Allocation margin: reserve headroom for board-to-board variation and EMC stress conditions.
Source Condition Distribute Isolation Additive Measure Total jitter budget = X fs (allocate + margin)
Scope guard: this section covers budgeting logic; detailed protocol timing (e.g., JESD subclass rules) is out of scope.

H2-7. Signal Formats & SI Design: CMOS and Differential Clocks

Clock format selection (single-ended CMOS vs differential) determines sensitivity to threshold noise, reflections, and common-mode coupling. Signal integrity and termination choices can improve jitter margin without changing the isolator.

Format-driven guidance
  • CMOS: edge rate and reflections strongly affect crossing time; series damping often helps.
  • Differential: better rejection of common-mode shifts; requires controlled impedance and correct termination.
  • Fanout/load: confirm output drive and loading to avoid edge distortion and DCD growth.
Data checkpoints (placeholders)
Length mismatch (diff pairs): ≤ X mm (or ≤ Y ps).
Termination: within Z Ω of target impedance.
Edge control (CMOS): tune series R to meet rise/fall and jitter margin (system-defined).
CMOS Clock Driver R Load Series damping reduces reflections Differential Clock Driver Load Proper termination Control impedance + match lengths
Scope guard: interface standards are referenced only by signal behavior; protocol-level requirements are not expanded.

H2-8. Power Integrity for Clock Isolation

Clock isolation performance is often limited by local power noise rather than the isolator’s intrinsic jitter floor. Each side of the barrier must provide low impedance, clean decoupling, and controlled transient response.

PI rules that protect jitter margin
  • Local decoupling at pins: minimize loop area; prioritize high-frequency current paths.
  • Rail isolation: isolate the clock rail from high di/dt loads (switchers, drivers, IO banks).
  • Transient control: avoid droop during CM events (EFT/ESD) that can translate into timing slips.
  • Partitioned return: do not allow return currents to cross the isolation gap.
Data checkpoints (placeholders)
Clock-rail ripple: ≤ X mVpp (bandwidth specified).
PDN impedance: ≤ Y mΩ within critical band (system-defined).
Transient droop: ≤ N mV during worst-case switching/CM stress.
Clock Isolator Primary Clock Rail Secondary Clock Rail Decouple Decouple Switching Loads Keep noise away
Scope guard: detailed PDN simulation methods are out of scope; this section provides layout-ready PI constraints.

H2-9. Layout & Grounding Rules for Low-Jitter Isolation

Layout determines whether the isolation barrier behaves like a controlled boundary or a noise injector. The layout goal is to keep the clock’s return path local, prevent cross-gap currents, and isolate high di/dt loops away from the clock path.

Hard layout rules
  • Strict partition: primary and secondary copper must not overlap across the barrier region.
  • No return across gaps: avoid stitching capacitors or routes that create hidden cross-gap return paths.
  • Keep-out zone: maintain a clear corridor around the barrier and sensitive clock pins.
  • Short, controlled routes: keep clock traces short; avoid routing near switching nodes and dense IO bundles.
  • Place decoupling tight: shortest loop for each side’s rail and ground reference.
Data checkpoints (placeholders)
Decoupling distance: ≤ X mm from supply pins.
Keep-out width: ≥ Y mm around the barrier (per safety + EMC).
Clock route clearance: ≥ N mm from fast-switch nodes or aggressor bundles.
Primary Zone Secondary Zone KEEP OUT Isolator Cdec Cdec Clock route Clock route No return across gap
Scope guard: safety distances depend on system standards; this section focuses on jitter-relevant layout constraints.

H2-10. EMI, Barrier Capacitance, and Y-Cap Tradeoffs

Even with low additive jitter, common-mode current paths can inject noise that modulates clock thresholds. Barrier capacitance and optional Y-caps can reduce emissions in some cases but may create leakage and new coupling routes that hurt timing.

Practical tradeoffs
  • Lower barrier capacitance generally reduces CM current and emissions, improving robustness in noisy cabinets.
  • Edge-rate control can reduce EMI but must preserve downstream timing margins.
  • Y-caps: can improve EMI by providing a controlled CM return, but must respect leakage limits and avoid routing CM currents through sensitive clock references.
Data checkpoints (placeholders)
CM emission target: meet system EMI limits with margin M (test-defined).
Y-cap value: ≤ X nF (system-defined); leakage: ≤ Y µA (standard-dependent).
Timing stability under stress: no clock discontinuity during EFT/ESD events (pass criteria N events).
Primary Secondary Cbar Barrier Common-mode current path Optional Y-cap EMI improvement vs leakage & coupling
Scope guard: safety leakage limits are standard-dependent; link to the site’s Safety & Compliance page for normative limits.

H2-11. Validation & Production Test

Verification must reproduce the datasheet measurement intent: same integration band, controlled fixtures, and defined termination. The pass criteria should be measurable on the bench and repeatable across builds and stress conditions.

Measurement workflow
  1. Define jitter metric: additive RMS jitter and integration band [fL, fH].
  2. Control fixtures: termination, cable/connector quality, probe method, shielding.
  3. Separate contributors: measure source baseline, then add isolator, then add distribution load.
  4. Stress test: thermal corners + CM events (EFT/ESD) to ensure no timing discontinuity.
  5. Document: setup diagrams, analyzer settings, and acceptance tables for production repeatability.
Engineering Checklist (Design → Bring-up → Production)
  • Design gate: jitter budget table complete; integration band aligned; skew/drift requirements declared.
  • Design gate: clock format + termination strategy selected; route/partition rules applied.
  • Bring-up gate: baseline source jitter measured; isolator-added jitter measured with fixed setup.
  • Bring-up gate: stress checks (temp + EFT/ESD) show no timing discontinuity; record results.
  • Production gate: fixture and analyzer settings frozen; pass/fail limits stated as X/Y/N; certificates and reports archived.
Clock Source DUT Isolator Fixture Analyzer RMS + Band Define integration band [fL, fH] and keep it consistent Verify across temp + CM stress (EFT/ESD)
Scope guard: this section defines verification; compliance lab procedures vary by standard and are not fully replicated here.

H2-12. Applications & IC Selection

Applications (clock isolation use cases)
  • High-speed ADC sampling: prioritize lowest additive RMS jitter and clean clock-rail PI; validate across temperature.
  • Precision DAC clocking: control phase-noise sidebands and DCD; ensure termination and load do not distort edges.
  • JESD clock/SYSREF distribution: prioritize skew/drift matching across lanes; keep measurement and integration bands consistent.
  • Multi-board timing: treat isolation as one element in a full distribution budget; enforce repeatable fixtures and production gates.
IC Selection (decision flow with thresholds)
  1. Clock format: CMOS vs differential; confirm frequency range and output swing compatibility.
  2. Additive RMS jitter: ≤ X fs over [fL, fH] (same band used for verification).
  3. Skew/drift: lane matching ≤ Y ps; drift ≤ Z ps over temperature.
  4. DCD: ≤ N (percent or ps equivalent), especially if dividers or duty-sensitive logic is used.
  5. CM robustness: dv/dt immunity ≥ M kV/µs; confirm behavior under EFT/ESD stress.
  6. PI + layout feasibility: ensure clean local rails and partition rules can be met on the target PCB.
  7. Safety constraints: working voltage and creepage/clearance must meet system standards (link to Safety page on the site).
Format Jitter Skew/Drift DCD CM Robustness PI + Layout Safety Constraints Pass only if thresholds (X/Y/Z/N/M) are met under the same test definitions
Scope guard: selection focuses on clock isolation constraints; protocol-level constraints are referenced only as “timing needs”.

H2-13. FAQs (Troubleshooting & Acceptance)

Each answer follows a fixed structure: Likely cause / Quick check / Fix / Pass criteria (X/Y/N placeholders).
Datasheet says 200 fs, but the system measures 800 fs—what to check first?
Likely cause: jitter metric mismatch (integration band/filters) or fixture-induced noise dominates.
Quick check: lock the analyzer band to [fL, fH] and compare baseline (source only) vs isolator-added.
Fix: standardize measurement definition; improve termination/shielding; remove probe artifacts.
Pass criteria: additive RMS jitter ≤ X fs over [fL, fH] with repeatability σ ≤ Y fs over N runs.
Jitter is fine at room temperature but worsens at hot—why?
Likely cause: rail noise increases with temperature (regulator headroom/impedance) or skew drift is interpreted as jitter.
Quick check: measure rail ripple at isolator pins at hot; compare skew/drift across lanes.
Fix: strengthen local decoupling, isolate clock rail from switching loads, and tighten skew budget controls.
Pass criteria: jitter ≤ X fs and skew drift ≤ Y ps across N thermal points (min/room/max).
Works on bench, fails in cabinet—what is the first isolation-side suspect?
Likely cause: common-mode injection path or return-path mistake creates timing modulation under EMI.
Quick check: run an EFT/ESD-like stress and correlate jitter spikes with rail droop or CM events.
Fix: enforce partition/keep-out; reduce CM coupling; revise Y-cap placement/return routing if used.
Pass criteria: no timing discontinuity and additive jitter increase ≤ X fs under N stress events.
Changing termination improved the waveform but worsened jitter—how?
Likely cause: termination change altered edge crossing behavior (ringing/overshoot) and increased threshold timing uncertainty.
Quick check: compare crossing-time stability rather than peak-to-peak amplitude; check DCD and short-term jitter.
Fix: tune termination and series damping for stable crossings; keep loading within output drive limits.
Pass criteria: period jitter ≤ X ps and DCD ≤ Y (%, or ps eq.) across N loads.
Multi-lane clocks drift out of alignment over time—what is most often wrong?
Likely cause: lane-to-lane skew drift from temperature gradients or shared-rail noise coupling into timing.
Quick check: measure skew at cold/room/hot; check whether drift correlates with local rail ripple or load activity.
Fix: choose tighter drift specs; equalize thermal environment; isolate clock rails; improve lane symmetry.
Pass criteria: skew ≤ X ps and skew drift ≤ Y ps over N thermal points and activity states.
EFT testing causes sporadic “ticks” on the clock—what to do?
Likely cause: CM event triggers supply dip or threshold perturbation, producing a timing discontinuity.
Quick check: monitor isolator rails during EFT; look for droop/ground bounce coincident with ticks.
Fix: reinforce local decoupling; improve partition; add CM mitigation without routing CM currents through clock references.
Pass criteria: zero missing/extra edges in N EFT bursts; additive jitter increase ≤ X fs.
Adding a Y-cap reduced EMI but jitter got worse—why?
Likely cause: the Y-cap moved CM current into a path that modulates the clock reference/threshold.
Quick check: verify CM return routing; compare jitter with/without Y-cap and with different placement.
Fix: relocate or resize the Y-cap; route CM currents away from clock grounds; re-check leakage constraints.
Pass criteria: EMI passes with margin and jitter ≤ X fs; leakage ≤ Y µA per standard; stable across N conditions.
Differential clock isolation shows asymmetric edges—what is the fastest check?
Likely cause: incorrect termination/common-mode biasing or format mismatch causes DCD and edge asymmetry.
Quick check: confirm termination value/location; confirm receiver bias requirements; verify pair length match.
Fix: correct termination and bias network; enforce pair routing rules; validate DCD spec under load.
Pass criteria: DCD ≤ X and lane skew ≤ Y ps with output/load conditions held constant for N measurements.
Jitter spikes only at high digital activity—SI or power noise?
Likely cause: SSO/crosstalk or shared-rail noise couples deterministic jitter into clock edges.
Quick check: correlate jitter with IO switching and rail ripple; isolate clock rail temporarily if possible.
Fix: separate rails/returns; increase local decoupling; adjust routing to reduce aggressor coupling.
Pass criteria: jitter under max activity ≤ X fs and skew ≤ Y ps over N traffic profiles.
Phase-noise plot looks good, but integrated jitter fails—what mismatch is typical?
Likely cause: the integration limits or filters differ from the pass criteria; low-frequency noise may dominate RMS.
Quick check: re-integrate with the exact [fL, fH] and confirm instrument settings match the target definition.
Fix: standardize the jitter definition in documentation; update test scripts and fixture diagrams accordingly.
Pass criteria: integrated RMS jitter ≤ X fs over [fL, fH], verified on the frozen fixture with N repeats.
Define Metric Control Fixture Isolate Cause Stress Repeat until pass criteria is stable

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