Isolated UART / GPIO for PLC & Field I/O
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Scope Guard
In-scope: UART TX/RX + GPIO control/status across an isolation barrier: latency/skew budgeting, fail-safe states, power sequencing, EMC/ESD coupling, layout rules, and validation.
Out-of-scope: RS-485/CAN/LIN PHY details, I²C open-drain timing, USB/Ethernet compliance, isolated DC-DC topologies, and full safety standard clauses (link to sibling pages only).
H2-1. What Is Isolated UART / GPIO
Definition (engineering meaning)
Isolated UART / GPIO means carrying low-to-mid speed control, status, and service signals across an isolation barrier
without sharing ground, while keeping
timing margins predictable (latency/skew) and
outputs safe by default during power-up, power-down, or faults.
Typical use cases (why isolation is chosen):
- PLC / field I/O: noisy cabinet ground and transient events require barrier protection plus defined fail-safe states.
- Service UART (maintenance/debug): frequent handling and ESD exposure; isolation reduces ground-loop risk and protects the controller domain.
- Control board ↔ power/drive board: high dv/dt common-mode switching can inject noise unless the barrier and layout control the coupling path.
- Remote small board / short harness: status + enable + fault lines need robust behavior under ground potential differences.
Reality check: isolation does not “remove” noise — it changes the failure modes into timing drift, fail-safe defaults, and common-mode coupling paths.
What this page solves (six engineering “new pits” after isolation)
- Latency budgeting: how isolator propagation delay (tpd) consumes UART sampling margin and impacts pulse timing. (Pass criteria placeholder: Δtpd ≤ X ns)
- Skew / mismatch: how channel-to-channel skew breaks handshake or multi-line GPIO coordination. (skew ≤ Y ns)
- Fail-safe states: defining TX idle and GPIO default levels/Hi-Z during UVLO, brownout, or power loss. (default state verifiable)
- Power sequencing: guaranteeing “no unintended toggles” for any VDD1/VDD2 order. (no spurious toggles within X ms)
- EMC/ESD coupling: identifying barrier capacitance paths and placing protection so return currents stay on the correct side. (post-ESD: error rate ≤ N/min)
- Validation + production proof: test methods to measure delay/skew, immunity behavior, and recovery policy for field diagnostics. (repeatable test plan)
Output of this topic page: a consistent timing/behavior “contract” that can be verified on bench and enforced in production.
Diagram: Two-domain partition (signals + supplies + split grounds)
H2-2. Where It’s Used and What It’s Not
Good fit (what isolated UART/GPIO is best at)
- Control + status lines: enable/reset/select, fault/ready/interrupt, boot mode straps — where safe defaults matter.
- Service / diagnostic UART: short, point-to-point access for commissioning and field maintenance under ESD risk.
- Board-to-board ground mismatch: when local ground noise or ground potential difference causes false triggers or damage in direct connections.
- Cabinet / harness environments: where dv/dt and common-mode events dominate; isolation reduces direct stress but still requires EMC-aware layout.
Decision cue: if the job is “commands + flags + service access”, isolated UART/GPIO is usually the simplest and most testable choice.
Not a good fit (use the right isolated interface instead)
- Long cable + strong external interference: use isolated differential buses (RS-485 / CAN / LIN) for controlled impedance, robustness, and receiver behavior.
- Multi-drop bus arbitration / termination-dependent behavior: UART/GPIO is point-to-point by nature; buses need PHY-level signaling and topology rules.
- Open-drain bi-directional shared bus semantics: isolated I²C needs special handling for pull-ups, clock stretching, and bidirectional edges.
- High-speed packet links with compliance testing: isolated USB/Ethernet require different signal integrity + EMC strategies than discrete UART/GPIO lines.
- Strictly synchronous clock chains or ultra-low jitter budgets: use dedicated low-jitter clock isolation devices and a clock-focused timing budget.
Rule of thumb: if the requirement is “networking” or “compliance-driven high-speed”, UART/GPIO isolation is the wrong tool.
Fast decision checklist (30 seconds)
- Is it point-to-point? If not, a bus PHY is likely required.
- Is the main payload “commands + flags”? If yes, UART/GPIO is a strong candidate.
- Is there a strict timing or jitter contract? If yes, plan a dedicated timing budget (and possibly a clock isolator).
- Is the environment dv/dt / ESD dominated? If yes, treat coupling paths + layout as first-class design work.
Diagram: Interface routing (choose the right isolated link)
H2-3. Isolation Architectures for UART and GPIO
UART signal groups (direction is the first-class constraint)
In real systems, UART rarely means only TX/RX. Isolation architectures are selected by
direction, channel grouping, and default-state behavior.
Typical UART-related signals (grouped by function):
- Data: TX (primary → remote), RX (remote → primary)
- Flow control: RTS / CTS (optional, but direction must be explicit)
- Service / boot control: RESET, BOOT/STRAP, DBG_EN (optional)
Direction rule: every lane must have a known source side and sink side. Swapping a lane’s direction often looks “alive”
on a scope but fails functionally (e.g., handshake never completes).
Architecture mapping (common patterns):
- 2ch (1+1): TX + RX only (minimal, common for service UART)
- 4ch (2+2): TX/RX + RTS/CTS (more robust for managed ports)
- 6ch (3+3) / 8ch: add RESET/BOOT/extra status lines (field-friendly control contract)
- Mixed-direction: when extra GPIO must cross opposite directions beyond a symmetric split
Practical checklist: confirm lane direction + mapping, then confirm default states for each lane during UVLO and power sequencing.
GPIO across the barrier (what works well vs what needs a timing contract)
GPIO isolation is best when signals are control/state. It becomes sensitive when signals are
edge/width dependent (pulses, interrupts, PWM). The safe approach is to classify GPIO by behavior.
Behavior groups and constraints:
- Static control (EN/SEL/RESET): most robust. Key requirement is fail-safe default and no spurious toggles.
- Event inputs (FAULT/READY/INT): robust if glitch susceptibility is managed (noise/ESD events must not look like valid pulses).
- Pulse / step lines (PULSE/STEP): feasible only when minimum pulse width and delay variation are budgeted. (Pass criteria placeholder: PWmin ≥ X ns, Δtpd ≤ Y ns)
- PWM: possible but higher risk. The “contract” must specify allowed duty error and edge timing shift. (ΔDuty ≤ X%, edge shift ≤ Y ns)
Three fast questions:
(1) Is it point-to-point?
(2) Does correctness depend on pulse width/edge timing?
(3) Must the line default to a safe state under power loss?
If (2) or (3) is “yes”, timing + default-state rules are mandatory design inputs.
Diagram: Channel direction and supply topology (2ch / 4ch / 6ch / mixed-direction)
H2-4. UART Timing Budget: Latency, Skew, and Baud Tolerance
UART sampling model (why async links are sensitive to cumulative error)
UART is asynchronous: it uses the start bit to align timing once,
then relies on the local receiver clock to sample each bit near the bit center.
Any drift that shifts the receiver’s sampling instant toward a transition edge increases the probability of framing/bit errors.
- Oversampling: provides a stable sample point around the bit center (not “more speed”).
- Sample point: a practical “window” where the bit value is expected to be stable.
- Start-bit alignment: the reset point — if corrupted, the whole frame becomes fragile.
Design mindset: treat the sample window as a budget to be spent by clock mismatch + delay variation.
Error sources to budget (what actually moves the sample point)
- Clock mismatch (baud tolerance): transmitter and receiver clocks differ. Isolation does not create this error, but it reduces margin so the same mismatch becomes riskier.
- Propagation delay variation (Δtpd): not the absolute delay, but the change across voltage/temperature/process that shifts effective sampling relative to bit time. (use datasheet tpd(min/max) and temp drift)
- Channel mismatch (skew): typically critical for handshake / control alignment (RTS/CTS, reset sequencing, multi-line GPIO), and can create false ordering of events. (use datasheet skew max)
Worst-case budgeting stacks these contributors as “static offset + drift range”, then validates at temperature and supply corners.
Turning datasheet numbers into a timing contract (repeatable + testable)
- Start from bit time: define the target baud and compute bit time as the reference budget.
- Collect worst-case delay limits: use datasheet tpd(min/max) and any specified PVT drift.
- Convert Δtpd into sample-point shift: express the shift as a fraction of bit time. (Pass criteria placeholder: |Δtpd| / Tbit ≤ X%)
- Add skew for multi-line coordination: for RTS/CTS or multi-GPIO events, require ordering margin. (skew ≤ Y ns; ordering margin ≥ Z ns)
- Define validation at corners: run Tmin/Tmax and Vmin/Vmax; verify error rate + “no spurious toggles” after disturbance. (errors ≤ N per Y minutes)
Result: a timing contract that can be measured on the bench (delay/skew) and enforced in production (stress + long-run).
Diagram: Bit time + sample window + delay shift (block-style timing view)
H2-5. GPIO Behavior Across the Barrier
Output GPIO (EN / RESET / SEL) — default state and power-up glitch
Output-class GPIO is typically used for enable, reset,
mode select, and chip-select like control.
Across an isolation barrier, correctness is dominated by two contracts: what the output becomes when power is not valid,
and whether any spurious edges occur during transitions.
What must be defined (per critical output pin):
- Power-down default: High / Low / Hi-Z (explicitly required for safety and field behavior).
- Power-up behavior: no unintended toggles while VDD1/VDD2 ramps or while one side is missing.
- Hold policy: whether the output holds a safe state until the remote side is confirmed valid.
Pass criteria placeholders:
(a) spurious toggles = 0 across N power cycles;
(b) default reached within X ms after power invalid;
(c) output remains safe under partial power on either side.
Input GPIO (FAULT / READY / INT) — glitch immunity and minimum pulse width
Input-class GPIO typically carries status or events.
Across isolation, the primary failure mode is false events caused by short glitches (ESD, dv/dt injection, ground bounce),
and the secondary failure mode is missing real events when filtering is too aggressive.
Required contracts (for each event input):
- Minimum valid pulse width (PWmin): define the narrowest event that must be reliably detected. (PWmin ≥ X ns/µs)
- Glitch rejection window: define what must be rejected as non-events. (reject ≤ Y ns/µs)
- Trigger model: edge vs level, and whether latching is required for short events.
Pass criteria placeholders:
false-trigger rate ≤ N per hour under disturbance;
detection rate = 100% for events with width ≥ PWmin across PVT corners.
PWM / pulse GPIO — when a different isolated interface is mandatory
PWM and pulse-style GPIO can cross isolation, but only when timing error is non-critical.
When control depends on duty accuracy, edge placement, or multi-line synchrony,
the safer approach is to move timing generation to the isolated side and transmit configuration data instead of raw edges.
Red-line conditions (treat as “must not use raw GPIO across the barrier”):
- Closed-loop sensitivity: duty/phase error directly changes a regulated quantity (torque, current, precision dimming). (ΔDuty ≤ X% and edge shift ≤ Y ns must be guaranteed)
- Pulse width near limits: pulses are comparable to filter windows or delay variation. (PWmin margin ≥ Z× worst-case timing spread)
- Synchronous multi-line timing: multiple PWM/step lines must align with tight relative skew limits.
Practical alternatives (selection pointer only): use isolated SPI to deliver control words to the isolated side, or use a dedicated isolated driver that generates/validates timing locally.
Diagram: Pulse fidelity vs filtering boundary (RAW vs FILTERED vs SYNC/LATCH)
H2-6. Fail-Safe States and Power Sequencing
Define defaults first (TX idle, GPIO High/Low/Hi-Z)
For PLC and field I/O, the biggest risk is not “data corruption” but unexpected actuation.
A fail-safe design starts by defining the default electrical state for each critical pin under power loss and undervoltage.
- UART TX idle: define idle polarity and the required behavior when either side is unpowered.
- GPIO outputs: define default = High / Low / Hi-Z for each control pin (EN/RESET/SEL).
- GPIO inputs: define whether missing/invalid remote power shall be interpreted as Fault, Not-ready, or “don’t care”.
Pass criteria placeholders: default reached within X ms; no valid edges during transitions; stable default under partial-power conditions.
Power sequencing (VDD1/VDD2 in any order) — require safe outputs
In modular systems and service scenarios, VDD1 and VDD2 cannot be assumed to ramp in a fixed order.
A robust design must specify output behavior for all sequencing cases, including partial-power and repeated cycling.
Sequencing cases that must be safe:
- Case 1: VDD1 valid first, VDD2 missing → outputs must remain in defined safe defaults.
- Case 2: VDD2 valid first, VDD1 missing → remote side must not back-power or generate unintended outputs.
- Case 3: both ramp but with different slopes → no transient toggles at threshold crossings.
Pass criteria placeholders: spurious toggles = 0 for N cycles; recovery to ACTIVE only after “both sides valid” condition is met for Y ms.
UVLO and brownout — prevent chatter, repeated resets, and out-of-order recovery
The most field-visible instability occurs when supply voltage hovers near UVLO thresholds.
Without anti-chatter rules, the system can oscillate between “valid” and “invalid”, producing repeated resets and unintended edges.
Engineering strategies (policy-level, testable):
- Hysteresis / blanking window: avoid toggling outputs while crossing UVLO boundaries.
- Latch-to-safe: once invalid is detected, hold safe defaults until a stable “recover OK” condition is met.
- Ordered recovery: require a deterministic sequence from power valid → IO safe → link enable → functional enable.
Pass criteria placeholders: no output chatter under brownout injection; recover to ACTIVE only after stability time Y ms; no repeated reset storm across M cycles.
Diagram: Power-up / power-down state machine (OFF → UVLO → ACTIVE → FAULT-SAFE)
H2-7. EMC/ESD and Common-Mode Injection for Single-Ended Lines
Barrier capacitance → common-mode current path (why noise “sprays” across the barrier)
Isolation blocks DC conduction, but the barrier still has finite capacitance.
Any fast transient (ESD, switching dv/dt, ground bounce) can drive a common-mode current through the barrier capacitance.
For single-ended UART/GPIO, that common-mode current can be converted into radiated noise and false edges once it couples into the cable/connector system.
- Driver: dv/dt events (ESD strike, fast switching node, hot-plug bounce).
- Coupler: barrier capacitance (unavoidable in real isolators).
- Antenna: cable + connector + chassis loop (turns CM current into radiation and coupling).
Pass criteria placeholders: CM current peak ≤ X mA during dv/dt events; false-edge rate ≤ N/hour on UART/GPIO lines under disturbance; no unintended resets across Y stress cycles.
Port ESD/TVS placement and return (primary returns to primary; secondary returns to secondary)
ESD suppression succeeds only if the discharge current closes a short, local loop.
A common failure is placing the TVS near the connector but routing its return into the wrong domain reference,
which injects the ESD energy into sensitive logic and can even drive cross-domain disturbances.
Placement and return rules (interface-focused):
- Near the entry: TVS and protection components should sit at the connector/entry to minimize “on-board travel”.
- Same-side return: protection return must go to the local reference of that side (GND1/chassis on primary, GND2/chassis on secondary).
- No cross-gap return: never route a TVS return across the isolation gap/keepout.
Pass criteria placeholders: 0 unintended toggles on protected lines across N ESD strikes; no latch-up/reset; clamped residual spike ≤ X V with ringing duration ≤ Y ns.
Edge shaping (slew control / series R) — immunity vs timing margin trade-off
Single-ended edges can excite cable radiation and create overshoot/ringing that looks like extra transitions.
Slowing the edge and adding damping can reduce EMI, but overly slow edges reduce noise margin and can break timing at higher data rates or narrow pulses.
The goal is controlled edges, not “as slow as possible”.
- Series R: reduces peak current, damps ringing, and limits fast spectral content on cables.
- Slew control: reduces high-frequency components that strongly radiate from harness loops.
- Boundary conditions: keep rise/fall time within an allowed fraction of bit time; ensure PWmin margin for pulse GPIO and interrupts.
Pass criteria placeholders: EMI margin improves by X dB while UART error rate remains ≤ Y; 0 false interrupts; pulse detection = 100% for width ≥ PWmin.
Diagram: Common-mode coupling current path (Cbarrier → ICM → cable → chassis → return)
H2-8. Layout & Grounding Rules for Isolated UART/GPIO
Partition first: keepout, gap/slot, and “no-routing” rules
Correct isolation starts with a clean physical boundary.
The primary and secondary domains must be treated as two separate boards connected only through the isolator.
The isolation gap/keepout must remain free of copper, vias, and high-field switching nets to avoid unintended coupling.
- Primary plane: signals and return remain on GND1 side.
- Secondary plane: signals and return remain on GND2 side.
- Gap/slot + keepout: no traces, no vias, no copper pour crossing the boundary.
Checklist placeholders: keepout respected; no cross-gap stitching; isolator straddles boundary with clean pin escape on each side.
Return paths: never let signal return cross the gap; chassis/shield as a controlled reference
UART/GPIO are single-ended and therefore depend on a well-defined local return.
If the return is forced to “find a path” across the gap, the loop expands, radiates, and becomes sensitive to injected common-mode current.
Use chassis/shield connections only as a controlled reference at the entry point, not as an accidental cross-domain return path.
- Local loop: keep UART/GPIO loop area small on each side (signal + local return).
- No cross-gap return: avoid routes that force return current across the isolation boundary.
- Shield/chassis principle: bond at the entry to contain noise locally; do not create uncontrolled long shield loops.
Validation placeholders: EFT/ESD tests show 0 false triggers; no resets; measured noise on GPIO lines stays below X Vpp during stress.
Connector-entry discipline: protection at the entry, domain-referenced returns, and test access
The harness entry is the energy entry.
Protection, damping, and reference must be established before energy reaches sensitive circuitry.
Reserve a small, consistent “entry zone” so that ESD return and damping components always have a short, predictable path.
- TVS placement: at the connector with short return to the local domain reference.
- Series R / damping: near the driver/receiver to control edge and ringing before it hits the harness.
- Test points: reserve observation points to verify waveform, clamp behavior, and false-edge events during production tests.
Production criteria placeholders: pass N stress cycles with 0 false events; clamp and ringing within limits; repeatable results across fixtures.
Diagram: PCB top-view partition map (Primary plane / gap / secondary plane / keepout / connector entry)
H2-9. Validation: How to Prove It Works
Functional validation: loopback, long-run, and controlled error injection
Functional pass is not “it works once”. The goal is to prove stable behavior across time, temperature, and injected disturbances,
with predictable fail-safe and diagnosable logs when faults occur.
Setup
- UART: TX/RX loopback paths (same-side and cross-barrier), known test frames, error counters enabled.
- GPIO: output-to-input return path (jumper/fixture), interrupt counting, timestamp capture if available.
- Conditions: sweep supply corners and temperature corners (placeholders: VDD = X1…X2, T = Y1…Y2).
Procedure
- Loopback: verify idle levels, polarity, and stable framing under nominal settings.
- Long-run: run continuous traffic and toggle patterns over hours; record error rates over fixed windows.
- Error injection: introduce controlled baud offset and short glitch pulses; observe fail-safe entry and recovery behavior.
Pass criteria placeholders
- UART: error rate ≤ X / 10⁹ bits (or ≤ Y / hour) during long-run; 0 unexpected resets across N hours.
- GPIO: false interrupt ≤ X / hour; missed event = 0 for pulse width ≥ PWmin.
- Diagnostics: fault events are logged with timestamp/cause; counters are monotonic and not reset unexpectedly.
Log points (minimum set)
- UART: framing/parity/overrun counters; dropped bytes; reset-reason code.
- GPIO: interrupt count; debounce/filter hit count; event timestamp if available.
- Fail-safe: entry count; exit count; recovery time (ms) and recovery mode (auto/manual).
Timing validation: tpd/skew, baud margin, and minimum pulse width
Timing validation converts the budget into measured margins.
The focus is not absolute latency, but variation across PVT and channel mismatch that reduces sampling and detection margin.
What to measure
- tpd (min/max): input edge at TX/GPIO_OUT to output edge at RX/GPIO_IN across PVT corners.
- Skew (max): channel-to-channel mismatch for mixed-direction or multi-line control sets.
- Baud tolerance: scan baud offset until errors start; record the “error cliff” point.
- PWmin: sweep pulse width down and track detection success rate and false trigger rate.
How to run it
- Corner sweep: measure at nominal, hot, cold, and supply corners (placeholders: T, VDD).
- Windowed stats: report max/min across a fixed observation window, not single captures.
- Correlate: link timing deltas to UART/GPIO symptom counters (errors/false edges).
Pass criteria placeholders
- tpd: tpd_max ≤ X ns; Δtpd(PVT) ≤ Y ns.
- Skew: skew_max ≤ X ns for the relevant channel group.
- Baud margin: tolerable total offset ≥ X% without framing errors.
- PWmin: 100% detection for width ≥ X; 0 false triggers for width ≤ Y (filter region).
Disturbance validation: ESD/EFT and power wobble — fail-safe entry and predictable recovery
Passing disturbance tests means the system enters a known safe state and returns by a predictable policy.
The key outputs are no unintended actions, controlled fail-safe, and diagnosable logs.
What to observe
- ESD: UART drop/garble, GPIO false edges/interrupt storms, resets, latch events.
- EFT: repeated toggles, brownout-induced oscillation, fail-safe thrashing.
- Power wobble: output glitches at power-up/down, UVLO chatter, recovery time.
Pass criteria placeholders
- Fail-safe: outputs enter defined safe levels (TX idle, GPIO safe) within X ms of disturbance.
- Stability: no uncontrolled oscillation; fail-safe entry count ≤ N per event.
- Recovery: self-recovery time ≤ X ms (or manual-clear path is deterministic); 0 unintended actions during recovery.
- Logging: each event recorded with cause + timestamp + counter increments.
Diagram: Validation matrix (Test × Failure mode)
H2-10. Engineering Checklist
Card A — Design checklist (channels, safe states, protection, partition, edge control)
- Direction map frozen: define UART TX/RX and each GPIO as IN/OUT/INT with a one-line purpose.
- Safe-state table written: TX idle level + GPIO default (High/Low/Hi-Z) per line.
- Power-order assumption explicit: VDD1/VDD2 any-order start; outputs must not glitch into unsafe actions.
- UVLO/brownout policy defined: no chatter loops; deterministic entry/exit into safe states.
- Timing budget captured: tpd(max/min), Δtpd(PVT), channel skew(max) written into margin placeholders.
- UART baud margin target set: total tolerable offset ≥ X% (clock error + drift + isolator variation).
- GPIO pulse boundary set: PWmin for 100% detection + reject window for 0 false triggers.
- Entry-zone rule applied: protection at connector; return stays in the same domain (no cross-gap return).
- Edge shaping decided: series-R / slew control used to balance EMI vs timing margin.
- Partition/keepout enforced: primary plane, gap/slot, secondary plane, no copper/vias in keepout.
- Return integrity checked: signal return never forced across the isolation gap.
- Test access reserved: tpd/skew measurement points + UART error counters + GPIO event counters.
Reference parts (example MPNs)
- 2-ch (1+1) digital isolator: TI ISO7721; Analog Devices ADuM1201; Silicon Labs Si8621.
- 4-ch mixed-direction: TI ISO7741; Analog Devices ADuM1401; Silicon Labs Si8641.
- ESD/TVS (single-line): Nexperia PESD5V0S1UL; Littelfuse SMF5.0A; onsemi ESD9B5.0ST5G.
- ESD array (multi-line): Semtech RClamp0504; Nexperia PESD5V0X1BSF (array family).
- Series resistor (damping): Yageo RC0402FR-0733RL (33 Ω, 0402) as a common starting point.
- Ferrite bead (entry noise): Murata BLM18AG601SN1D (0603) as a typical example.
Pass criteria placeholders: direction/safe-state/power-order/timing/entry-zone rules reviewed and signed off; ECO requires re-run of H2-9 validation.
Card B — Bring-up checklist (power order, idle levels, false triggers, injection, logs)
- Power-order test: VDD1→VDD2 and VDD2→VDD1 both pass with no unsafe output transitions.
- Power-down test: each side drops independently; outputs settle into defined safe states.
- UART idle correctness: idle level, polarity, framing settings verified against the safe-state table.
- Loopback sanity: same-side loopback + cross-barrier loopback both pass.
- Long-run started: fixed time windows; error counters logged periodically (no “single capture” acceptance).
- tpd measured: record tpd(min/max) at nominal and at least one corner (placeholders: T/VDD).
- Skew measured: multi-line toggles; record worst-case skew(max) for the used channel group.
- Baud cliff found: sweep baud offset to the error onset; keep a safety margin beyond that point.
- PWmin verified: pulse width sweep; 100% detection above PWmin, 0 false triggers in reject window.
- Noise injection quick check: controlled glitch injection does not cause spurious actions or reset storms.
- Fail-safe behavior confirmed: disturbance causes safe-state entry by policy; no thrashing loops.
- Logs actionable: reset reason, UART counters, GPIO event counters, fail-safe entry/exit timestamps are captured.
Reference parts (example MPNs often used on bring-up benches)
- Logic-level header (service port): Samtec TSW-105-07-G-S (0.1″ header family example).
- Test clip / probe point: Keystone 5000/5001 (test point family example).
- UART bridge (lab tool reference): FTDI FT232R (USB-UART IC used on many adapters).
Pass criteria placeholders: long-run ≥ Y hours with error rate ≤ X; 0 unintended actions; recovery time ≤ N ms; logs complete for every injected event.
Card C — Production checklist (hi-pot or insulation screen, functional self-test, sampling, traceability)
- Factory self-test fixed: UART frame test + GPIO toggle/interrupt test; results tied to serial number.
- Safe-state verified in test: power-up/down paths validate defined defaults (no accidental enable/reset).
- Insulation screen (if required): hi-pot/continuity procedure defined with simple pass/fail limits (placeholders).
- Sampling plan defined: AQL or fixed-rate sampling; re-test rules documented (placeholders).
- Golden unit maintained: used to validate fixture health and test repeatability.
- Fixture version locked: fixture HW/SW version, calibration record, maintenance interval tracked.
- BOM/PCBA version locked: isolator, TVS, key passives substitutions require re-running H2-9 gates.
- Firmware/config locked: baud, filters, default states, recovery policy cannot drift between builds.
- Protection placement audited: TVS/return path and entry-zone layout checked on AOI criteria list.
- Traceability complete: certificates/reports archived; build record includes versions and test results.
- Failure routing defined: reproduce → classify symptom → confirm logs → decide rework/scrap.
Reference parts (example MPNs used in production test setups)
- High-voltage relay (test fixture concept): Omron G2RL (relay family example).
- Shunt for simple current checks: Vishay WSL/WSLP (shunt family example).
Pass criteria placeholders: 100% functional self-test pass; insulation screen pass (if applicable); sampling failure rate ≤ X%; complete traceability per unit.
Diagram: Design-to-production gate flow (Design freeze → EVT → DVT → PVT)
H2-11. Applications
PLC remote I/O (fault/ready GPIO, safe states)
- Safe-state first: outputs must never enable actuators on brownout or power-order mismatch.
- Pulse integrity: define PWmin for fault/ready/interrupt lines to avoid missed events.
- Entry-zone discipline: TVS and return paths stay within the local domain; avoid cross-gap return.
- Validation focus: long-run counters + disturbance (ESD/EFT) with predictable fail-safe and recovery.
Example pairing (MPNs)
- Isolator: TI ISO7741 (4ch) or ADI ADuM1401 (4ch).
- TVS/ESD: Nexperia PESD5V0S1UL (single line) or Semtech RClamp0504 (array).
- Damping: Yageo RC0402FR-0733RL (33 Ω series) on fast edges near the driver.
Service UART for industrial equipment (ESD and ground bounce)
- Command safety: avoid “garbled UART” turning into unintended actions; enforce safe default states.
- Connector entry is the energy entry: place ESD close to the connector with short return loops.
- Edge control: series-R reduces ringing and radiated emissions on service cables.
- Validation focus: ESD hits produce 0 unintended commands; logs show cause/time; recovery is deterministic.
Example pairing (MPNs)
- Isolator (2ch 1+1): TI ISO7721 or ADI ADuM1201.
- ESD array: Semtech RClamp0504 (multi-line protection).
- Series-R: Yageo RC0402FR-0747RL (47 Ω) as an alternative damping value.
MCU ↔ high-side sensing controller (CMTI environment + default state control)
- Common-mode stress reality: prioritize robust isolation in high dv/dt environments.
- Default states must be safe: enable/reset/select lines cannot float into unsafe states during disturbances.
- Timing variation matters: measure Δtpd and skew across corners; keep control timing margin.
- Validation focus: EFT/power wobble does not cause thrashing; recovery is bounded and logged.
Example pairing (MPNs)
- Isolator: TI ISO7741 (4ch) or Silicon Labs Si8641 (4ch).
- TVS (rail clamp example): Littelfuse SMF5.0A on exposed control lines.
- Bead (entry noise example): Murata BLM18AG601SN1D to reduce high-frequency injection.
Multi-drop debug header (why it is usually not recommended)
- Stub and return ambiguity: branches increase ringing and false edges; reference paths become inconsistent.
- ESD exposure multiplies: more taps mean more entry points for injected energy.
- If unavoidable: enforce strict entry-zone protection and stronger validation (H2-9 matrix).
Example pairing (MPNs)
- Isolator: TI ISO7721 (2ch) for minimal line count.
- ESD array: Semtech RClamp0504 close to each exposed header entry.
- Series-R: Yageo RC0402FR-0733RL on each branch to reduce ringing.
Diagram: Application puzzle (4 typical system shapes)
H2-12. IC Selection Logic
Card A — Decision tree (from requirements to common solution archetypes)
Goal: converge on channel count + direction mix + safe-state behavior + timing margin + EMC robustness, then validate with measurable gates.
- UART only? If UART-only → step 2. If UART+GPIO or GPIO-only → step 5.
- Need handshake / control lines? (RTS/CTS/RESET/BOOT) If no → Archetype 1 (2ch 1+1). If yes → step 3.
- Safe default state required when either side is unpowered? If yes → step 4. If no → Archetype 2 (4ch basic/mixed).
- Timing tight? (tpd variation / skew must stay inside UART margin) Tight → Archetype 3 (4ch + tighter timing grade; measure tpd/skew). Relaxed → Archetype 2’ (4ch + safe-state option).
- GPIO behavior dominated by pulses/interrupt/PWM? Static enables/resets → Archetype 4 (mixed multi-ch, safe-state priority). Pulse/INT sensitive → step 6.
- Minimum pulse width / glitch immunity tight? Tight → Archetype 5 (pulse/INT sensitive; PWmin validation required). Relaxed → Archetype 4.
- Harsh dv/dt / EMC environment? (motor-drive cabinet, long harness, noisy chassis) Yes → upgrade any archetype to high CMTI + low coupling + stronger entry protection and edge control.
Common archetypes (outputs) + example MPN candidates
Archetype 1 — 2ch (1+1) UART only
- Isolator: TI ISO7721 / ADI ADuM1201 / SiLabs Si8621
- ESD (single-line): Nexperia PESD5V0S1UL / onsemi ESD9B5.0ST5G
- Series R: Yageo RC0402FR-0733RL (33 Ω) or RC0402FR-0747RL (47 Ω)
Validate: long-run error rate ≤ X; ESD hit → 0 unintended commands; recovery ≤ N ms.
Archetype 2 — 4ch UART + handshake / boot
- Isolator: TI ISO7741 / ADI ADuM1401 / SiLabs Si8641
- ESD array: Semtech RClamp0504 (4-line) (place at connector entry)
- Ferrite bead (entry noise): Murata BLM18AG601SN1D (0603)
Validate: measure tpd/skew; power-order (VDD1/VDD2) must not produce unsafe GPIO.
Archetype 3 — Timing-tight 4ch (tpd/skew sensitive)
- Isolator family candidates: TI ISO77xx 4ch class / ADI ADuM14xx class / SiLabs Si86xx class
- Damping: Yageo RC0402FR-0733RL on fast edges near the driver
- Pull resistors (defaults): Yageo RC0402FR-0710KL (10 kΩ) or RC0402FR-0747KL (47 kΩ)
Validate: skew(max) ≤ X ns; Δtpd across PVT ≤ Y ns; UART baud margin ≥ Z%.
Note: select the ordering option/variant that guarantees the required default output state; confirm in datasheet.
Archetype 4 — Mixed multi-ch GPIO control set
- Isolator candidates: TI ISO7741 / ADI ADuM1401 / SiLabs Si8641 (choose direction mix)
- ESD: Semtech RClamp0504 (array) + optional single-line PESD5V0S1UL for exposed lines
- Edge shaping: 33–100 Ω series (start at 33–47 Ω; adjust by ring/EMI)
Validate: 0 unintended enable/reset during brownout; glitch rate ≤ X/1k events.
Practical rule: keep the solution set small (2ch / 4ch / mixed). Spend effort on safe-state definition + entry protection + validation, not on collecting model lists.
Card B — Key spec cards (read → risk → pitfall → validate)
1) Channel count & direction
What it controls: correct mapping for TX/RX/INT/EN lines.
What to read: channel direction table, max data rate, enable pins.
Pitfall: “looks symmetric” but direction mix is wrong → dead handshake.
Validate: loopback + per-line toggles; 0 swapped channels.
2) Default output state / fail-safe
What it controls: no unintended enable/reset on power loss.
What to read: “default output”, “failsafe”, output when VDD missing.
Pitfall: assuming defaults without checking the ordering option.
Validate: VDD1/VDD2 any-order; outputs match safe-state table.
3) Prop delay tpd (min/max) & drift
What it controls: UART sampling margin and timing alignment.
What to read: tpd(max/min), Δtpd vs temp/VDD, pulse-width distortion.
Pitfall: using “typical tpd” only; ignoring drift and spread.
Validate: measure tpd(min/max) → margin ≥ X% of bit time.
4) Channel-to-channel skew
What it controls: handshake correctness and multi-line coherence.
What to read: skew(max), skew drift vs PVT.
Pitfall: ignoring skew when RESET/BOOT is time-critical.
Validate: simultaneous toggles; skew(max) ≤ X ns.
5) Data rate ↔ UART baud margin
What it controls: reliable start-bit alignment and sampling window.
What to read: max toggle rate, PWD, recommended input filtering.
Pitfall: fast edges improve eye but worsen EMI and false triggers.
Validate: baud sweep to cliff; keep ≥ Y% margin.
6) CMTI / dv/dt immunity
What it controls: immunity to common-mode spikes and false edges.
What to read: CMTI rating (kV/µs), test conditions, fail behavior.
Pitfall: treating CMTI as system immunity without layout/return control.
Validate: EFT/noise injection; false-event rate ≤ X.
7) Barrier coupling (Cbarrier) & CM emission
What it controls: “noise spray” across the barrier into cables/chassis.
What to read: barrier capacitance, EMI notes, edge-rate options.
Pitfall: ESD/TVS return crossing the gap → turns into an antenna loop.
Validate: radiated/near-field scan; compare with/without series-R.
8) Supply range & UVLO behavior
What it controls: deterministic safe-state during brownout and restart.
What to read: VDD range, UVLO thresholds/hysteresis, power-up default timing.
Pitfall: UVLO chatter → repeated resets/false interrupts.
Validate: slow ramp + dip test; 0 unsafe toggles.
9) ESD rating vs system protection
What it controls: survival of exposed service ports and field I/O.
What to read: HBM/CDM and IEC notes; recommended external TVS.
Pitfall: relying on IC rating while leaving cable entry unprotected.
Validate: ESD at connector; check safe-state + logs + recovery.
10) Package fit (creepage/clearance on PCB)
What it controls: whether the PCB partition and keepout are physically feasible.
What to read: package creepage/clearance, recommended land pattern, keepout guidance.
Pitfall: routing a “small” package but violating the required gap.
Validate: DRC rule + physical measurement; keepout respected.
Pass criteria placeholders: CMTI ≥ X kV/µs (system target), skew(max) ≤ Y ns, Δtpd ≤ N ns, PWmin ≥ Z ns, 0 unsafe actions across any power-order.
Card C — Quick pairings (isolation + protection + edge control + minimal power hint)
These are compact reference combinations. Confirm safe-state ordering options and exact ratings in the datasheets before freezing a BOM.
Pairing A — Service UART (2ch)
- Isolator: TI ISO7721 / ADI ADuM1201 / SiLabs Si8621
- ESD: Semtech RClamp0504 (array) or Nexperia PESD5V0S1UL (single)
- Series R: Yageo RC0402FR-0733RL (33 Ω)
- Pulls (defaults): Yageo RC0402FR-0710KL (10 kΩ)
Validation hook: ESD at connector → 0 unintended commands; recovery time ≤ N ms.
Pairing B — UART + RTS/CTS or BOOT/RESET (4ch)
- Isolator: TI ISO7741 / ADI ADuM1401 / SiLabs Si8641
- ESD array: Semtech RClamp0504
- Bead (entry): Murata BLM18AG601SN1D
- Series R: Yageo RC0402FR-0747RL (47 Ω)
Validation hook: measure tpd/skew; power-order must keep RESET/BOOT in safe state.
Pairing C — PLC remote I/O GPIO set (mixed)
- Isolator (direction mix): TI ISO7741 / ADI ADuM1401 / SiLabs Si8641
- TVS (single): Littelfuse SMF5.0A or Nexperia PESD5V0S1UL
- Series R: Yageo RC0402FR-0733RL (start point)
- Test points: Keystone 5000/5001 (family example)
Validation hook: PWmin sweep + false-interrupt counter; 0 unintended enable during brownout.
Pairing D — Harsh dv/dt / high EMC stress
- Isolator candidates: TI ISO77xx class / ADI ADuM14xx class / SiLabs Si86xx class (choose high-CMTI grade)
- ESD array: Semtech RClamp0504
- Edge control: Yageo RC0402FR-0747RL (47 Ω) + keep loops compact
- Isolated supply (example only): Murata NXE1S0505MC (module) (power details go to Isolated Power page)
Validation hook: EFT/power wobble → no thrashing; recovery bounded and logged.
Diagram: Selection decision tree (7 nodes → 4 common outputs)
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H2-13. FAQs
Field troubleshooting (fixed 4-line answers)
Format per question: Likely cause → Quick check → Fix → Pass criteria (threshold placeholders X/Y/N).
UART idle looks normal, but occasional framing errors appear — check baud budget or isolator delay drift first?
Likely cause: Baud tolerance margin is already thin; added propagation delay variation (PVT drift) shifts the effective sampling window.
Quick check: Recompute error budget (TX/RX clock ppm + sampling point + worst-case Δtpd); run a baud sweep to find the cliff and compare to the expected margin.
Fix: Tighten endpoint clocks or lower baud; select a lower-drift isolator grade; add 33–47 Ω series damping to reduce ringing-induced edge ambiguity.
Pass criteria: Framing errors ≤ X over Y minutes at Tmin/Tmax, and measured baud cliff margin ≥ N% beyond the target baud.
Errors show up only at low/high temperature — skew PVT drift or threshold/edge slowing?
Likely cause: Channel-to-channel skew or Δtpd grows across PVT; slower edges at temperature corners increase time spent near the input threshold (more susceptible to noise).
Quick check: Measure tpd/skew at two temperature extremes; capture rise/fall times at the receiver threshold and compare against the UART/GPIO timing margin.
Fix: Pick a tighter timing grade (lower drift/skew); reduce edge sensitivity with series R and strong default pulls; avoid long stubs near noisy bundles.
Pass criteria: Δtpd ≤ X ns and skew ≤ N ns across temperature sweep, with 0 functional fails over Y thermal cycles.
A GPIO toggles once during power-up — default-state configuration or sequencing glitch?
Likely cause: Output is not guaranteed to a safe default when one side is unpowered; UVLO transitions create a brief uncontrolled output state.
Quick check: Test VDD1-first and VDD2-first ramps; scope the GPIO with proper local ground reference and record any transitions during UVLO entry/exit.
Fix: Use a fail-safe/default-state variant; add external pull-up/down to enforce safe state; gate downstream enable/reset until both rails are valid.
Pass criteria: Unsafe transitions = X over Y power cycles (all power orders), and max observed glitch width ≤ N ns.
ESD to chassis causes UART garbage but the link stays up — common-mode injection path or TVS return?
Likely cause: ESD current couples through barrier capacitance into the single-ended line reference; a TVS return that crosses domains amplifies the injected common-mode disturbance.
Quick check: Inspect TVS placement and its return path (must return to the same local domain); use a current probe to see if ESD drives cable/common-mode current.
Fix: Move TVS to the connector entry and keep return local; add series R / controlled slew to reduce high-frequency content; ensure chassis bond strategy does not force return across the barrier.
Pass criteria: After N ESD hits at X kV across Y locations, UART garbage frames = 0 and the system stays in defined safe states.
Intermittent issues even with a short cable — ground reference/probing or overly strong drive causing ringing?
Likely cause: Measurement setup hides the real threshold behavior; fast edges ring on the single-ended line and create double-crossings at the receiver.
Quick check: Re-measure at the receiver pin using a ground spring; temporarily add 33–100 Ω series R and observe whether framing/glitch events drop.
Fix: Keep series damping; shorten stubs; add stable default pulls; avoid routing near high dv/dt nodes and keep return loops compact.
Pass criteria: Overshoot ≤ X V and double-crossings ≤ N per edge, with 0 framing/glitch fails over Y hours.
RTS/CTS occasionally “deadlocks” — wrong channel mapping/direction or inconsistent fail-safe states?
Likely cause: Direction mix or channel mapping is swapped; during power loss one side drives a fail-safe level that violates the handshake assumptions.
Quick check: Force RTS/CTS to known levels and confirm observed levels on both sides; cross-check schematic net names against isolator channel pins.
Fix: Correct mapping/direction; enforce consistent defaults with pulls; define a power-up handshake policy (ignore CTS until rails stable).
Pass criteria: Deadlocks = X over Y hours, and handshake recovery time ≤ N ms after any rail dip.
GPIO pulses are missed — insufficient minimum pulse width or input-side filtering/synchronization delay?
Likely cause: Pulse width approaches the effective PWmin after propagation + filtering; receiver-side debounce/synchronizer stretches/blocks short pulses.
Quick check: Sweep pulse width and record capture probability; temporarily bypass/relax any input filter and see if missed pulses disappear.
Fix: Widen pulses or convert to level+ack; tune/remove filtering; select a faster/cleaner isolator grade when true pulse fidelity is required.
Pass criteria: Pulses ≥ X ns have loss ≤ N per 10^6 pulses over Y minutes (including noise injection).
PWM duty cycle distorts across the barrier — edge limiting or sampling/filtering effects?
Likely cause: Unequal rise/fall delays (pulse-width distortion) plus added slew control shifts duty; any downstream filter/sync further alters effective duty.
Quick check: Measure high/low times on both sides; compare rise/fall edge timing and quantify duty error vs frequency.
Fix: Reduce unnecessary edge limiting; use an isolator with lower pulse-width distortion; if precise PWM is required, encode as digital words over an isolated serial interface.
Pass criteria: Duty error ≤ X% over Y minutes across operating frequency range, and edge timing asymmetry ≤ N ns.
Occasional lock-up when power order differs — UVLO behavior or latch/clear policy?
Likely cause: UVLO chatter or partial-power states leave outputs in an undefined handshake/control combination; recovery requires a defined reset/clear action.
Quick check: Reproduce with controlled ramps and brownout dips; record whether the isolator outputs enter the intended fail-safe state at each UVLO boundary.
Fix: Add hysteresis to the system-level “power good” gating; enforce reset until both rails are stable; select parts with deterministic UVLO/fail-safe behavior.
Pass criteria: Lock-ups = X over Y randomized power sequences, and recovery time to normal operation ≤ N ms.
Works on bench, fails in a cabinet — chassis ground / shield termination causing common-mode current?
Likely cause: Cabinet bonding/shield termination creates a stronger common-mode path; injected CM current shifts the single-ended reference and triggers false edges.
Quick check: A/B test shield termination (single-point vs both ends) and chassis strap placement; measure CM current on the cable during the failure condition.
Fix: Use a controlled chassis bonding scheme; keep TVS and returns local; reduce edge rate (series R) to cut high-frequency CM excitation.
Pass criteria: In-cabinet run shows ≤ X errors over Y minutes, and measured CM current ≤ N mA at the dominant interference condition.
A “stronger” TVS made things worse — added capacitance degrading edges/threshold margin?
Likely cause: Higher TVS capacitance increases RC loading; slower/rounded edges and threshold uncertainty increase susceptibility to noise and timing jitter.
Quick check: Compare rise/fall times and threshold crossings before/after TVS change; estimate effective line capacitance and verify against receiver requirements.
Fix: Use a low-capacitance TVS; keep TVS at the entry with a clean local return; add series R to control ringing without killing edge margin.
Pass criteria: Rise/fall time stays within X ns target, and total errors ≤ N over Y hours with the chosen TVS.
Production hi-pot occasionally fails — board-edge contamination/spacing/coating process?
Likely cause: Local contamination or moisture lowers insulation resistance; creepage/clearance near the barrier is effectively reduced by residue or coating voids.
Quick check: Visual inspect barrier edges/slots; measure leakage vs humidity; correlate failures to cleaning/coating lot and PCB edge handling.
Fix: Tighten cleaning and bake; increase keepout/slot margin where possible; standardize coating thickness and coverage; lock process parameters to reduce variance.
Pass criteria: Hi-pot at X Vrms for Y seconds with leakage ≤ N µA, and 0 breakdown across the defined sampling plan.
