Isolated Differential Amplifier for Inverter and Drive Measurements
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Topic focus: Isolated Differential Amplifier (high linearity + strong CMTI) for inverter/drive measurement chains. Content stays strictly within this device class and its system integration boundaries.
H2-1. What It Is and Where It Fits
Definition in one sentence
An isolated differential amplifier measures a small high-side differential signal (typically across a shunt or divider), transfers the information across an isolation barrier, and reconstructs a low-side analog output (differential or single-ended) suitable for an ADC/MCU domain.
Where it sits in an inverter/drive measurement chain
- Typical signals: shunt drops (mV to hundreds of mV), bus-divider sense, phase-related differential measurement points.
- Typical environment: large common-mode swings with fast edges (high dv/dt) near switching nodes and gate loops.
- System role: preserve the differential information while preventing common-mode disturbance from becoming output error or EMI.
Why a non-isolated differential amplifier often fails in real drives
Mechanism: common-mode displacement current driven by dv/dt couples through parasitics into the measurement/ADC reference path.
Symptom: output glitches synchronized to switching edges; ADC codes jump at specific PWM phases.
Meaning: isolation and controlled return paths are required to keep dv/dt energy out of the low-side signal chain.
Mechanism: ground bounce and shared return impedance mix power current and sense return.
Symptom: low-current error grows under load; “bench OK, in-system bad”.
Meaning: Kelvin sense and strict domain partitioning are mandatory when common-mode is large and fast.
Mechanism: ADC sampling transients “pull” the driver/output network, creating settling errors that look like measurement noise.
Symptom: errors worsen after ADC change or sampling rate change.
Meaning: output drive, RC isolation, and sampling-aware interface design must be treated as part of the measurement chain.
Scope guard and measurable promises
- This page covers: continuous-time analog-chain metrics (linearity, drift, bandwidth/delay, noise), dv/dt injection mechanisms, ADC interfacing, and layout/validation rules.
- Not covered here: ΔΣ bitstream + digital filtering (see Isolated ΔΣ Modulator page) and integrated sampling digital interfaces (see Isolated ADC page).
- Core promises (verified in later sections): high linearity, stable gain/offset, controlled bandwidth and delay, strong CMTI under dv/dt stress, and system-ready outputs for robust ADC sampling.
H2-2. Architecture Taxonomy
The canonical internal pipeline (what is actually inside)
- Differential front-end: high CMRR input stage that sets the baseline for linearity and input handling.
- Encoding/modulation: converts the analog information into a robust form for barrier transfer (influences noise spectrum, bandwidth, and delay).
- Isolation barrier transfer: capacitive or magnetic coupling that determines coupling capacitance and common-mode injection sensitivity.
- Demodulation + reconstruction: reconstructs the continuous-time analog signal (sets distortion, ripple, group delay).
- Output buffer/interface: drives ADC sampling networks and external RC/anti-alias components (sets settling robustness).
Common output forms and what they change at system level
Analog output (differential or single-ended): flexible connection to external ADCs and filters, but accuracy depends on output drive, ADC sampling transients, and anti-alias choices.
Ratiometric/reference-assisted output: simplifies gain/offset tracking and calibration workflows, but requires clean reference routing and disciplined domain partitioning to avoid reference pollution.
Hard boundary vs. Isolated ΔΣ Modulator and Isolated ADC
- Isolated ΔΣ Modulator: outputs a bitstream and relies on external digital filtering/decimation for final accuracy and bandwidth.
- Isolated Differential Amplifier (this page): provides a continuous-time analog signal whose performance is validated by linearity, bandwidth/delay, noise, and dv/dt immunity in the analog domain.
H2-3. Use Cases in Inverters and Drives
Drive measurement map (what is measured and why it is hard)
- Phase current: 3-channel sensing for motor control feedback; must remain stable under switching dv/dt.
- DC bus monitoring: bus voltage/current for efficiency, derating, and fault correlation.
- Common difficulty: small differential signals ride on large, fast common-mode movement; parasitics and return paths can convert dv/dt energy into measurement error or EMI.
Low-side vs High-side shunt: what changes in practice
Low-side shunt: simpler common-mode conditions, but shared return impedance and power-current ground bounce can contaminate the sense reference if Kelvin routing and partition are weak.
High-side / floating shunt: measurement stays closer to the switching phase and can be cleaner conceptually, but the common-mode swing is larger and faster, making dv/dt injection and EMI coupling the dominant risks.
Why isolated differential amplifiers show up here: they preserve small differential information while breaking the direct common-mode coupling path into the ADC/MCU domain, improving repeatability in real dv/dt environments.
Control-loop interface requirements (kept at system-contract level)
- Bandwidth: too low causes dynamic distortion and phase lag; too high passes switching noise that later becomes ADC code spread.
- Delay / settling: predictable group delay and fast settling protect stability margins and reduce sampling-phase sensitivity.
- Multi-channel consistency: channel-to-channel matching matters for 3-phase symmetry; mismatched delay/scale appears as imbalance.
Protection path thinking (latency + false-trigger immunity)
- End-to-end latency budget: sensing → ADC/decision → response. In high dv/dt systems, “fast enough” must be defined as a measurable chain budget, not a vague requirement.
- False-trigger immunity: dv/dt-induced glitches must not be interpreted as real overcurrent events; immunity is a joint outcome of CMTI, coupling capacitance, interface settling, and layout partition.
H2-4. Key Performance Metrics That Actually Matter
In high dv/dt drives, “good on paper” often fails at system level because metrics are evaluated in isolation. The practical approach is to map each datasheet metric to a concrete system consequence, then derive thresholds from an end-to-end error and stability budget.
Static accuracy metrics (calibration and drift control)
Linearity / INL / THD: determines waveform fidelity; nonlinearity becomes harmonic distortion and bias in inferred current/torque estimation. Treat it as a shape error that cannot be removed by a single-point gain calibration.
Gain error / drift / tempco: sets how quickly calibration becomes invalid over temperature and aging. Practical selection starts from allowed system current error and allocates a fraction to gain drift across the full ΔT range.
Offset / drift: dominates low-current accuracy because offset maps directly into an equivalent current error through the shunt. Offset stability is often more important than peak linearity in light-load efficiency regions.
Dynamic and interface metrics (stability margin and sampling robustness)
Bandwidth & phase delay: bandwidth that is too low introduces phase lag and dynamic distortion; bandwidth that is too high passes switching components that later inflate ADC code variance. Selection should target predictable group delay and settling within the sampling window.
Output drive / load: the amplifier must drive ADC sampling capacitance and any RC networks without creating code-dependent settling errors. Weak drive or poorly chosen series-R can look like “noise” but is actually deterministic sampling disturbance.
High dv/dt reality metrics (immunity, injection, and EMI)
Input common-mode range: defines whether the input stage can tolerate the static common-mode level; dynamic switching behavior is governed by CMTI and coupling paths.
CMTI (kV/µs): indicates how well the signal path resists dv/dt-induced disturbance. Even “100 kV/µs-class” parts can fail at system level when parasitics and return paths convert common-mode energy into differential error.
Barrier capacitance (coupling capacitance): sets the displacement-current injection level under dv/dt, which impacts both EMI and measurement disturbance. Lower coupling reduces injected common-mode current but must be considered alongside timing and noise needs.
Noise density & integrated noise: noise must be evaluated within the effective bandwidth of the chain, including any external filtering, otherwise comparisons are misleading.
H2-5. Error Budgeting for Current Measurement Chains
Step 1 — Lock the error definition (target + combination rule)
- Target (pick one): Total error < X%FS (relative) or |I error| < X A (absolute).
- Work points: low-current (offset-dominant), nominal current (gain-dominant), full-scale (linearity headroom), temperature corners (drift), PWM-edge condition (injection).
- Combination rule: use Worst-case for correlated/guardband items; use RSS for independent random noise terms.
Step 2 — Decompose the chain into budgetable blocks
Total current error is not a single number; it is the sum of multiple mechanisms that must be budgeted separately: shunt + isolated amplifier + ADC/interface + temperature drift + dynamic/settling + dv/dt injection.
- Shunt terms: tolerance, tempco, self-heating shift (included as budget inputs; shunt technology details are out of scope here).
- Amplifier terms: offset, gain error, linearity, drift, noise (use input-referred equivalents where possible).
- ADC/interface terms: quantization and INL contributions plus sampling/hold interaction (kept at interface-impact level, not ADC textbook content).
- Dynamic terms: bandwidth, group delay, settling; filtering-induced phase bias is budgeted as dynamic error.
- Injection terms: dv/dt-coupled displacement current creating output/ADC glitches; must be treated as a separate, verification-heavy item.
Step 3 — Normalize units (so the table actually adds up)
- Voltage → current: I_error = V_error / R_shunt (use input-referred V_error when comparing amplifier and injection terms).
- Voltage → ADC LSB: LSB = V_ref / 2^N, then V_error / LSB gives code impact.
- ppm/°C → %FS drift: gain_drift ≈ tempco(ppm/°C) × ΔT / 10^4 (relationship form for budgeting).
- Noise integration: Vn_rms ≈ e_n × sqrt(BW_eff) (BW_eff set by the effective chain bandwidth, including any external filtering).
Rule: use a single budget reference space—either input-referred (µV) or system-referred (%FS / A / LSB)—and keep every row convertible without ambiguity.
Step 4 — Budget template fields (mobile-safe, spreadsheet-ready)
- Item: Shunt / Amp / ADC / Filter&Dynamic / Injection
- Spec form: µV, ppm/°C, %FS, nV/√Hz, LSB
- Convert to input-referred: equivalent µV at shunt input
- Convert to system: %FS / A / LSB
- Combine rule: Worst-case or RSS (explicit per row)
- Test hook: static, thermal, PWM-edge injection, sampling-settling check
Minimum work-point rows: Low-I, Nominal-I, Full-scale, Temp hot/cold, PWM-edge (injection). Each work-point can reuse the same item rows but with condition-specific values.
Step 5 — Budget dynamic and sampling effects (not optional in drives)
- Bandwidth shortfall: creates amplitude droop and phase bias; treat as dynamic error at the frequencies that matter for the loop/sampling scheme.
- Settling shortfall: appears as code-dependent error at the sampling instant; budget it explicitly as “sampling-time error”, not as random noise.
- Filtering side effects: reduce noise but can add group delay; budget delay and phase as separate terms if stability margin is tight.
Step 6 — Turn the budget into pass/fail checks
- Static: offset/gain/linearity within allocated limits over the defined range.
- Thermal: drift terms within allocation across ΔT.
- Dynamic: settling within the sampling window to meet an allocated error threshold.
- Injection: PWM-edge induced glitches below an allocated µV/LSB/%FS threshold (write the threshold as X in the budget and verify).
H2-6. dv/dt Injection, CMTI Reality, and EMI Mechanisms
The core contradiction: high CMTI on paper, glitches in the field
- dv/dt creates displacement current: I_CM ≈ C_couple × dv/dt
- Coupling paths exist by default: barrier capacitance and parasitics route I_CM into the low-voltage domain.
- Return impedance converts current into error: V_error ≈ I_CM × Z_return
- The visible symptoms: output glitch, ADC sampling error, control jitter, and EMI uplift.
Injection path taxonomy (identify the dominant route)
- Barrier coupling (Cbarrier): PWM-edge synchronized glitches; strongly correlated with dv/dt edges.
- Parasitic-to-chassis/heatsink coupling: measurement changes with chassis bonding and mechanical assembly.
- Return-path sharing (ground bounce): load-dependent drift; “bench OK, system bad” behavior.
- ADC sampling interaction: errors appear at sampling instants; changes with ADC sampling rate or RC interface.
Datasheet CMTI vs system CMTI (what actually decides pass/fail)
- Datasheet CMTI: measured under defined board layout, load, and stimulus conditions.
- System CMTI: determined by coupling capacitance, loop area, return-path impedance, and sampling/interface behavior.
- Practical meaning: the objective is to confine I_CM into a controlled loop and prevent it from generating V_error at sensitive nodes.
How injection shows up (field-friendly signatures)
- PWM-edge synchronized spikes: dominant coupling path is likely Cbarrier/parasitics.
- Sampling-instant-only errors: interface settling and ADC sampling interaction dominate.
- Load-dependent drift: shared return impedance converts switching current into reference movement.
- Chassis bonding sensitivity: chassis/heatsink coupling is likely part of the dominant loop.
Mitigation strategy matrix (kept at chain level, no magnetics deep-dive)
- Geometry control: reduce coupling area and shrink current loops so displacement current has a short, predictable return path.
- Impedance shaping: use small RC damping or output isolation resistors to prevent injected current from producing large V_error at sensitive nodes.
- Sampling-aware interface: design the output RC and drive strength so ADC sampling transients do not amplify injected disturbances.
Verification hooks (tie back to the Injection row in the budget)
- Edge-stress test: measure glitch amplitude and duration under representative dv/dt edges.
- Sampling alignment: verify sampling-time error stays under an allocated LSB/µV threshold.
- Return-path sensitivity: controlled perturbations (bonding/loop adjustments) should change results in a way that confirms the identified dominant path.
H2-7. Front-End Design: Shunt, Scaling, Filtering, and Protection
Front-end role map (what the input network must guarantee)
- Linearity contract: keep the differential signal proportional to the shunt voltage without unintended clipping or rectification.
- Injection control: shape high-frequency energy so dv/dt-coupled disturbances do not dominate the ADC sampling instant.
- Bandwidth shaping: set an effective cutoff that matches control/sampling needs; excess bandwidth only imports noise and edge energy.
- Protection + survivability: survive overvoltage, surge, and ESD without turning protection parasitics into a new coupling path.
Kelvin sensing (stabilize the reference point before filtering)
- Kelvin objective: isolate the measurement reference from power-loop IR drop and switching return currents.
- Correct pick-off: take Kelvin+ / Kelvin− from the shunt element terminals, not from copper that carries load current.
- Routing separation: keep Kelvin traces away from high di/dt loops and switching nodes; avoid crossing coupling “hot zones”.
- Field signature: “low load OK, high load drifts” often points to Kelvin pick-off contaminated by return currents.
Differential RC (a budgetable knob, not “more is better”)
- What it does: limits edge/EMI energy, suppresses spikes, and defines an effective input bandwidth.
- Rdiff role: current limiting into clamps and input structures; also sets interaction with input capacitance and source impedance.
- Cdiff role: differential energy shunt and cutoff setting; reduces edge sensitivity but can slow settling.
- Non-negotiable constraint: choose the cutoff using an allocated settling/phase budget (X/Y placeholders), then back-calculate feasible RC ranges.
Protection placement (survive without importing a new coupling path)
- Place close to the source: clamp/surge elements should intercept energy near the high-side pickup point to keep discharge loops short.
- Short clamp loop: long clamp return paths convert fast current into EMI and can re-inject into Kelvin traces.
- Parasitics matter: clamp capacitance and layout inductance can reshape high-frequency behavior; verify that protection does not increase PWM-edge glitches.
Workflow — “budget first, then set the cutoff”
- Define the useful signal bandwidth for the control/sampling objective (placeholder X kHz).
- Allocate phase/settling error (placeholder Y LSB or Y%FS) from the chain error budget.
- Choose a differential RC range that meets the allocated settling and does not amplify injection at PWM edges.
- Validate with edge-stress conditions (dv/dt representative) and sampling timing; update the Injection and Dynamic rows in the budget.
- Only after the chain passes, refine anti-aliasing at the output interface (covered in H2-8) to avoid pushing bandwidth too high.
Bring-up checklist (front-end acceptance hooks)
- Static: gain/offset within allocated limits across temperature.
- Dynamic: step response settles within the sampling window to < X LSB (placeholder).
- Injection: PWM-edge synchronized glitches < X µV or X LSB (placeholder).
- Protection: after stress events, no abnormal drift or persistent offset shifts are observed (layout loop remains short).
H2-8. Output Interface to ADC / MCU
Output form decision (differential vs single-ended)
- Differential output → differential ADC: strongest immunity to reference movement; keep loading symmetric and routing matched.
- Differential output → single-ended ADC: a defined conversion approach is required; asymmetry can increase sensitivity to injection and sampling kickback.
- Single-ended output → single-ended ADC: simplest topology, but the ground/reference path quality becomes a dominant error lever.
The sampling event model (Cin/S&H is the real load)
ADC inputs are not steady high impedance. During sampling, the input behaves like a switch charging a sampling capacitor (Cin/S&H). That charge pulse draws transient current from the amplifier output, creating droop and settling error if the output network cannot supply charge fast enough.
Drive + RC design (avoid sampling-time deterministic error)
- Allocate a settle threshold: require settling error < X LSB (placeholder) within the ADC sampling window.
- Constrain Rout × Cin: the output path time constant must allow the node to settle before conversion latches the value.
- If an RC is used: treat it as part of both anti-aliasing and sampling buffering, and include it in the Dynamic row of the chain error budget.
Anti-alias sanity (do not over-open the bandwidth)
- Only pass what is needed: bandwidth beyond the useful signal range imports noise density and PWM-edge energy.
- Keep the chain consistent: align output filtering with the sampling plan and the noise/bandwidth priorities set by the performance metrics.
Sampling sync strategy (avoid the dirtiest instants)
- If sampling time is controllable: avoid switching edges and commutation transitions; sample in quieter windows when possible.
- If sampling time is not controllable: the output network must guarantee settle and glitch immunity to the allocated X LSB/µV threshold.
Bring-up checklist (output interface acceptance hooks)
- Sampling transient: charge-pulse disturbance < X LSB/µV (placeholder) at the input node.
- Settling: within the sampling window, the node settles to < X LSB error.
- Rate sensitivity: changing ADC sampling rate does not produce disproportionate error growth.
- Edge + sampling overlap: worst-case PWM-edge overlap still stays within allocated thresholds.
H2-9. Layout, Partition, and Return-Path Rules
Partition contract (Primary / Secondary must stay independent)
- Isolation band = keep-out zone: treat the barrier as a physical “no-cross” region for routing and copper return.
- No return-path bridging: copper shapes that unintentionally reconnect primary and secondary return currents reduce system-level CMTI.
- Cross-domain traffic must be explicit: only the intended isolation component/interface should carry signals across the barrier.
Shortest loops (three loops that decide repeatability)
- Input differential loop: Kelvin → R/C → IN+/IN−. Smaller area reduces dv/dt pickup and edge-synchronous glitches.
- Output-to-ADC loop: OUT → ADC network → return path. A controlled loop reduces sampling-time droop and deterministic error.
- Decoupling loop: supply pin → capacitor → return pin. A short loop prevents reference bounce from becoming measurement noise.
High dv/dt exclusion (keep sensitive traces away from hot zones)
- Switch node hot zone: keep Kelvin pickup, input RC, and IN+/IN− routing away from half-bridge and phase-node copper.
- Gate-drive current loop: avoid running sensitive differential traces parallel to gate-drive loops that carry fast edge currents.
- Coupling test: long parallel runs with hot nodes increase capacitive pickup; shorten and re-route until edge-synchronous artifacts shrink.
Guard and slot actions (reduce coupling area, not just cosmetics)
- Slots: use slots to shrink unwanted coupling and prevent accidental return-path bridging across the isolation band.
- Guards: use guard copper only when its return/termination is defined; a floating guard can become a coupling plate.
- Goal: reduce effective coupling area and control where displacement current returns.
Shielding and ground (when it helps vs when it gets worse)
- Helps: a shield copper region with a defined return path can confine fields and reduce random pickup.
- Hurts: a shield without a controlled return can increase barrier coupling, turning dv/dt energy into injected common-mode current.
- Rule: every shield decision must also define where its displacement current returns.
Stitching strategy (controlled stitching, not random stitching)
- Stitch within a domain: stitching is intended to control return current inside Primary or inside Secondary.
- Avoid bridging near the barrier: stitching that provides a cross-band return shortcut breaks the partition contract.
- Verify with stress: confirm that PWM-edge glitches reduce after stitching changes; otherwise stitching may have created a new coupling plate.
Layout review checklist (10 hard rules)
- Barrier keep-out enforced for routing and copper return (NO CROSS).
- Kelvin pickup taken from shunt terminals, not power copper.
- Input differential loop area minimized (Kelvin → R/C → IN).
- Input R/C and clamp loops kept short; placement close to pickup point.
- Sensitive traces avoid switch-node and gate-loop hot zones (keep-out respected).
- Output-to-ADC loop controlled; differential symmetry preserved when applicable.
- ADC reference/return does not share a high di/dt return segment.
- Decoupling loop minimized (pin → cap → return pin).
- Slots/guards reduce coupling area and do not create floating coupling plates.
- Shield copper includes a defined return path; stitching stays within domain.
H2-10. Validation and Debug: What to Measure First
Step 1 — Bench baseline (lock the static chain first)
- Static linearity: verify gain and linear behavior at DC/low frequency before adding dv/dt stress.
- Offset and drift trend: check offset shift with temperature to confirm baseline stability.
- Purpose: if the chain fails here, the issue is not “inverter noise” yet—fix connectivity, reference, or configuration first.
Step 2 — Dynamic response (settling, bandwidth, and phase delay)
- Step response: confirm the chain settles inside the sampling window to < X LSB (placeholder).
- Bandwidth sanity: ensure bandwidth is not so wide that it imports switching edge energy into the measurement.
- Phase delay: verify group delay remains within Y (placeholder) required by the control/sampling plan.
Step 3 — Controlled dv/dt stress (observe glitch and recovery)
- Glitch amplitude: capture output glitch peak during edges (threshold placeholder X µV or X LSB).
- Recovery time: measure time to return within limit after the edge (placeholder Y).
- Repeatability: if the artifact is edge-synchronous, treat it as injection-path dominated and revisit loops/partition.
Step 4 — Timing correlation (align to the switch node)
- Trigger source: use the switch node or gate signal as the trigger reference to stabilize timing.
- Interpretation: edge-locked glitches indicate coupling/injection; sampling-locked artifacts indicate output-to-ADC interaction.
- Action: adjust loops/placement first for edge-locked issues; adjust output drive/RC and sampling plan for sampling-locked issues.
Step 5 — Fast decision split (what the symptoms point to)
- Device/static chain issue: errors remain even without dv/dt stress; baseline linearity/offset is unstable.
- Output interface / sampling issue: error magnitude changes strongly with sampling rate/window or input acquisition settings.
- Layout / return-path issue: changing probe reference or chassis/ground strategy produces large shifts in artifacts.
- Injection-path issue: artifacts are phase-locked to edges and scale with dv/dt; loop area and coupling dominate.
Probe discipline (measure without creating the artifact)
- Differential probing: prefer differential probes for high-side and sensitive nodes to avoid uncontrolled ground loops.
- Reference awareness: the probe reference path can reroute return currents and create a “measurement-made” glitch.
- Consistency: keep probe placement and reference consistent between runs to make comparisons meaningful.
Pass criteria placeholders (X / Y / N)
- Static: gain/offset/linearity within X (placeholder).
- Dynamic: settling < X LSB within window; delay < Y (placeholder).
- dv/dt stress: glitch peak < X; recovery < Y (placeholder).
- Correlation: edge-aligned artifacts must remain below thresholds across operating conditions.
- Overall: Pass / Conditional / Fail = N (placeholder).
H2-11. Selection Guide and Quick Decision Tree
This section turns “pick an isolated differential amplifier” into a fast, system-driven routing flow: start from dv/dt + common-mode stress, then lock bandwidth/latency and output interface, and only then refine accuracy and drift.
6 questions → 1 shortlist
dv/dt priority “red-line”
Device examples (real P/Ns)
Step 1 — Answer these 6 questions first
- Common-mode swing & dv/dt: what is the worst-case switching node dv/dt and how close is the sensor loop to that node? Target placeholder: CMTI ≥ [X] kV/µs, system-verified.
- Required bandwidth / latency: what control-loop bandwidth and phase delay budget can be tolerated? Target placeholder: BW ≥ [Y] kHz, delay ≤ [T] µs.
- Linearity / distortion: is THD / nonlinearity a limiting factor for the current waveform (FOC estimation error)? Target placeholder: nonlinearity ≤ [A]%FS.
- Low-current accuracy: how small is the current of interest, and how much offset/noise is acceptable at that point? Target placeholder: offset ≤ [B] µV (input-referred), noise ≤ [C] µVRMS.
- Output interface: differential vs single-ended output, and how hard is the ADC input to drive (S/H capacitance, sampling kickback)? Target placeholder: settle to [D] LSB within [E] ns/µs.
- EMI & coupling constraints: what is acceptable common-mode injection through barrier capacitance (system EMI and ADC glitch risk)? Target placeholder: barrier coupling / EMI margin validated on PCB.
Step 2 — dv/dt “red-line” priority (what wins first)
In inverter/drive environments, selection priority typically follows this order:
- System CMTI robustness (device capability + layout realizability + return-path control) comes before “perfect DC accuracy”.
- Output interface stability under ADC sampling often decides repeatability more than headline gain error.
- Only after dv/dt stability is proven, refine drift/linearity to meet the full error budget.
Boundary note (no topic overlap):
If the output required by the system is a bitstream with external digital filtering, route to the sibling page:
Isolated ΔΣ Modulator. If sampling and a digital interface are integrated, route to Isolated ADC.
Quick Decision Tree (visual router)
Use this as a “first-pass” routing tool. Thresholds are placeholders and should be replaced with system targets.
Example device shortlist (real part numbers)
The following parts are commonly used as “isolated differential amplifier” building blocks. They are examples to anchor the selection flow; final choice must match input range, isolation requirement, and ADC interface constraints.
A) Shunt-based current sensing (mV input, differential analog output)
- TI AMC1301 — ±250 mV class, reinforced isolated amplifier, differential analog output.
- TI AMC1302 — ±50 mV class, higher gain for small shunt drops, differential analog output.
- TI AMC1400 — ±250 mV class, reinforced isolation, used when higher isolation working voltage and robust system-level immunity are required.
- TI AMC3301 — ±250 mV class with integrated isolated DC/DC (single-supply on low-side to simplify isolated bias design).
- Skyworks (ex-Silicon Labs) Si8920 — isolated analog amplifier with differential analog output (commonly used in fast current loops).
B) Voltage sensing / scaled signals (V-level input, differential output to ADC)
- TI AMC1311 — up to 2 V range class, differential analog output (often paired with a divider for bus/phase voltage monitoring).
- TI ISO224 — ±12 V single-ended input with differential output (used for industrial ±10 V / ±12 V sensing domains).
- TI ISO124 — classic ±10 V isolation amplifier (legacy-friendly, simple use cases).
C) Legacy / module-style isolation amplifiers (system overhead minimized)
- Analog Devices AD202 / AD204 — transformer-coupled isolation amplifier modules used in older industrial platforms and test equipment.
Practical shortlist rule:
Pick input range first (±50 mV / ±250 mV / 0–2 V / ±10–12 V), then decide whether an integrated isolated supply is beneficial, then validate ADC settling under real sampling conditions, and finally lock drift/linearity against the error budget.
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H2-12. FAQs (Troubleshooting & Acceptance Criteria)
These FAQs are scoped strictly to this page: linearity, dv/dt injection, layout/return-path, output drive into ADC sampling, and validation measurements. Each answer follows a fixed 4-line structure with data placeholders for field-ready pass/fail criteria.
Data placeholders used in Pass criteria
- X: amplitude/error (e.g., [X_glitch] LSB or [X_err]%FS)
- Y: timing/recovery/settling (e.g., [Y_rec] ns/µs or [Y_settle] µs)
- N: occurrence/stat window (e.g., ≤ [N_occ] / 1000 edges or 0 events in [N_min] minutes)
Output shows glitches near switching edges, but static linearity is perfect — injection or ADC kickback?
Likely cause: dv/dt displacement current through the isolation barrier (injection) or ADC sample/hold kickback reflected into the driver (kickback).
Quick check: keep dv/dt the same, then shift ADC sampling phase (or acquisition time) across the PWM period; injection tracks switching edges, kickback tracks the sampling instant.
Fix: reduce loop area/return-path coupling first; then add/retune output RC for ADC settling; finally limit bandwidth (anti-alias) to what the control loop needs.
Pass criteria (X/Y/N): glitch peak ≤ [X_glitch] LSB, recovery ≤ [Y_rec] ns/µs, occurrences ≤ [N_occ]/1000 edges.
Bench is OK, but low-current error drifts a lot in-system — offset drift or Kelvin pickup corrupted by power return?
Likely cause: input-referred offset/drift dominates at low current, or Kelvin sense traces share/close-couple to high di/dt return paths.
Quick check: short the input (or apply a stable known mV source) while running the same PWM; drift that remains is device/temperature, drift that changes with switching is layout/return coupling.
Fix: enforce true Kelvin routing and separation from power loops; improve differential RC at the input; then calibrate offset vs temperature if needed.
Pass criteria (X/Y/N): low-current error ≤ [X_lowI]%FS (or ≤ [X_uV] µV), drift ≤ [Y_drift] ppm/°C, 0 out-of-band events in [N_min] minutes.
Datasheet CMTI is high, but the system still mis-triggers — loop area or ground/reference path?
Likely cause: “system CMTI” is limited by PCB loop area and return-path geometry, not the device headline CMTI alone.
Quick check: measure output glitch while moving/adding a controlled return path (e.g., a short temporary return stitch on the low-side) and compare; strong sensitivity indicates return-path dominance.
Fix: minimize sensitive loop area; keep the barrier keep-out clean; control the low-side return path and decoupling loop; avoid unintended cross-domain capacitance.
Pass criteria (X/Y/N): no false trips under dv/dt ≥ [X_dvdt] kV/µs, glitch ≤ [X_glitch] LSB, ≤ [N_occ]/1000 edges.
Error increases only in a specific PWM duty region — sampling phase or dv/dt overlap point?
Likely cause: sampling window overlaps the highest dv/dt / ringing interval at certain duty cycles, amplifying injection or settling error.
Quick check: sweep sampling phase across PWM for the same duty and log error vs phase; a sharp phase-dependent spike indicates overlap with switching/ringing.
Fix: move sampling away from the switching edge; add damping to reduce ringing; set bandwidth/RC so settling completes before sampling.
Pass criteria (X/Y/N): worst-case error across duty sweep ≤ [X_err]%FS, phase-dependent spike amplitude ≤ [X_spike] LSB, 0 violations across [N_sweep] duty points.
Swapping the ADC made accuracy worse — larger sampling capacitance or insufficient driver RC/settling?
Likely cause: the new ADC input presents higher dynamic load (S/H capacitance, kickback), causing droop or incomplete settling.
Quick check: reduce ADC sampling rate or extend acquisition time; if error improves, the issue is settling/drive rather than DC gain/offset.
Fix: add/retune series resistance and a small shunt capacitor near ADC; ensure the driver settles within the ADC acquisition window; keep anti-alias cutoff consistent with the needed bandwidth.
Pass criteria (X/Y/N): settle to ≤ [X_settle] LSB within [Y_acq] µs, kickback-induced step ≤ [X_kick] LSB, 0 outliers in [N_samples] samples.
High-frequency noise increased, but bandwidth demand is low — filter cutoff too high or no anti-alias at the output?
Likely cause: bandwidth is left “wide open” so switching noise and injection energy are not sufficiently attenuated before ADC sampling.
Quick check: temporarily add a known RC low-pass at the ADC input and compare integrated noise in-band; strong improvement indicates missing/too-high anti-alias filtering.
Fix: set cutoff based on control bandwidth + margin; implement a stable anti-alias RC at the ADC input; avoid excessive phase delay by budgeting first.
Pass criteria (X/Y/N): in-band noise ≤ [X_noise] LSB RMS (or [X_uVrms] µV RMS), no spurs above [X_spur] dB, stable across [N_runs] runs.
Only one phase/channel misbehaves in a 3-phase design — local coupling/layout or channel skew?
Likely cause: local coupling to a nearby switching node/return path, or small but critical differences in routing/RC that change settling or injection susceptibility.
Quick check: swap ADC channels (logical mapping) or swap input RC networks between phases; if the problem follows the physical channel, it is layout/analog; if it follows the ADC mapping, it is interface/firmware timing.
Fix: make all three channels truly symmetric in routing and return paths; keep sensitive loops away from the noisiest dv/dt nodes; standardize the input/output RC values and placement.
Pass criteria (X/Y/N): channel-to-channel mismatch ≤ [X_mismatch]%FS, phase-dependent glitch ≤ [X_glitch] LSB, 0 phase outliers in [N_cycles] cycles.
Gain drift exceeds spec after temperature rise — self-heating or external shunt tempco mapping?
Likely cause: shunt self-heating and tempco dominate the gain error, or local heating shifts analog front-end parameters beyond the assumed thermal model.
Quick check: compare drift with PWM on vs PWM off at the same ambient; then measure shunt temperature (or estimate from power) and correlate gain change with shunt temp.
Fix: treat shunt + amplifier + ADC as one drift budget; improve thermal design around shunt; apply temperature compensation where justified by system requirements.
Pass criteria (X/Y/N): gain drift ≤ [X_gainppm] ppm/°C (or ≤ [X_gainfs]%FS over ΔT), error after warm-up ≤ [X_err]%FS, stable within [N_min] minutes.
Measurement chain “jumps” during EMI testing — real common-mode path or probing/grounding artifact?
Likely cause: common-mode current injection excites the measurement chain, or the probe reference/ground lead creates a false error during fast transients.
Quick check: repeat the measurement with proper differential probing and minimal loop area; compare with a “quiet” reference channel; probe artifacts usually change dramatically with probe grounding.
Fix: fix the measurement method first (true differential probe, short reference path); then mitigate common-mode injection via return-path control and bandwidth/RC tuning.
Pass criteria (X/Y/N): no unexplained steps > [X_step] LSB during EMI stress, glitch recovery ≤ [Y_rec] µs, 0 false events in [N_tests] test runs.
Output occasionally saturates or clamps — input overvoltage spikes or clamp threshold too low?
Likely cause: high-side spikes exceed the input range (or input network resonates), or protection clamps engage too early and “stick” during switching noise.
Quick check: capture input differential voltage with a true differential probe at the device pins; check whether spikes exceed the intended input range and whether clamping coincides with saturation.
Fix: strengthen/relocate input protection close to the source; add damping (R/C) to limit spikes; ensure clamp thresholds align with normal operating peaks.
Pass criteria (X/Y/N): no saturation events in [N_min] minutes, peak input ≤ [X_inpk] (within range), clamp-trigger rate ≤ [N_occ]/1000 edges.
Same design behaves differently across builds/lots — assembly parasitics/cleanliness or fixture return path?
Likely cause: small changes in spacing, contamination, or solder/flux residues change parasitic capacitance and leakage; test fixtures can also create unintended return paths.
Quick check: compare with the same DUT on two fixtures (or with fixture grounding changed); then inspect/clean and re-test; strong fixture sensitivity indicates return-path/measurement dependency.
Fix: lock down assembly cleanliness and critical clearances; standardize fixture grounding/return; add acceptance tests that detect injection sensitivity early.
Pass criteria (X/Y/N): lot-to-lot delta ≤ [X_lot]%FS, no fixture-dependent shift > [X_shift] LSB, pass rate ≥ [N_yield]% over [N_units] units.
dv/dt test passes on bench but is worse in the field — real ringing or Y-cap/shield changed injection paths?
Likely cause: field switching waveform includes ringing/higher edge energy, or system-level Y-caps/shields/grounding create new common-mode current paths not present on the bench.
Quick check: measure real switching node dv/dt and ringing spectrum in the field setup; then repeat with/without shield/Y-cap connection (controlled) to see if glitches follow the return-path change.
Fix: damp ringing at the source; rework return-path and shielding strategy to avoid injecting CM current into the measurement chain; re-validate with the final mechanical/grounding configuration.
Pass criteria (X/Y/N): field glitch ≤ [X_glitch] LSB at dv/dt ≥ [X_dvdt] kV/µs, recovery ≤ [Y_rec] µs, 0 false events in [N_hours] hours.
