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Isolated ΔΣ Modulator for Bitstream-Based Current Sensing

Isolated ΔΣ Modulator for Bitstream-Based Current Sensing

← Back to: Digital Isolators & Isolated Power

Scope Guard
In-scope: isolated ΔΣ modulator bitstream, external digital filtering/decimation, timing & latency, error budgeting, dv/dt & EMI hooks, and HV current/voltage sensing system integration.
Out-of-scope: isolated ADC interface deep dives, isolated differential amplifier analog chains, and isolated DC-DC topology details (link to sibling pages where relevant).

H2-1. What it is & when to use it

The fast definition that prevents wrong expectations

An isolated ΔΣ modulator converts a high-side analog signal into an isolated bitstream. The bitstream is not a voltage value and not a ready-to-use digital word. A numeric measurement is obtained only after external digital filtering + decimation.

Best fit (✅) — when isolated ΔΣ is the correct tool
  • High dv/dt and strong common-mode noise are present (motor drives, inverters, HV bus switching environments).
  • Isolation is mandatory and stable accuracy over temperature is required (current/voltage sensing across a barrier).
  • Digital post-processing is acceptable (MCU/DSP/FPGA resources exist for decimation, synchronization, and calibration).
Not a fit (⛔) — when another path should be chosen
  • Ultra-low latency is required and filter group delay cannot be tolerated in the control loop.
  • Compute/filter resources are constrained (no safe budget for decimation + validation + synchronization).
  • A “read-a-code” interface is expected with minimal digital design (an isolated ADC path is typically better aligned).
Selection gates — the four questions to answer before committing
  1. Target bandwidth: What signal bandwidth must remain accurate after filtering (control bandwidth vs measurement noise bandwidth)?
  2. Allowed latency: What end-to-end group delay is acceptable (filter + decimation + compute + PWM update)?
  3. Isolation requirement: What insulation level and working voltage/lifetime class is required at the system level (use the Safety page for standards/derating details)?
  4. Digital resources: Which implementation is available (MCU/DSP/FPGA), and can it sustain deterministic decimation + synchronization + diagnostics?
Design intent: treat isolated ΔΣ as a signal chain (sensor → bitstream → digital filter → timing closure), not as a drop-in “ADC replacement”.
Diagram — “When to choose an isolated ΔΣ modulator”
Applications Motor phase current HV bus current Isolated shunt/CT Decision criteria Bandwidth Latency dv/dt EMI Safety Choose a path Isolated ΔΣ modulator Isolated diff amp Isolated ADC Focus: choose by bandwidth/latency + dv/dt/EMI + system safety needs (implementation details follow in later chapters).
Visual intent: decision-first. Only node names are shown to avoid stealing content from sibling pages.

H2-2. System architecture

The reference chain used by every later chapter

A complete isolated ΔΣ measurement is a cross-domain chain: sensor → minimal analog conditioning → isolated modulator → bitstream → digital filter/decimator → sample stream → control. The numeric value emerges only after decimation, and the system timing is dominated by filter group delay plus synchronization policy.

Partition intent: keep HV (Primary) and LV (Secondary) domains physically and electrically separated. No return currents should cross the isolation gap; the barrier should be treated as a controlled coupling element with dv/dt and EMI implications.
Interface checklist (what must be planned, not assumed)
  • CLK: defines the bitstream time base; clock quality and routing discipline affect effective noise and susceptibility to dv/dt events.
  • DATA (bitstream): a high-edge-rate digital line; treat as a signal-integrity and EMC participant, not a “slow sensor wire”.
  • SYNC/RESET (optional): enables deterministic alignment across channels and across power cycles; crucial for three-phase current coherence.
  • DIAG/FAULT (optional): used to surface undervoltage/overtemperature/bitstream health indicators for field debugging.
  • Supplies (Primary/Secondary): plan for a clean reference on each side; the power–signal co-design impacts EMI, jitter exposure, and start-up determinism.
Multi-phase note: treat “three modulators” as one synchronized instrument. Shared clocking and repeatable reset policy are prerequisites for meaningful phase comparisons.
Diagram — “End-to-end isolated ΔΣ measurement chain (anchor)”
Primary / HV domain Secondary / LV domain Isolation barrier Sensor Shunt / CT AFE minimal RC Isolated ΔΣ modulator bitstream generator CMTI / dv/dt immune Digital filter + decimator Sample stream numeric values MCU / DSP / FPGA sync + diagnostics + control latency budget closure 3-phase alignment Shared clock + deterministic reset/sync + matched decimation delay → coherent phase current DATA (bitstream) CLK Group delay lives here
Anchor intent: the same diagram is referenced later for filtering, timing closure, dv/dt injection paths, and layout partition rules.

H2-3. ΔΣ modulator fundamentals

The intuition that supports filtering, timing, and error budgeting

A ΔΣ modulator uses oversampling and noise shaping to move most quantization noise out of the signal band. The output is a bitstream that can look random in the time domain, while still carrying a high-fidelity average information content. After digital low-pass filtering + decimation, the in-band noise drops and a stable numeric sample stream emerges.

Three outcomes matter in practice: (1) in-band noise (accuracy & repeatability), (2) out-of-band noise (filtering burden), and (3) group delay (timing closure in control loops).
  • Oversampling: pushes the quantization process to a much higher rate than the signal bandwidth.
  • Noise shaping (NTF intuition): redistributes quantization noise toward higher frequencies (out-of-band).
  • Decimation: removes out-of-band noise and reduces the stream into usable rate/word values with a deterministic delay.
Parameters that control the engineering trade-offs
  • OSR (Oversampling Ratio): higher OSR generally lowers in-band noise, but increases filtering/latency pressure and may constrain output bandwidth.
  • Modulator order (1st/2nd/3rd): higher order provides stronger noise shaping, while increasing sensitivity to implementation details (stability and tone behavior).
  • Idle tones (mention-only): discrete spectral components can appear under certain conditions; treat as a measurable artifact to detect and mitigate during validation.
Terminology (consistent definitions used by later chapters)
  • In-band noise: noise within the signal band that directly sets measurement repeatability and effective resolution.
  • ENOB: an engineering summary of effective resolution after noise, nonlinearity, and filtering.
  • NTF (intuition): a description of how the modulator pushes quantization noise out-of-band.
  • Group delay: deterministic time lag introduced by digital filtering/decimation that must be budgeted for timing closure.
Diagram — ΔΣ loop + noise shaping spectrum (in-band / out-of-band)
ΔΣ modulator loop (concept) Input Integrator Quantizer 1-bit / multi-bit Bitstream Feedback DAC Σ + / − Spectrum intuition Frequency Noise In-band Out-of-band Decimation LPF + downsample Output Sample stream Group delay (budget)
Diagram intent: show the loop building blocks and the frequency-domain “noise moved out-of-band” intuition, without heavy math or filter implementation details.

H2-4. Bitstream formats & interface reality

Bitstream is a fast digital interface (treat it as SI/EMI-critical)

The bitstream is a high-edge-rate digital signal that directly interacts with clock quality, reference return paths, and dv/dt events near the isolation barrier. Practical outcomes show up as effective noise increase, sporadic bit errors, or timing jitter that the decimator cannot fully average out.

  • 1-bit bitstream: common, simple wiring; sensitive to threshold integrity and clock edge placement (often shows up as higher output jitter when the environment is noisy).
  • Multi-bit bitstream (if used): can change quantization behavior and interface burden; treat as an implementation choice that affects filtering and robustness.
  • Clock & data roles: the clock master choice influences reset/sync determinism; clock jitter/duty degradation can map into effective measurement noise.
Engineering intent: plan clock source, edge-rate control, and return-path discipline early, before debugging looks like “analog noise”.
Practical checklist: interface modes and “bitstream-quality” symptoms
Interface mode checklist (describe what exists in the system)
  • Clocked DATA + separate CLK: deterministic sampling; routing and return-path control are mandatory.
  • Embedded/encoded clock (if applicable): reduces separate clock wiring but shifts emphasis to edge integrity and decoder tolerance.
  • SYNC/RESET (optional): enables repeatable alignment after power cycles and across multiple channels.
  • DIAG/FAULT (optional): exposes health indicators that speed up field debugging.
Symptom map (often misdiagnosed as “analog noise”)
  • Bench OK, inverter noisy: dv/dt injection or barrier-coupled common-mode current is reaching the digital threshold/return path.
  • Output jitter spikes near switching edges: clock edge placement and return-path discontinuity are likely contributors.
  • Only one phase is worse: asymmetric routing, local aggressor coupling, or different return path geometry is likely.
  • Temperature/posture dependent instability: borderline SI margins exposed by impedance/edge-rate drift or harness movement.
Diagram — bitstream + clock routing and return-path discipline (no cross-barrier return)
Primary / HV side Secondary / LV side Isolation barrier DATA driver DATA receiver CLK source CLK input Series R DATA (bitstream) CLK Return path (HV) Return path (LV) NO return Edge-rate control
Diagram intent: show that DATA/CLK are fast digital nets. Each side owns its return path; the barrier must not become a return conductor.

H2-5. Digital filtering & decimation design

The two top objectives: in-band noise vs. system latency

A decimation chain is not “just a low-pass filter.” It is a controlled pipeline that simultaneously reduces in-band noise and sets a deterministic group delay. Every stage must be justified against these two objectives, otherwise the design becomes either too slow (excess delay) or too noisy (insufficient stopband rejection / ripple).

Pipeline “building blocks” used by most practical designs: CIC / SincN (coarse decimation) → FIR compensation (shape the passband / stopband) → optional notch (targeted cleanup) → downsample (set output data rate).
  • In-band noise: driven by OSR, passband ripple, and how much out-of-band energy is removed before downsampling.
  • Group delay: dominated by stage order / taps and the number of decimation stages (must be budgeted explicitly).
Practical filter blocks and the trade-offs that matter
CIC / SincN (or multi-stage CIC): computationally efficient for large decimation ratios, but introduces passband droop and limited stopband control. Treat it as a “coarse reduction” stage that must be followed by compensation if the passband flatness matters.
FIR compensation: corrects droop and sets the passband / stopband explicitly. The cost is tap count (compute) and added delay.
Notch / anti-ripple (optional): a targeted fix for stubborn discrete components (e.g., switching-related lines). Use sparingly: it can add delay and complicate phase behavior.
Engineering rule: stopband rejection protects against aliasing after downsampling; passband ripple and droop control the “effective noise floor” in the band of interest.
Goal-driven combinations (no wide tables)
Target: Low noise (highest fidelity)
  • Pipeline: modest-ratio CIC → longer FIR (tight passband ripple) → optional notch
  • What it buys: best in-band noise and clean spectrum margin
  • Cost: higher compute and higher group delay
Target: Low latency (fast control response)
  • Pipeline: multi-stage CIC with minimal FIR (or short FIR) → downsample early
  • What it buys: minimal group delay / quicker data availability
  • Cost: passband droop/ripple control is weaker; noise performance may degrade
Target: Low compute (MCU/DSP budget constrained)
  • Pipeline: CIC-heavy chain → small FIR only for essential compensation
  • What it buys: easy real-time implementation and predictable load
  • Cost: tighter specs (ripple/stopband) are harder; may require careful OSR choice
How to back-solve OSR and output data rate from real constraints
  1. Define signal bandwidth: separate “measurement bandwidth” from “control bandwidth” to avoid over-design.
  2. Set a hard latency ceiling: specify a maximum allowed group delay for the measurement path.
  3. Specify a noise target: choose an in-band noise / repeatability target that the system needs (not only the datasheet).
  4. Choose ODR (output rate): ensure ODR supports the bandwidth needs and the control update cadence.
  5. Back-solve OSR and decimation ratio: OSR sets the raw-to-ODR reduction and the burden of stopband suppression before downsampling.
Outcome: the decimation pipeline becomes an intentional design, not a default filter block copied from a reference design.
Diagram — decimation pipeline (CIC → FIR → notch → downsample) with key metrics tags
Decimation pipeline (concept) Bitstream in CIC / Sinc N (coarse) FIR comp (shape) Notch (optional) Downsample set ODR Output stream (samples) Output rate ↓ Passband Stopband Delay + Passband ✓ Stopband ✓ Compute + Delay + ODR defined here Alias risk control Key metrics: Output rate (ODR), Passband, Stopband, Group delay.
Diagram intent: show where ODR is set, where stopband prevents aliasing, and where group delay accumulates—without math-heavy detail.

H2-6. Timing, latency & synchronization

Latency sources and the only budget that matters: end-to-end

Group delay is not a single number hidden in a datasheet. It is the sum of multiple deterministic contributions: filter delay, pipeline/buffering delay, and the system update cadence. Multi-channel systems must treat delay and skew as first-class constraints, especially when comparing phase-related currents (e.g., 3-phase sensing).

Latency budget checklist (write it down, then verify it)
  • Sampling event: define the “true time” reference for each channel.
  • Decimation group delay: set by stage order / taps and decimation structure.
  • Compute window: MCU/DSP execution latency and scheduling jitter.
  • Actuation update: control update boundary (e.g., PWM latch / frame timing).
Engineering intent: treat the measurement output as “time-stamped information” with a known delay, not as an instantaneous value.
Synchronization strategies (choose by strictness and diagnosability)
Tier 1 — Basic (shared clock, identical decimation)
  • Mechanism: single clock domain + identical filter configuration across channels
  • What it ensures: consistent steady-state group delay matching
  • Risk: power-up/reset ordering can still introduce alignment ambiguity
  • Acceptance: channel-to-channel skew within X (placeholder)
Tier 2 — Advanced (reset/sync alignment + fixed offset correction)
  • Mechanism: synchronous start/reset + explicit alignment event
  • What it ensures: repeatable alignment across power cycles
  • Cost: extra pins/firmware state handling
  • Acceptance: skew stable within X over Y minutes (placeholder)
Tier 3 — Strict (calibration / time-tag / diagnosable alignment)
  • Mechanism: calibration step and/or time-tagging to track effective sample time
  • What it ensures: traceable alignment under temperature, aging, and resets
  • Cost: extra validation and diagnostic telemetry
  • Acceptance: residual alignment error below X across Z conditions (placeholder)
Diagram — time alignment (group delay, skew, and correction)
Multi-channel timing alignment (concept) Time → CH-A CH-B CH-C Bitstream Decimation Output sample Bitstream Decimation Output sample Bitstream Decimation Output sample Group delay Skew Alignment correction Key concepts: group delay (per-channel) + skew (between channels) + explicit correction for repeatable alignment.
Diagram intent: show that “alignment” means output samples correspond to the same effective time, after accounting for group delay and skew.

H2-7. Accuracy & error budget

Purpose: make accuracy reviewable and testable

An error budget is a design-review tool, not a spreadsheet exercise. The intent is to force every accuracy claim to be attached to a source, a condition, a mitigation, and a verification method. For isolated ΔΣ systems, the budget must cover both analog contributors (front-end, sensor, drift) and digital contributors (bitstream integrity, clock/threshold sensitivity, decimation effects).

  • Target: Total error @ bandwidth under a defined condition set (temperature, ODR, dv/dt, EMI).
  • Method: sum contributions with consistent units and explicit assumptions (placeholders X/Y/Z).
  • Outcome: the design becomes auditable: “what dominates” is obvious and mitigation is prioritized.
Error tree: keep coverage complete without crossing domains
Organize the budget as a tree so every term has a home and no contributor is counted twice:
Branch A — Front-end & sensor
  • Gain / offset: resistor ratio, shunt tolerance, bias currents
  • Temperature drift: TCR, thermal gradients, self-heating
  • Nonlinearity: front-end headroom, saturation, common-mode dependency
Branch B — Modulator + reference/clock
  • In-band noise: quantization residue after OSR + decimation
  • Clock jitter impact: timing uncertainty mapping into amplitude noise/distortion
  • Reference sensitivity: reference drift/noise coupling into the measurement
Branch C — Digital chain & bitstream integrity
  • Bitstream quality: threshold/edge disturbances causing random errors or correlated artifacts
  • Decimation response: passband ripple/droop altering effective noise in-band
  • Aliasing failures: insufficient stopband rejection before downsampling
Rule: each leaf term must map to a measurable verification step, otherwise it is not a budget term.
Error budget entry template (card fields, mobile-safe)

Use one entry per source. Keep the fields stable so design review and bring-up checks share the same language.

Template entry
  • Source: (e.g., Shunt tolerance / Offset / Clock jitter)
  • Condition: (temperature range, bandwidth, ODR, OSR, dv/dt class)
  • Contribution: X (placeholder; use one unit system consistently)
  • Mitigation: (layout symmetry, better grade part, calibration, filtering)
  • Verification: (injection test, shorted-input noise, correlation with switching, A/B config)
Practical tip: treat “verification” as a test plan snippet; it prevents untestable budget terms from surviving design review.
Map bitstream issues into equivalent noise or distortion
Bitstream “quality” becomes an accuracy term when it changes the statistics of the decimated output:
Random-like disturbances → equivalent in-band noise
  • Symptom: output variance rises; noise floor lifts in-band
  • Mechanism: threshold jitter / edge uncertainty converts into random bit errors
  • Budget term: add as in-band noise contribution under the relevant condition
Correlated disturbances → spurs / distortion
  • Symptom: discrete tones appear; repeatable artifacts track switching patterns
  • Mechanism: periodic coupling modulates sampling/threshold conditions
  • Budget term: treat as distortion/spur term; verify by correlation to the aggressor
Fast sanity checks (verification-oriented)
  • Fix the window: same ODR, same bandwidth, same statistic window for A/B comparisons
  • Correlate: compare noise/spur change versus switching edges or dv/dt events
  • A/B toggles: edge-rate / series R / routing symmetry (observe impact on output statistics)
Calibration strategy: accuracy vs latency vs maintenance
One-time calibration (factory / bring-up)
  • Benefit: simple workflow and stable runtime behavior
  • Risk: drift across temperature/aging becomes a residual error term
  • Budget linkage: keep “temp drift” and “long-term drift” explicit
Online calibration (in-field / runtime)
  • Benefit: compensates drift under large temperature spans and stress
  • Cost: requires timing windows, state handling, and diagnostic traceability
  • System impact: can change effective latency and alignment; document it in the timing budget
Acceptance (placeholder): Total error @ bandwidth < X under condition set Y; verified by method Z with fixed statistics window.
Diagram — error budget tree (leaf terms roll up to Total error @ bandwidth)
Total error @ bandwidth Front-end & sensor Modulator + clock Digital chain Gain Offset Temp drift Shunt tol Nonlinearity In-band noise Clock jitter Reference Linearity Bit errors Ripple Aliasing Droop Mitigation Layout / parts / calibration Verification Injection / stats / A-B Each leaf must have: Condition + Contribution + Mitigation + Verification (placeholders X/Y/Z).
Diagram intent: a review-ready error tree that rolls up leaf terms into Total error @ bandwidth.

H2-8. Isolation barrier effects

CMTI, barrier capacitance, and EMI: symptom-driven engineering view

Isolation in ΔΣ systems is not only a safety boundary. Under fast common-mode transitions (high dv/dt), the isolation barrier can form a coupling path that injects disturbance into the secondary reference and digital thresholds. The result is often seen as noise lift, bit errors, or unlock events.

Symptom → likely cause → first mitigation knobs
  • Noise spikes during switching edges: dv/dt injection perturbs thresholds/sampling → tighten CMTI class, control edge rate, enforce strict return-path discipline.
  • EMI fails / strong common-mode radiation: barrier capacitance creates a CM current path → reduce CM loop area, manage CM current closure, avoid uncontrolled cross-barrier returns.
  • One channel worse (asymmetry): layout/return asymmetry magnifies coupling → enforce symmetry, consistent edge shaping, consistent reference boundaries.
CMTI target classes and what must be checked in the datasheet
Use CMTI as an engineering filter, then validate the test conditions match the system reality.
CMTI class (quick screening)
  • Class A: ≥ 50 kV/µs (baseline industrial)
  • Class B: ≥ 100 kV/µs (strong dv/dt environments)
  • Class C: ≥ 150 kV/µs (very aggressive switching immunity)
Datasheet conditions (must be read with the number)
  • Output state/load: which logic level, what loading, what receiver threshold class
  • Supply & temperature: VDD range and test temperature (room vs extremes)
  • dv/dt waveform: amplitude, edge slope definition, repetition rate
  • Failure definition: transient glitch allowed or counted as failure; lock/unlock criteria
Engineering link: treat barrier effects as error-budget conditions (dv/dt class, EMI class), not as “rare corner cases.”
Scope boundary

Safety certificates, VIORM/VIOTM, partial discharge, creepage/clearance, and compliance documentation belong in the Safety & Compliance section/page (link only; do not duplicate standards text here).

Diagram — dv/dt injection path across the isolation barrier
HV domain LV domain ISO barrier Switch node dv/dt CM current Cbar Coupling Secondary reference Digital threshold / sampling Disturb Bit errors / Noise CMTI class ≥ 50/100/150 Key path: dv/dt → CM current → barrier coupling (Cbar) → reference disturbance → threshold shift → bit errors/noise.
Diagram intent: visualize the coupling path so mitigations can be placed on the correct loop and boundary.

H2-9. Analog front-end & protection

Input conditions: range and common-mode reality

The analog front-end for an isolated ΔΣ modulator is the short segment that defines whether the system behaves like a precision instrument or like a noisy digital link. The key is to write the input conditions as an engineering condition set (range, common-mode movement, dv/dt environment, and expected spike energy), then design a minimal network that prevents the input from being pushed into nonlinearity or overload.

High-side vs low-side shunt (what changes)
  • High-side shunt: common-mode rides on switching nodes; dv/dt injection and spike stress are usually dominant.
  • Low-side shunt: common-mode is calmer, but ground bounce and shared return impedance can corrupt Kelvin sensing.
  • Condition set placeholders: differential input range X, common-mode swing Y, spike amplitude Z, dv/dt class N.
Review rule: if the worst-case condition set is not written down, the protection network cannot be proven sufficient.
Protection without destroying bandwidth: layer the functions

A robust front-end uses layered functions. Each component must have a single job: limit spike current, remove the most dangerous HF energy, or clamp true fault events. Over-using any one layer typically trades away bandwidth, phase margin, or symmetry.

Layer 1 — limit & damp (spike current control)
  • Series R / small RC: reduces edge energy into the input, limits peak current during spikes.
  • Risk if oversized: bandwidth loss and extra phase lag in the measurement chain.
  • Symmetry: keep differential paths matched to avoid offset/distortion terms.
Layer 2 — minimal anti-alias (do the minimum necessary)
  • Key point: oversampling is not a guarantee against fold-in from strong HF spikes.
  • Goal: suppress switching residue/edge bursts that would alias into the in-band region after decimation.
  • Constraint: keep the filter light enough to respect the latency and phase budget.
Layer 3 — clamp (only for real overload events)
  • Clamp / TVS (if needed): keeps inputs within safe limits during fault transients.
  • Hidden cost: parasitic capacitance and asymmetry can become accuracy terms (add to the error budget).
  • Placement: place to control surge current loops; keep Kelvin sensing untouched.
A “minimal network” is preferred: every extra component must justify itself as a measurable risk reduction.
Minimal front-end networks by measurement type

These are minimal patterns to start review and bring-up. They must be tuned against the condition set (range, bandwidth, dv/dt, and spike energy). The intent is to prevent overload and fold-in while keeping the measurement chain fast and symmetric.

Pattern A — Motor phase shunt (high dv/dt)
  • Must-have: true Kelvin sense from shunt pads to the network and modulator input.
  • Typical: series damping (Rlimit) + light differential RC.
  • Optional: clamp only if overload events exist; keep parasitic symmetry.
Pattern B — HV bus shunt (large spikes, slower bandwidth)
  • Priority: spike energy control and defined input headroom.
  • Typical: stronger damping than phase-current chains; minimal anti-alias matched to target bandwidth.
  • Verification: step/edge injection test to confirm no fold-in dominates in-band noise.
Pattern C — Current transformer (CT)
  • Must-have: burden network that prevents CT saturation and defines the measurement range.
  • Typical: burden + damping + light RC; clamp only if open-circuit risk exists.
  • Accuracy hook: CT behavior becomes an error term (temperature and frequency dependence).
Boundary rule: do not expand into isolated differential amplifier architectures here; keep the scope at “modulator input network only.”
Front-end review checklist (keep it short and enforceable)
  • Kelvin is real: sense lines return to shunt pads (not to power copper).
  • Symmetry: differential paths and components are matched (avoid ΔC/ΔR accuracy terms).
  • Headroom: worst-case spikes cannot push the input into overload/nonlinearity.
  • Minimal anti-alias exists: HF switching energy is not allowed to fold into band.
  • Clamp is justified: protection parts are used only for defined fault events.
  • Loop control: spike current loops are compact; sensitive nodes are not inside power loops.
  • Verification ready: injection and A/B toggles are defined before layout freeze.
Diagram — typical input network (minimal) with Kelvin & return-path discipline
Shunt / CT Kelvin Rlimit RC Clamp / TVS (optional) ΔΣ Modulator High-current return loop (keep away) Sensitive zone Signal (diff) Return stays local Minimal chain: Shunt/CT → Rlimit → RC → (Clamp/TVS) → ΔΣ input; Kelvin sense must avoid power return copper.
Diagram intent: show the minimal input network and enforce Kelvin/return-path separation to prevent accuracy loss.

H2-10. Layout & EMC hooks

Primary/Secondary partition rules (PCB-review ready)
  • Do not cross the isolation slot: no trace, no copper, and no return path is allowed to “sneak” across.
  • Keep domains self-contained: primary returns must close on primary; secondary returns must close on secondary.
  • Separate power loops from sense loops: high-current loops must not surround the input/Kelvin area.
  • Control coupling on purpose: if any CM path is introduced for EMI, it must be deliberate and documented (details belong in Safety page).
Bitstream/clock routing hooks (edge + return control)
Treat clock and bitstream as fast digital nets. Their stability depends on edge-rate control and a clean, local return path that stays inside the domain.
Practical hooks
  • Return path: route clock/data with an adjacent reference so the return stays tight and local.
  • Series R placement: place near the driver to shape edges before reflections build.
  • Keepout: define a keepout corridor near the isolation slot and dv/dt aggressor areas.
  • Symmetry: keep paired lines similar to avoid skew and asymmetry-driven coupling.
EMI symptoms → which loop to check first
  • Noise worsens only during switching edges: check cross-slot coupling and secondary reference disturbance loops.
  • Radiated EMI increases after a layout revision: check loop area growth and unintended return detours.
  • One channel becomes worse than others: check asymmetry in routing, return, and keepout adherence.
  • Series R improves stability drastically: edge-rate/reflection control was missing; verify driver-side placement.
  • Adding a CM path helps EMI but introduces constraints: the trade-off exists; detailed limits belong in the Safety page.
Diagram — PCB partition with isolation slot, keepout, and return-path discipline
Primary Secondary ISO slot Guard Clock/Data Keepout Clock/Data Keepout HV switching loop Sense / Kelvin front-end Digital filter / MCU Clock/Data routing Return stays in Primary Return stays in Secondary No cross-slot return Stitch (optional) Focus: partition + keepout + local returns; avoid any unintended cross-barrier loop that injects CM noise.
Diagram intent: enforce partition rules and keepout corridors so PCB review can spot cross-slot return and coupling risks quickly.

Validation & production test

What must be verifiable (and repeatable)
  • In-band noise: report noise after the same decimation settings (baseline filter profile locked).
  • Linearity / gain / offset: multi-point sweep with the same input fixtures and wiring.
  • Latency / group delay: step-response alignment from input event → decimated output update.
  • Drift: time and temperature drift tracked with a fixed measurement window.
Pass/fail criteria should be expressed on the decimated sample stream, not by visually “judging” the raw bitstream.
Bring-up test sequence (bench)
  1. Interface sanity: confirm clock presence, data toggling, and stable logic thresholds at the receiver.
  2. Bitstream health quick checks: detect stuck-at (all 0/1), abnormal transition density, and unstable duty/edge behavior.
  3. Baseline filter lock: freeze one decimation profile (OSR/output rate/FIR taps) as the measurement baseline.
  4. Noise measurement: capture a stable window; report RMS noise and PSD in-band (same window length every run).
  5. Linearity sweep: apply multi-point known input; compute gain/offset and nonlinearity (report method fixed).
  6. Latency check: apply a repeatable step; measure time-to-valid output and effective group delay.
  7. Drift snapshot: short time drift check; optional temperature points if the setup is available.
A single “golden” firmware build + a single baseline decimation profile avoids argument about denominators and windowing.
System validation under switching dv/dt (stress plan)
  • Switching frequency sweep: step fsw across operating range and observe noise/lock/health indicators.
  • Edge-rate knob: adjust gate resistor/drive strength and confirm whether measurement noise follows dv/dt severity.
  • A/B wiring & grounding: controlled changes (shield bond, return routing, keepout adherence) to locate dominant coupling paths.
  • Correlation: tie measurement artifacts to events (gate transitions, PWM edges, resets, UVLO) using time markers.
High-voltage insulation tests (Hi-pot / partial discharge) belong to the Safety & Compliance page; this section stays on measurement robustness and manufacturability.
Production test: minimal set (covers most failure modes)
  • Digital self-check: activity counters for CLK/DATA; basic status pin sampling if available.
  • Bitstream health metric: transition-rate window, stuck-at detection, and density stability limits.
  • Calibration flow check: 1–2 point calibration execution + NVM write/read integrity + checksum.
  • Fast noise spot-check: short capture window; compare against golden distribution limits.
Reference items (example part numbers for repeatable validation)
  • Digital filter IC (optional): TI AMC1210 (4-channel decimation filter for ΔΣ modulators).
  • Isolated ΔΣ modulators (golden sample options): AMC1306M05 / AMC1306M25, AMC1305M05 / AMC1305M25, AD7400A, AD7401A, AD7403, ADuM7701.
  • Evaluation hardware (optional): EVAL-ADuM7701, EVAL-AD7403FMCZ (useful for interface/decimation bring-up baselines).
Final selection should match the insulation class, input range, interface style, and system dv/dt profile.
Diagram: validation setup overview
Signal Source Current / Voltage Stimulus Step / Sine / DC DUT AFE + Isolated ΔΣ Modulator Bitstream (DATA) + Clock (CLK) Health / Status (optional) Acquisition FPGA / MCU Counters + Capture Digital Filter / Decimator Baseline profile locked Metrics Noise Latency Drift dv/dt fsw
The same baseline decimation profile must be used for all A/B comparisons; otherwise noise and delay numbers are not comparable.

Applications & IC selection logic

Application cards (system view)
Motor / inverter phase current (3-phase)
Goal: stable phase current feedback under high dv/dt and fast PWM edges.
Pain: common-mode injection, channel-to-channel skew, and restart alignment.
Key specs: bandwidth/ODR, group delay, CMTI class, barrier capacitance, temperature drift.
Hooks: shared clock strategy, reset alignment, bitstream integrity, tight partition + return control.
Validation: fsw sweep + edge-rate knob + multi-channel alignment check (see Validation section).
HV bus current / shunt monitoring
Goal: accurate bus current under wide common-mode swing and harsh EMI.
Pain: drift across temperature, EMI-driven noise bursts, and layout-dependent coupling paths.
Key specs: input range, drift, CMTI, barrier capacitance (EMI path), diagnostics/health behavior.
Hooks: minimal front-end protection without killing bandwidth; controlled edge rate on CLK/DATA.
Validation: compare noise distribution across dv/dt and switching conditions (same filter profile).
Selection scorecard (how to rank candidates)
1) Bandwidth / Output data rate
What it affects: control bandwidth and measurement responsiveness.
Red flags: ODR too low for the control loop; OSR too high for the allowed delay.
Quick check: compute ODR margin vs required signal bandwidth + guard.
2) Latency / Group delay
What it affects: phase margin of the current loop and multi-channel alignment.
Red flags: delay dominates the sampling→compute→PWM update pipeline.
Quick check: keep total delay within the control budget (system-level).
3) CMTI class (dv/dt immunity)
What it affects: noise bursts, missing codes, or lock/health failures during switching events.
Red flags: lab noise spikes that track switching edges more than input signal level.
Quick check: compare candidate CMTI rating and test conditions to the system dv/dt profile.
4) Barrier capacitance (common-mode EMI path)
What it affects: coupled common-mode current and radiated/conducted emissions pressure.
Red flags: emissions sensitive to cabling/chassis and “mysterious” ground reference shifts.
Quick check: treat barrier capacitance as an EMI coupling channel; plan return paths accordingly.
5) Drift & calibration behavior
What it affects: absolute accuracy across temperature and long-term stability.
Red flags: unacceptable warm-up drift or required calibration frequency too high.
Quick check: define calibration policy (factory-only vs periodic) before locking the part.
6) Interface style & diagnostics
What it affects: bitstream robustness, EMC knob options, and production test coverage.
Red flags: no practical way to detect stuck-at or degraded bitstream quality in production.
Quick check: ensure the receiver can implement health metrics and alignment strategy.
Example BOM (IC part numbers)
Isolated ΔΣ modulators (bitstream output)
  • TI: AMC1306M05, AMC1306M25
  • TI: AMC1305M05, AMC1305M25
  • ADI: AD7400A, AD7401A, AD7403, ADuM7701
Choose input range and interface style first, then rank by CMTI/barrier capacitance and drift.
Digital filtering (optional dedicated IC)
  • TI: AMC1210 (4-channel decimation filter for ΔΣ modulators)
Many systems implement decimation in FPGA/MCU; a dedicated filter IC is useful when firmware resources are tight or when a fixed, validated filter path is preferred.
Quick pairings (names + part numbers; implementation stays on sibling pages)
  • Motor / inverter: Isolated gate driver (UCC21520 / UCC21750 / ADuM4135) + isolated ΔΣ modulator (e.g., AMC1306M05 / AD7403) + isolated bias transformer driver (e.g., SN6505A).
  • HV bus sensing: Isolated ΔΣ modulator (e.g., AMC1306M25 / AD7400A) + receiver/decimation (FPGA/MCU or AMC1210) + EMC-controlled CLK/DATA edges (series-R + return discipline).
Detailed gate-drive protection, isolated power topologies, and interface implementations are handled on their dedicated pages to avoid scope overlap.
Diagram: selection decision tree (ΔΣ modulator focus)
Bandwidth ODR / OSR Latency Group delay CMTI dv/dt class Barrier C EMI path Diagnostics Health pins Cost BOM Decision order: performance → robustness → manufacturability
Lock bandwidth/latency first, then validate dv/dt immunity and EMI coupling paths before final cost optimization.

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FAQs

Each answer is fixed to 4 lines for fast field triage and measurable acceptance: Likely cause / Quick check / Fix / Pass criteria (threshold placeholders X/Y/N).
Bitstream looks “jittery,” and decimated noise is out of spec—clock jitter or bit errors first?
Likely cause: receiver-side clock jitter or EMI/SI-driven bit errors raising effective in-band noise.
Quick check: A/B swap the clock source or reduce CLK edge-rate; run a bitstream health window (stuck-at + transition density + error counters).
Fix: tighten CLK integrity (source/route/termination), add series-R near the driver, and improve return/partition to cut error injection.
Pass criteria: in-band noise ≤ X (RMS, defined band) over Y s with baseline decimation locked; bit error/health events ≤ N per 10^6 bits.
3-phase currents match in magnitude but are phase-misaligned—different group delay or unsynced start?
Likely cause: channel-to-channel group delay mismatch (filter/OSR differences) or reset/sync not aligned across modulators.
Quick check: force identical decimation profiles on all phases and measure skew; then re-test with a shared reset/sync edge across channels.
Fix: lock per-channel OSR/filter settings, distribute a common clock, and implement deterministic reset/sync sequencing for aligned startup.
Pass criteria: channel-to-channel skew ≤ X samples (or ≤ X µs) after sync; repeatable across Y power cycles; residual group-delay delta ≤ N samples.
Bench noise is low, but in-system noise explodes—dv/dt injection path or barrier-C common-mode loop?
Likely cause: dv/dt-driven common-mode current couples through the barrier capacitance and disturbs thresholds/returns on the secondary side.
Quick check: sweep gate edge-rate (or dv/dt severity) and observe whether noise scales with switching edges; A/B chassis/return bonding to see coupling sensitivity.
Fix: enforce primary/secondary partition, control return paths, slow CLK/DATA edges where safe, and reduce injection loops near the barrier.
Pass criteria: noise increase vs bench ≤ X% under dv/dt=Y (kV/µs) and fsw=N; no lock/health faults during switching stress.
Measurement error shifts with switching frequency—input RC shaping or insufficient notch/stopband rejection?
Likely cause: front-end RC changes effective bandwidth/phase, or decimation stopband/notch is too weak against switching-related content.
Quick check: hold input constant and sweep fsw; A/B front-end RC (small controlled change) and compare against an alternate decimation profile with stronger stopband.
Fix: tune minimal RC for spike control without phase damage, and strengthen digital stopband/notch where switching artifacts leak into band.
Pass criteria: gain/offset variation across fsw sweep ≤ X% from Y to N kHz with baseline settings; spurs in-band ≤ X dBc.
Drift is obvious at low/high temperature—shunt/AFE drift or modulator offset drift first?
Likely cause: temperature drift from shunt and front-end network dominates, or modulator offset/gain drift is not being calibrated.
Quick check: hold input at a known zero/constant point; compare drift with input shorted (front-end dominated) vs normal wiring (shunt/network dominated).
Fix: tighten the drift budget (component TC + layout thermal gradients) and define a calibration policy (factory + optional periodic correction).
Pass criteria: drift ≤ X (ppm/°C or µV/°C equivalent) from Y to N °C after warm-up; recalibrated error ≤ X% of full scale.
One phase occasionally “jumps”—crosstalk bit errors or digital filter overflow/saturation?
Likely cause: occasional bit errors from crosstalk/return disturbance, or downstream accumulator overflow/saturation in decimation.
Quick check: log bitstream health flags and filter overflow flags with timestamps; A/B add series-R on the affected lane and see if jumps disappear.
Fix: harden SI/return (spacing, reference, edge control) and ensure decimation math has headroom (word length, saturation handling, scaling).
Pass criteria: no output step glitches > X LSB in Y minutes; overflow/saturation events = 0 (or ≤ N); health errors ≤ N per 10^6 bits.
Bandwidth is sufficient but control “feels slow”—group delay or MCU filtering compute bottleneck?
Likely cause: group delay from decimation dominates the loop, or the MCU/FPGA cannot sustain the required filtering at the chosen ODR.
Quick check: compute end-to-end latency (sample→decimate→control→PWM) and profile CPU/FPGA load; A/B reduce filter complexity and observe response.
Fix: rebalance OSR/ODR and filter pipeline for latency, and move heavy filtering to hardware acceleration if needed.
Pass criteria: total measurement latency ≤ X µs; CPU/FPGA utilization ≤ Y% at ODR=N; missed-deadline count = 0 over Y minutes.
EMI test fails but functionality is OK—reduce edge rate first or fix return/partition first?
Likely cause: fast edges on CLK/DATA and uncontrolled return paths excite common-mode radiation and barrier coupling paths.
Quick check: A/B add or increase series-R to slow edges; if emissions barely move, prioritize partition/return fixes and keepout enforcement.
Fix: control edge-rate within timing margin and close return paths; keep all digital loops compact and away from the isolation barrier region.
Pass criteria: EMI margin ≥ X dBµV at Y MHz (and key bands); measurement noise penalty from edge-control ≤ N% at nominal dv/dt.
Readings are unreliable for the first seconds after power-on—filter fill time or reset/sync timing?
Likely cause: decimation pipeline fill/settling dominates startup, or reset/sync sequencing leaves channels misaligned initially.
Quick check: measure time-to-stable output with a fixed input; A/B enforce deterministic reset/sync and compare stabilization time and channel skew.
Fix: gate the output until the decimator is filled, and align reset/sync to a known clock boundary for repeatable startup.
Pass criteria: settle to within X% of final value within Y ms after reset; initial channel skew ≤ N samples across Y power cycles.
Same hardware, different lots show very different noise—clock tolerance/layout stack-up or input-network tolerance?
Likely cause: clock source phase-noise/jitter variation, PCB stack-up/return differences, or passive tolerances in the input network.
Quick check: lock the same decimation profile and compare (1) clock swap A/B and (2) measured input RC values; correlate lot differences to one knob.
Fix: tighten clock specification and layout constraints, and define input-network tolerances that preserve bandwidth and spike handling.
Pass criteria: lot-to-lot in-band noise variation ≤ X% under the same fixture and settings; measured RC within Y%; clock jitter/health meets ≤ N (defined metric).
Distortion appears only at high current—front-end saturation or shunt self-heating/thermal drift?
Likely cause: input network or modulator input saturates under large signal/spikes, or shunt self-heating shifts resistance and causes nonlinear error.
Quick check: compare distortion vs current with controlled pulse duration (thermal vs instantaneous); monitor shunt temperature rise and check for clipping signatures.
Fix: ensure front-end headroom and spike control, and model shunt heating with a validation plan (pulse vs steady-state) plus calibration if needed.
Pass criteria: distortion metric (e.g., THD or max deviation) ≤ X at Y A; shunt ΔT ≤ N °C (defined airflow); no clipping/rail events in logs.
It looks like quantization noise, but it’s actually periodic ripple—idle tone/limit cycle or aliased switching ripple?
Likely cause: deterministic idle tones/limit cycles in ΔΣ behavior or switching ripple leaking through and aliasing into band.
Quick check: view the decimated spectrum for narrow spurs; A/B change fsw slightly or apply dither/notch and observe spur movement and amplitude change.
Fix: mitigate tones (dither/seed) and strengthen stopband/notch to reject switching components that can alias into band.
Pass criteria: largest in-band spur ≤ X dBc; spur reduces by ≥ Y dB after mitigation; residual ripple ≤ N (RMS or pk-pk, defined band).

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