High-CMTI / High-dv/dt Isolated Gate Drivers (100–200 kV/µs)

Q: CMTI rated 150 kV/µs, but false turn-on still happens—suspect Cbarrier or gate loop first?

Likely cause: Gate loop / Kelvin return and the closure path are converting injected current into Vgs bump; Cbarrier alone rarely explains “system-only” false turn-on. Quick check: Measure Vgs referenced to Kelvin return (TP1↔TP2) and align with SW node edges (TP3); confirm whether Vgs bump timing matches dv/dt transitions and whether TP2 bounce is large. Fix: Tighten gate loop and Kelvin routing first; then add/verify Miller clamp return reference and strengthen turn-off path (Rgoff + controlled damping) before changing barrier assumptions. Pass criteria: False turn-on count = 0 over Y minutes / N switching events; off-state Vgs bump < X V margin under worst dv/dt and temperature corner.

Q: A stronger Miller clamp made EMI worse—check clamp return path or Rg split first?

Likely cause: Clamp return reference is noisy (wrong ground/return), turning clamp action into extra HF current loops; or Rgon/Rgoff split is pushing more HF content into the wrong edge. Quick check: Compare clamp node activity vs TP2 Kelvin return bounce; if EMI worsens when clamp engages, the clamp return is likely injecting HF current into a larger loop. Fix: Re-anchor clamp return to the intended quiet Kelvin reference; then refine Rgon/Rgoff split and add HF damping (bead / local snubber) instead of globally increasing Rg. Pass criteria: EMI margin improves by X dB with no increase in false pulses (0 over N events) and no thermal penalty beyond X °C rise over Y minutes.

Q: DESAT keeps reporting short-circuit but the device is not heating—blanking too short or dv/dt is corrupting the sense loop?

Likely cause: dv/dt is pulling the DESAT sense reference or node, creating false Vce/Vds events; or blanking window is too short for the switching transient. Quick check: Time-align TP4 (fault/DESAT) to TP3 (SW node) and gate waveform; if faults cluster at turn-on/turn-off edges and disappear when dv/dt is reduced, it is likely a mis-trip. Fix: Stabilize DESAT sense reference/return and reduce dv/dt coupling first; then extend blanking to cover the transient while re-validating short-circuit protection response time. Pass criteria: Mis-trip count = 0 over Y minutes at worst dv/dt; short-circuit response still meets X µs maximum detection/turn-off window.

Q: Same board is fine at room temp, but false triggers increase at high temp—UVLO chatter or threshold drift?

Likely cause: UVLO threshold/hysteresis behavior at temperature corners causes supply-edge chatter; leakage and reference drift increase susceptibility to dv/dt injection. Quick check: Run a temperature sweep while logging TP4 faults and rail stability; correlate mis-trips with undervoltage events or ripple bursts on the secondary supply. Fix: Increase UVLO stability (hysteresis/hold-off policy if configurable), improve secondary rail decoupling and return integrity, and re-check clamp reference under temperature. Pass criteria: Mis-trips = 0 across temperature range for Y minutes; UVLO transitions are clean and Vgs bump < X V under worst dv/dt.

Q: Long PWM input wiring causes occasional missing pulses—input filtering/thresholds or isolation-side ground bounce?

Likely cause: Input threshold/glitch filtering is being crossed by ground bounce; or long-line ringing is creating extra transitions that are filtered/clipped inconsistently. Quick check: Correlate missing pulses with TP5 (primary ground bounce) and the input edge timing; verify whether the input level crosses the threshold during bounce windows. Fix: Improve primary-side reference stability and input return; add controlled edge conditioning at the source rather than aggressive filtering that distorts duty timing. Pass criteria: Missing edge count = 0 over N input pulses at worst-case wiring; PWM duty error < X% over Y minutes.

Q: Negative turn-off bias removed false triggers but efficiency dropped—optimize Rgoff first or reduce negative bias amplitude?

Likely cause: Larger gate swing increases driver loss and may force harder transitions; the original root cause may be a weak turn-off path and closure loop, not insufficient margin. Quick check: Compare drive power before/after -Vg and check whether Vgs bump margin is met without the full negative amplitude. Fix: Strengthen turn-off path (Rgoff + clamp reference + HF damping) and tighten Kelvin loop; then reduce -Vg to the minimum that preserves margin. Pass criteria: False turn-on = 0 over N events while drive loss stays below X W and temperature rise < X °C over Y minutes.

Q: Double-pulse test passes, but the full system still false-triggers—system common-mode loop or measurement reference error?

Likely cause: System-level closure path changes are re-routing injected current; or measurement reference is wrong, creating a false Vgs bump narrative. Quick check: Re-measure with strict Kelvin reference and log TP5 bounce; compare bench vs installed conditions with the same trigger definition and bandwidth. Fix: Control the closure path (return/partition) and re-validate with the TP map under real installation; avoid solving only by slowing edges unless thermal limits allow. Pass criteria: False turn-on = 0 in the installed system over Y minutes; Vgs bump differs by < X V across setups.

Q: Only one phase is problematic—layout asymmetry or different power-loop parasitics?

Likely cause: Asymmetric Kelvin return / clamp reference routing or phase-to-phase parasitic coupling changes injected current magnitude and closure impedance. Quick check: Capture identical TP1/TP2/TP3 waveforms for all phases using the same probe method; compare Vgs bump and TP2 bounce. Fix: Symmetrize gate loop and return geometry; standardize damping placement; re-check partition boundaries around the isolation slot per phase. Pass criteria: Phase-to-phase delta in Vgs bump < X V and mis-trips = 0 across all phases over N cycles / Y minutes.

Q: Fault recovers then immediately re-triggers—auto-retry too aggressive or latch/clear policy wrong?

Likely cause: Retry occurs before rails/thermal/loop return to stability; or clear policy releases faults into the same dv/dt corner condition. Quick check: Log fault timing vs UVLO events and switching edges; confirm whether retrigger happens within a consistent short window after re-enable. Fix: Add controlled hold-off after clear and require stable rails before re-enable; re-validate blanking/threshold behavior during recovery transitions. Pass criteria: No re-trigger within X ms hold-off and mis-trips = 0 over N recovery cycles.

Q: Slowing switching removes false triggers but temperature rises—add clamp or rebuild Kelvin loop first?

Likely cause: Slower edges reduce injection spectral energy but increase switching loss; root cause is typically off-state margin and closure loop control. Quick check: Compare Vgs bump and TP2 bounce before/after slowing edges; verify whether clamp/turn-off strengthening would meet margin without large thermal penalty. Fix: Prioritize Kelvin loop integrity and clamp return reference; then apply targeted HF damping. Use edge slowing only as a last step within thermal limits. Pass criteria: False turn-on = 0 while temperature rise < X °C and efficiency stays above X% over Y minutes.

← Back to: Digital Isolators & Isolated Power

Core idea: High-CMTI isolated gate drivers succeed by controlling the common-mode injection loop—barrier capacitance, gate-loop/Kelvin returns, and edge shaping determine whether high dv/dt becomes false turn-on and protection mis-trips or a non-event. The engineering goal is measurable: false pulses = 0, mis-trips = 0, and Vgs bump stays below margin across worst-case dv/dt, temperature, and undervoltage corners.

H2-1 · Scope Guard & One-Sentence Takeaway

One-sentence takeaway

High-CMTI isolated gate drivers win by controlling the common-mode injection loop— layout discipline, barrier capacitance, edge shaping, and robust UVLO/blanking decide whether high dv/dt becomes false turn-on or a non-event.

CMTI: 100–200 kV/µs-class dv/dt immunity tPD / skew UVLO behavior DESAT blanking Miller clamp

Outcome: A practical failure model, the highest-leverage knobs, and a validation plan that proves dv/dt robustness in the real system (not only on paper).
Audience: SiC/GaN/IGBT power stages where switching edges inject common-mode displacement current across the isolation barrier.

Figure 1 — Scope map. This page focuses on the common-mode injection loop and gate-loop robustness under fast switching edges. Bridge control strategies, isolated power topologies, and safety standards are referenced only as link-outs to avoid content overlap.

Scope guard (to prevent cross-page overlap)

In scope

CMTI and dv/dt immunity for isolated gate drivers in SiC/GaN/IGBT environments.
Common-mode injection paths and how they turn into false turn-on, latch/reset, or protection mis-trips.
Countermeasures that directly control injection and return paths: layout, barrier capacitance, edge shaping, UVLO/blanking, Miller clamp, gate-loop design.
System validation: what to measure, where to probe, and what “pass” looks like in the real assembly.

Out of scope (link-only)

Half-bridge/full-bridge control strategy details → Dual / Half-Bridge Isolated Driver
Isolated bias and DC-DC topology deep dive → Isolated Power (DC-DC & Bias)
Standards, VIORM/creepage clause-by-clause → Safety & Compliance

H2-2 · Problem Model: Why High dv/dt Breaks Drivers

What breaks first under fast edges

High dv/dt does not “mysteriously” break isolation. It drives displacement current through parasitic capacitances. The system fails when that injected current finds a return path that crosses sensitive thresholds or state machines.

Core mechanism: injected current magnitude scales as i_inj = C · dv/dt. Lower coupling capacitance helps, but return-path impedance and reference shifts often dominate real failures.
Practical goal: force injected current to close in a harmless loop; prevent it from flowing through logic inputs, UVLO comparators, or gate-drive control paths.

Figure 2 — Three injection paths. dv/dt produces displacement current through parasitic capacitances. Failures happen when injected current closes through sensitive references: primary ground bounce (A), off-state gate bump (B), or I/O reference drift (C).

Failure symptoms mapped to injection paths (field-first view)

The fastest way to debug dv/dt issues is to treat each symptom as evidence of an injection path and its return-loop closure. Use the checklist below as an entry point before changing components.

Symptom: sporadic false turn-on / shoot-through
Likely path: Path B (Miller injection into gate loop)
First check: measure off-state Vgs bump at the device using Kelvin return reference
Evidence: Vgs peak and duration exceed the effective turn-on threshold during SW transitions
Symptom: driver latch/reset or unexpected output disable
Likely path: Path A or C (primary ground bounce or reference drift)
First check: correlate UVLO/fault pin timing with SW node transitions and supply dips
Evidence: fault/UVLO events align with dv/dt edges rather than load transients
Symptom: DESAT/short-circuit trips with no thermal evidence
Likely path: Path A (injection into sense/return) + protection timing sensitivity
First check: review DESAT blanking vs switching edge timing; probe DESAT pin with proper reference
Evidence: trip occurs inside blanking window or matches dv/dt edge, not current rise
Symptom: PWM edges missing / dead-time corruption / logic glitches
Likely path: Path C (I/O reference drift crosses thresholds)
First check: validate input thresholds, hysteresis, and input filtering; check ground reference integrity
Evidence: glitches present at logic input receiver but absent at upstream controller pin

Working definitions (used consistently across this page)

dv/dt: the switch-node edge rate seen by parasitic coupling paths (system-level, layout-dependent).
CMTI: immunity to common-mode transients without producing erroneous output states; datasheet values depend strongly on test setup and thresholds.
false turn-on: unintended device conduction triggered by off-state gate voltage bump that crosses the effective threshold under switching transients.

H2-3 · Key Specs That Actually Matter (Not Marketing)

Spec-to-failure map (use this before reading datasheets)

Spec values only matter if they block a specific failure mode. The quickest selection workflow is to map each spec to the injection path it protects: Path A (primary ground bounce), Path B (Miller gate bump), and Path C (I/O reference drift).

Path A → CMTI conditions + Cbarrier + UVLO/default Path B → Miller clamp + output pull-down + skew Path C → input thresholds + hysteresis + glitch filter

Figure 3 — Dimensional view. The injected current magnitude scales with C_barrier and dv/dt. System failure is defined by where this current closes and what references it disturbs.

Spec cards (each spec becomes a decision gate)

Each specification below is written as an executable gate: what it means, why it matters, how to verify, and the typical pitfall. Placeholder thresholds (X/Y/N) are intentionally left as project-specific knobs.

CMTI (kV/µs)

What: immunity to a common-mode transient without creating an erroneous state; meaning depends on test setup (Vcm step, output state, supplies, temperature).
Why: protects against Path A and Path C failures (ground bounce and reference drift that cross thresholds).
How to verify: correlate fault/UVLO/output glitches with switch-node edges under worst-case supply margin and temperature; confirm “no wrong state” within window X.
Typical pitfall: comparing CMTI numbers across vendors without matching conditions; ignoring the most fragile case (near-UVLO or high temperature).

Gate: no wrong state Check: edge correlation Worst-case: near UVLO

Barrier capacitance (pF)

What: effective coupling capacitance across the isolation barrier that multiplies dv/dt into displacement current.
Why: sets the injection current upper bound and impacts EMI and false triggering sensitivity (Path A dominated systems).
How to verify: estimate i_inj budget using measured dv/dt; validate by observing primary-ground bounce and fault timing under worst-case switching edges.
Typical pitfall: assuming “lower is always better” while the return path still closes through sensitive references; ignoring chassis capacitance in the system.

Budget: i = C·dv/dt Watch: GND bounce System: chassis C matters

Input threshold / hysteresis / glitch filter

What: input receiver behavior that defines when a disturbed reference becomes a logic transition and whether short glitches are rejected.
Why: primary protection for Path C (I/O reference drift and threshold crossings during dv/dt events).
How to verify: inject worst-case common-mode transient while monitoring input and internal output edges; confirm no extra transitions within window X and no missed valid pulses.
Typical pitfall: over-filtering that eats real PWM edges or shifts effective dead-time; underestimating reference drift at the receiver.

Gate: no extra edges Tradeoff: latency Path C critical

Propagation delay / skew

What: timing from input transition to output transition; skew is channel mismatch across outputs and across temperature/supply drift.
Why: high-frequency PWM and multi-channel synchronization can amplify small mismatches into shoot-through risk or protection timing gaps (Path B interaction).
How to verify: measure tPD/skew across voltage and temperature corners; ensure timing budget margin ≥ X and mismatch ≤ Y over the intended operating range.
Typical pitfall: using typical numbers only; ignoring drift with supply droop and temperature that occurs during real switching stress.

Budget: margin ≥ X Skew: ≤ Y Corner: V/T drift

UVLO behavior & default states

What: under-voltage lockout thresholds, hysteresis, and the output’s defined safe state during power-down or brownout.
Why: dv/dt-induced supply bounce can enter UVLO; safe defaults prevent unintended pulses or half-enabled states (Path A + state-machine robustness).
How to verify: perform brownout and fast supply dip tests synchronized with dv/dt edges; confirm outputs go to the defined safe state within X and recover predictably.
Typical pitfall: UVLO thresholds too close to nominal rails; auto-retry behavior that creates repeated stress during switching transients.

Gate: safe state in UVLO Check: dip + dv/dt Risk: retry storms

Output drive strength & Miller clamp

What: pull-up/pull-down capability and clamp behavior that fights off-state gate bump caused by Cgd under dv/dt.
Why: primary mitigation for Path B; clamp + Rgon/Rgoff must match device Qg/Cgd and the gate-loop parasitics.
How to verify: measure off-state Vgs bump at the device with Kelvin reference; confirm peak/duration stays below an effective threshold across worst-case dv/dt.
Typical pitfall: assuming stronger drive always improves robustness while it can worsen ringing/EMI; clamp return path or placement undermines effectiveness.

Path B critical Measure: Vgs bump Placement matters

H2-4 · Injection Physics: The Common-Mode Current Loop You Must Control

Minimal model: displacement current + loop closure

dv/dt produces displacement current through parasitic capacitors. The system fails when this current closes through a loop that disturbs a sensitive reference: an input receiver threshold, UVLO comparator, fault logic, or the off-state gate loop.

Where it comes from: the switch node edge is the source; fast edges raise i_inj even when the average current is small.
Where it couples: C_barrier (across isolation), C_{sw-to-chassis} (to chassis/earth), C_gd (Miller), and mutual inductance in the gate loop.
Why “ground is not 0 V”: return-path impedance creates ground bounce and common-mode lift; the same logic threshold can be crossed without any “real signal” change.

Figure 4 — Minimal loop model. Injection current is unavoidable; the engineering objective is to control the closure point and minimize Z_return impact on references so dv/dt does not become a state change.

Loop check checklist (turn physics into actions)

The loop can be debugged like a circuit. Answer the questions below in order; each answer produces the next measurement target.

Injection source? What is the real switch-node dv/dt at the board level (measured at the right reference point)?
Coupling capacitor? Which term dominates: C_barrier, C_{sw-to-chassis}, or C_gd (Miller)?
Return path? Through which conductors does i_inj close—quiet ground, power return, chassis, or signal ground?
Reference point? Are measurements referenced correctly (Kelvin return, differential probe) to avoid “ghost” ground bounce artifacts?
Bandwidth? Which path dominates at high frequency (decoupling placement, loop inductance, and input filter bandwidth)?

Practical pass criteria (placeholders)

No wrong state: zero extra output edges during dv/dt events over Y minutes and N cycles.
No false turn-on: off-state Vgs bump stays below an effective threshold by margin X under worst-case dv/dt.
No protection mis-trip: DESAT/SC does not trigger inside blanking window except under forced fault conditions.

H2-5 · False Turn-On: Miller, dV/dt, and Gate Loop Countermeasures

Mechanism: dv/dt turns into gate current through Cgd (Miller)

False turn-on is driven by an injected Miller current that flows through Cgd during fast switch-node transitions. The hazard is defined by two observables: off-state Vgs bump (peak + duration) and where the current closes (return-path reference).

Injection: dv/dt at the switch node pushes current through Cgd into the gate network.
Conversion: gate-loop impedance converts injected current into a Vgs bump; a “small” bump can still be fatal if it lasts long enough.
Measurement rule: Vgs bump must be measured with a Kelvin source/emitter reference; an incorrect ground reference often fabricates or hides the real bump.

Figure 5 — Gate loop + clamp placement. A clamp is only as effective as its return reference. Device-side placement can suppress the off-state Vgs bump more directly, but it demands a disciplined Kelvin return and compact gate loop.

Countermeasure playbook (no tables; card list for mobile)

Choose countermeasures by matching a field symptom to the variable being controlled: gate-loop impedance, off-state margin, return reference, and clamp bandwidth.

Gate-source bleed (Rgs)

Benefit: provides a defined discharge path for injected current; reduces floating-gate sensitivity.

Cost: increases driver losses and can slow transitions if too aggressive.

When to choose: long gate traces, high-impedance drive, or intermittent bump on off-state gate.

Field symptom: sporadic false turn-on that correlates with dv/dt edges, especially with cable/fixture changes.

Primary knob: leakage path Best for: mild bumps Risk: extra loss

Split Rg (Rgon / Rgoff + diode)

Benefit: independently shapes turn-on/turn-off edges to balance EMI vs false turn-on immunity.

Cost: extra parts and layout sensitivity; diode parasitics can undermine the intended separation.

When to choose: ringing/overshoot is present, but stronger pull-down is still required during dv/dt events.

Field symptom: failures depend on edge polarity (only turn-off edges cause issues) or vary with temperature.

Primary knob: edge asymmetry Best for: EMI trade Risk: diode loop

Kelvin source/emitter return

Benefit: isolates the gate-drive reference from power-current return, preventing “fake Vgs” caused by ground bounce.

Cost: stricter layout constraints; wrong routing can re-couple the Kelvin path into the noisy return.

When to choose: the same schematic behaves differently across layouts or phases; Vgs measurement depends on probe ground choice.

Field symptom: false turn-on appears only on one leg/one board spin; scope readings are inconsistent.

Primary knob: reference integrity Best for: layout-sensitive Risk: routing mistakes

Miller clamp

Benefit: actively pulls the gate toward the source/emitter during off-state dv/dt events; blocks Cgd injection from building Vgs.

Cost: requires correct placement and return reference; effectiveness depends on clamp threshold and bandwidth.

When to choose: high dv/dt with low Vth devices, high Cgd, or when Rgoff/Rgs alone cannot suppress Vgs bump.

Field symptom: shoot-through during fast edges; failures improve with slower edges but return under performance settings.

Primary knob: clamp bandwidth Best for: fast dv/dt Risk: bad reference

Negative gate bias

Benefit: increases off-state margin against dv/dt-induced Vgs bumps; can stabilize the most aggressive switching corners.

Cost: higher EMI risk (larger Vgs swing), higher drive losses, and more complex isolated bias/UVLO considerations.

When to choose: clamp + layout discipline still leaves insufficient off-state margin; high temperature or device spread reduces Vth margin.

Field symptom: rare but catastrophic shoot-through that survives typical Rg tuning; strongly correlated with worst dv/dt corners.

Primary knob: Vgs margin Best for: hard corners Risk: EMI + complexity

H2-6 · Output Stage Robustness: UVLO, Blanking, DESAT/SC in High dv/dt

Protection must stay correct under dv/dt (mis-trips are dangerous)

In high dv/dt environments, protection circuits can be triggered by injected transients rather than real faults. Robust protection requires: stable UVLO behavior, blanking windows that match switching physics, and explicit safe output states.

UVLO: threshold + hysteresis decide whether supply bounce becomes repeated resets; recovery policy (latched vs auto-retry) defines field behavior.
DESAT/SC blanking: too short causes mis-trips; too long risks device overstress; tuning must be evidence-driven.
Soft turn-off: a controlled shut-down limits overshoot and avoids turning a fault into a higher dv/dt injection event.
Default state: power-down, brownout, or input floating must force a defined safe output state.

Figure 6 — DESAT blanking. The blanking window must cover legitimate turn-on transients while remaining short enough to protect the device under real short-circuit events.

Protection strategy decision tree (symptom → evidence → first action)

The first step is not “change the IC.” The first step is to decide whether the event is a mis-trip driven by dv/dt injection or a real fault. The branches below are written to produce evidence quickly.

Branch A — UVLO behavior under dv/dt

Symptom: output disables or resets that align with switch-node edges.
Mis-trip evidence: UVLO/fault timing correlates with dv/dt edges; supply dip is brief and repeats with edge rate changes.
Real-fault evidence: sustained supply droop driven by load or thermal conditions; correlation to dv/dt is weak.
First action: verify hysteresis margin and default safe state; compare latched vs auto-retry behavior under the same dv/dt profile.

Branch B — DESAT blanking (mis-trip vs real short-circuit)

Symptom: DESAT trips only during switching edges or during EMI stress tests.
Mis-trip evidence: DESAT pin/comparator crosses threshold inside the blanking window or with narrow spikes aligned to dv/dt.
Real-fault evidence: DESAT stays high beyond blanking; Vds/Vce indicates sustained abnormal conduction consistent with fault current.
First action: tune blanking with an evidence-driven flow: cover legitimate turn-on transient + noise margin, then verify worst-case SC response time remains within project limits.

Branch C — Soft turn-off under fault

Symptom: trips are followed by voltage overshoot or secondary glitches that create more dv/dt injection events.
Mis-trip evidence: overshoot and glitches disappear when dv/dt is reduced or clamp/return is improved.
Real-fault evidence: overshoot persists and is repeatable under forced-fault conditions.
First action: enforce a defined soft turn-off behavior and confirm output default state during brownout/input floating; avoid uncontrolled auto-retry storms.

Explicit safe-state requirements (placeholders)

Power-down / UVLO: output forced to a defined safe state within X and remains stable (no pulses) for Y.
Input floating: output default is deterministic (no metastable toggling) across temperature and supply corners.
Fault recovery: latched vs auto-retry policy is documented and testable; no retry storms during dv/dt stress.

H2-7 · Isolation Barrier Choices That Affect dv/dt Immunity

Selection boundary (dv/dt-only, no barrier “encyclopedia”)

This section focuses only on dv/dt immunity drivers: coupling multiplier (effective C_barrier), loop closure (where i_inj returns), and multi-channel consistency. Detailed barrier principles belong to the Device Classes pages.

Factor 1: Cbarrier Factor 2: return loop Factor 3: channel match

Figure 7 — dv/dt-only comparison. Different barrier implementations can present different effective coupling and different closure paths for injected current. The stable choice is the one that keeps the return loop away from sensitive references.

Decision cards (reasons only; avoid cross-page deep dives)

Capacitive vs magnetic/inductive (dv/dt sensitivity)

Decision factor: effective coupling (C_barrier) and where high-frequency common-mode current prefers to flow.

Why dv/dt cares: injected current scales with dv/dt and closes through a return path that can shift references (Path A/C behaviors).

What to verify: correlate misbehavior with switch-node edges and confirm whether ground/reference shift is the primary trigger.

Typical pitfall: selecting by “barrier type reputation” without budgeting the closure path (chassis coupling and layout dominate).

Knob: coupling Knob: closure Risk: reference shift

Integrated isolated driver vs discrete isolator + driver

Decision factor: controllability versus predictability under dv/dt stress.

Why dv/dt cares: integrated paths can be shorter and more matched, while discrete chains offer more external tuning knobs for edge shaping and filtering.

What to verify: confirm whether the system needs extra tuning knobs (Rgon/Rgoff/clamp behavior/threshold filtering) beyond what integration provides.

Typical pitfall: assuming integration automatically solves return-path issues; layout can negate the integration advantage.

Trade: knobs vs predictability Watch: return path Avoid: hidden coupling

Multi-channel consistency (match = stability multiplier)

Decision factor: channel-to-channel match in thresholds, filtering, and timing under voltage/temperature drift.

Why dv/dt cares: the first channel that flips becomes the system-level failure trigger (interlocks, faults, and skew cascades).

What to verify: skew/threshold drift across channels under worst dv/dt, supply margin, and temperature.

Typical pitfall: validating only one “golden channel” while the weakest channel dictates field reliability.

Knob: match Gate: worst channel Risk: cascades

What to pick when… (fast rationale)

Extreme dv/dt corners: prioritize controlled closure + strong channel consistency over “headline” CMTI alone.
Layout variability across phases/boards: prefer solutions that remain stable under small return-path deviations (match + robust thresholds).
Need for field tuning: favor architectures that allow explicit edge shaping, clamp strategy, and threshold/filter tuning without destabilizing timing budgets.
Multi-channel safety: choose the option that keeps the weakest channel within margin, not the typical channel.

H2-8 · Layout & Partition: Primary/Secondary, Gate Loop, Return Paths

Hard rules (layout decides dv/dt reality)

dv/dt immunity is frequently dominated by partition discipline, gate-loop area, and return-path control. The rules below are written as reviewable constraints, not generic advice.

Rule A — partition: keep primary/secondary copper and return paths separated; no accidental “bridge” across the isolation slot/keep-out.
Rule B — gate loop: driver → Rg → gate → Kelvin return must be the shortest and tightest loop on the secondary side.
Rule C — placement priority: HF decoupling first, then clamp/Rgoff network, then turn-on shaping (Rgon), while preserving clean references.
Rule D — reference strategy: maintain a secondary quiet ground distinct from power return so dv/dt current cannot shift logic thresholds.

Figure 8 — Placement blueprint. The isolation slot blocks accidental closure across domains. The gate loop is kept compact and referenced by a Kelvin return, while decoupling is layered by frequency close to the driver to minimize return-path impedance at dv/dt edges.

Layout checklist cards (Bring-up vs Production)

This checklist is structured for execution: bring-up items prioritize fast evidence, while production items prioritize repeatable acceptance criteria and documentation.

Bring-up checklist (fast evidence)

Reference sanity: verify Kelvin measurement reference for Vgs bump and driver return; avoid probe-ground artifacts.
Edge correlation: align faults/glitches with switch-node edges; confirm sensitivity to edge rate changes.
Return-path audit: sketch the i_inj closure loop; confirm no unintended crossing near the isolation slot.
Gate loop area: visually confirm driver→Rg→gate→Kelvin is the smallest loop on the secondary domain.
Decoupling reality: confirm HF decap loop is minimal and not routed through noisy return copper.

Goal: prove closure Tool: timing correlation Avoid: fake Vgs

Production checklist (repeatable gates)

Partition gate: no copper/return crossing across keep-out; review with a dedicated “return-path” checklist.
Placement gate: HF decap closest to driver supply pins; clamp/Rgoff network placed to preserve the intended return reference.
Loop gate: gate loop remains within a controlled footprint; Kelvin return is not merged into power return anywhere.
Acceptance criteria: no false pulses under dv/dt stress for Y minutes over N cycles (placeholder); document test points and probe reference.
Documentation: capture layout screenshots, stack-up notes, and test setup photos to prevent “lab-to-lab” mismatches.

Gate: no crossing Gate: loop integrity Gate: repeatability

H2-9 · EMI & Edge Shaping Without Killing Switching Performance

Why “just increase Rg” often backfires

Slower edges can reduce high-frequency spectral energy, but they also extend switching transition time, raising switching loss and temperature. Stable dv/dt systems use controlled knobs that shape edge rate and ringing without sacrificing off-state margin or protection correctness.

dv/dt & di/dt: faster edges increase EMI energy; slower edges increase E_sw and heat.
Ringing/overshoot: often needs damping, not just “slower.”
False turn-on risk: edge shaping changes Miller injection and can move problems between EMI and shoot-through.

Figure 9 — Gate-side knobs. Use separate knobs for edge rate, damping, and off-state margin. A single knob (only Rg) often trades EMI for heat without controlling ringing or false turn-on risk.

Knob matrix (structured for execution; no tables)

Rgon / Rgoff (split control)

Effect on dv/dt: primary control for turn-on/turn-off edge rate.

Effect on overshoot: can reduce excitation, but may not remove ringing without damping.

Effect on losses: larger values usually increase switching loss and temperature.

Risk: excessive Rgoff can worsen off-state immunity; excessive Rgon can cause thermal runaway in high-frequency operation.

Best for: edge budget Watch: heat Watch: Vgs bump

Gate ferrite bead (HF damping)

Effect on dv/dt: modest; mainly shapes very-high-frequency content.

Effect on overshoot: effective against high-frequency ringing by adding frequency-selective loss.

Effect on losses: typically smaller than brute-force Rg increases.

Risk: poor placement or unintended loop area reduces effectiveness; non-linear impedance can create corner-case behaviors.

Best for: HF ringing Watch: placement Watch: repeatability

Local snubber (gate-side / local only)

Effect on dv/dt: can reduce effective dv/dt by damping the resonant response.

Effect on overshoot: direct knob to reduce overshoot and ringing amplitude.

Effect on losses: adds dissipative loss; typically targeted to ringing energy rather than full switching energy.

Risk: wrong placement turns it into an antenna; over-damping can degrade dynamic performance without fully solving the root closure path.

Best for: overshoot Watch: antenna loops Scope: local only

Miller clamp & -Vg (off-state margin)

Effect on dv/dt: indirect; prevents dv/dt injection from converting into Vgs turn-on.

Effect on overshoot: not a primary overshoot knob; works by controlling gate reference and off-state behavior.

Effect on losses: -Vg increases gate swing and drive loss; clamp adds requirements on reference and bandwidth.

Risk: poor return reference undermines clamp; -Vg can worsen EMI if it forces harder transitions.

Best for: false turn-on Watch: reference Watch: EMI trade

Coupling (Cbarrier + closure path)

Effect on dv/dt: lower coupling can reduce injected current, but the return path can re-route through other parasitics.

Effect on overshoot: can shift where common-mode energy flows, changing ringing sensitivity by frequency band.

Effect on losses: typically not a direct loss knob, but can force edge shaping choices that change losses.

Risk: assuming “smaller Cbarrier solves everything” while the closure path moves to chassis coupling or layout bridges.

Best for: system view Watch: closure Avoid: single-metric

Practical tuning order (stable workflow)

Step 1: lock the return reference (Kelvin) and confirm the closure path is controlled.
Step 2: set Rgoff for off-state immunity first; validate false turn-on margin under worst dv/dt.
Step 3: add HF damping (bead / local snubber) to reduce ringing without large heat penalty.
Step 4: tune Rgon for EMI and efficiency balance; re-validate protection behavior and temperature.

H2-10 · Validation: How to Prove High-CMTI in Your System (Not Just Datasheet)

Validation goals (system-level, evidence-driven)

High-CMTI is proven when the system shows no false turn-on, no pulse loss/glitch, and no protection mis-trips under worst-case dv/dt and operating corners. This section defines a repeatable plan with explicit measurement points and pass criteria placeholders.

Goal: no false pulses Goal: no missing edges Goal: no mis-trips

Figure 10 — TP map. A repeatable validation depends on measuring the correct references. Gate waveforms must be Kelvin-referenced, and fault/DESAT timing must be aligned to SW node transitions.

Validation plan cards (Plan / Setup / Measure / Pass)

Plan

Objective: prove no false turn-on, no missing edges, and no protection mis-trips under worst dv/dt.
Scope: include temperature corners, undervoltage corners, and long PWM input lines where relevant.
Stress ranking: start with dv/dt step injection, then verify under double-pulse switching stress.

Target: 0 mis-trips Target: 0 false pulses

Setup

Stimulus: dv/dt step (SW node-like transition) and double-pulse switching condition.
Corners: high temp / low temp, supply undervoltage, and input timing worst case.
References: enforce Kelvin measurement reference for TP1/TP2 to avoid fabricated Vgs bumps.

Gate: Kelvin ref Gate: repeatable

Measure

Core waveforms: TP1 gate, TP2 Kelvin return, TP3 SW node.
Protection evidence: TP4 fault/DESAT pin timing aligned to edges.
Reference integrity: TP5 primary ground bounce relative to the intended quiet reference.

Measure: gate bump Measure: fault timing Measure: bounce

Pass (threshold placeholders)

False turn-on: count = 0 within Y minutes / N cycles (placeholder).
Missing edge / glitch: count = 0 within Y minutes under dv/dt stress (placeholder).
Protection mis-trips: fault misreport = 0 within defined window (placeholder).
Gate integrity: Vgs overshoot < X V and off-state bump stays below margin (placeholder).

Pass: 0 events Pass: Vgs < X Pass: repeatable

H2-11 · Quick Pairings (Just Enough to Route to Other Pages)

Pairing templates (module-level, link out for details)

These pairings provide just enough module guidance to route to related pages. Each card includes example part numbers for fast BOM seeding. Detailed half-bridge control strategy, isolated power topology design, and safety standard clauses are handled on their dedicated pages.

Figure 11 — Pairing puzzle. The purpose is routing: assemble modules at a block level, then follow links for deep design details.

Pairing card A — SiC half-bridge (high dv/dt, short-circuit risk)

Use case

SiC inverter leg / half-bridge where switching-node dv/dt stresses the isolation barrier and gate loop.

Why this driver type

High dv/dt immunity: prevents common-mode injected current from turning into false pulses or missing edges.
Off-state control: clamp and robust turn-off path reduce Vgs bump driven by Miller injection.
Protection correctness: DESAT blanking must avoid dv/dt-triggered mis-trips while still protecting the switch.

What to watch

Gate loop + Kelvin return: smallest loop area on the secondary side; no return crossing near the isolation slot.
Miller clamp placement: clamp reference must be the intended quiet return, not power return.
Blanking initialization: start conservative, then validate under double-pulse stress with TP map.
Edge shaping: use damping knobs before brute-force Rg increases to avoid thermal penalty.

Example BOM seed (part numbers)

Isolated gate driver (SiC-class examples): TI UCC21750 / UCC21710, ADI ADuM4135, Infineon 1EDC20I12AH.
Isolated bias (link out for topology): TI SN6505B (transformer driver), RECOM RxxP2xx series (isolated DC-DC module).
DESAT diode (typical): ON Semi 1N4148 (fast small-signal) or equivalent; choose by speed/leakage/temperature.
Gate resistor (split values): Vishay CRCW series / Yageo RC series (thick film); size by pulse rating.
Gate bead (HF damping): Murata BLM18 series (select impedance band to target ringing).

Isolated Bias / Power Dual / Half-Bridge Driver Safety & Compliance

Pairing card B — GaN high-speed (parasitics dominate)

Use case

GaN stages where ultra-fast edges make layout parasitics and high-frequency ringing the dominant failure triggers.

Why this driver type

Short-loop stability: dv/dt immunity must survive with minimal loop inductance and tight references.
Clamp-first strategy: off-state margin protects against gate bump and false turn-on.
HF damping knobs: bead/local damping controls ringing without forcing large switching-loss penalties.

What to watch

Measurement integrity: Kelvin reference is mandatory; probe-ground artifacts commonly mimic Vgs bumps.
Rgoff dominance: turn-off path often determines false turn-on stability more than turn-on shaping.
HF ringing band: target damping to the ringing frequency band rather than globally slowing edges.

Example BOM seed (part numbers)

Isolated driver (fast-edge capable examples): TI UCC21750, ADI ADuM4135, Silicon Labs Si828x family (choose by timing/protection needs).
Gate bead: Murata BLM18 / BLM21 series (select impedance vs frequency).
Local RC damping (component families): Vishay CRCW resistors + C0G/NP0 capacitors (Murata GRM C0G series).

Dual / Half-Bridge Driver Digital Isolator Device Classes

Pairing card C — IGBT industrial (protection + temperature + repeatability)

Use case

Industrial IGBT drives requiring robust DESAT/soft turn-off behavior and stable operation across temperature and supply corners.

Why this driver type

Protection correctness under dv/dt: fault logic and DESAT sensing must avoid dv/dt-induced false trips.
Soft turn-off behavior: reduces stress during short-circuit events and prevents overvoltage spikes.
Wide-temperature stability: thresholds and timing must remain consistent across the application range.

What to watch

Blanking window: too short triggers mis-trips; too long increases short-circuit energy.
Production repeatability: layout version control and component tolerance lock are mandatory.
Corner validation: verify at temperature extremes and undervoltage to prevent UVLO-induced glitches.

Example BOM seed (part numbers)

Isolated driver (IGBT-oriented examples): Infineon 1EDC20I12AH, TI UCC21750, Broadcom/Avago ACPL-337J (opto-replacement style).
DESAT diode: ON Semi 1N4148 or ultrafast diode family as required by temperature/leakage constraints.
Gate resistor (pulse-rated): Vishay CRCW series (choose size/power for pulse energy).

Safety & Compliance Isolated Power (DC-DC & Bias)

H2-12 · Engineering Checklist (Design → Bring-up → Production)

Checklist goal (execution + evidence)

This section compresses the entire page into an executable checklist with evidence gates. Use it as a review template for design, bring-up, and production readiness.

Figure 12 — Readiness gates. Treat each gate as a deliverable checklist with evidence: thresholds, topology, validation, and production records.

Engineering checklist (accordion; no tables)

Design (spec thresholds → loop topology → defaults)

Driver selection gate: shortlist parts by CMTI class + UVLO behavior + clamp availability (examples: TI UCC21750, ADI ADuM4135, Infineon 1EDC20I12AH).
Isolated bias seed: decide bias method and place candidates (examples: TI SN6505B transformer driver; RECOM RxxP2xx isolated module series).
Split gate resistors: define separate Rgon/Rgoff footprints (examples: Vishay CRCW / Yageo RC series; size for pulse energy).
Miller immunity knobs: reserve clamp routing and -Vg option if required; ensure the clamp return is the intended quiet reference.
HF damping footprint: add optional gate bead (example: Murata BLM18 series) and optional local RC damping pads (C0G capacitors: Murata GRM C0G family).
DESAT blanking default: set an initial blanking window placeholder (X ns/µs) with a plan to validate by double-pulse and dv/dt step tests.
Partition gate: enforce isolation slot keep-out and prohibit any return crossing; annotate in layout rules.
Decoupling plan: place HF + MF decoupling footprints close to driver supply pins; keep the loop compact.
Test-point plan: pre-place TP pads for gate (Kelvin), Kelvin return, SW node, fault/DESAT, and primary ground reference.

Bring-up (measure → correlate → tune)

Measurement gate: always measure Vgs referenced to Kelvin return (TP1↔TP2); reject probe-ground artifacts.
Edge correlation: align any glitches or faults with SW node transitions (TP3) to confirm dv/dt coupling.
Protection evidence: capture DESAT/fault timing (TP4) aligned to switching edges; distinguish mis-trips vs real events.
Return-path audit: sketch the injected-current closure loop and confirm it does not cross the isolation slot or logic reference.
Tuning priority: stabilize off-state immunity first (Rgoff/clamp/-Vg if used), then add HF damping, then tune Rgon for EMI/efficiency.
Corner sweep: validate at temperature corners and undervoltage corners to expose UVLO-induced glitch behavior.
Repeatability: lock the measurement bandwidth/trigger definition and time window for counting “false pulses” and “mis-trips.”
Pass placeholders: false pulses = 0 within Y minutes; mis-trips = 0 within window; Vgs bump stays below margin (X V placeholder).

Production (lock → control → record)

Layout lock: freeze the partition/keep-out rules and Kelvin loop geometry; treat as controlled characteristics.
Tolerance lock: lock Rgon/Rgoff, bead, and damping parts; avoid uncontrolled substitutes (e.g., Murata BLM18 impedance bands can differ).
Assembly controls: define inspection points around the isolation slot and critical return paths (no residue/bridging near keep-out).
Functional test: include a dv/dt stress screening step when feasible; record fault counters and gate integrity evidence where applicable.
Recordkeeping: store scope setup screenshots, TP reference definitions, and pass/fail thresholds (X/Y/N placeholders) as part of the production traveler.
Field diagnostics: log UVLO/OT/SC events with a clear latch/clear policy; ensure mis-trips can be distinguished from real faults.
Traceability: tie BOM revisions (e.g., UCC21750 vs ADuM4135 driver variant) to test reports and waveform archives.

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H2-13 · FAQs (10–12) — fixed 4-line answers + JSON-LD

Intent & pass/fail definition

These FAQs close only on field troubleshooting and acceptance criteria for high dv/dt / CMTI / gate-loop / protection mis-trips. Each answer is strictly four lines: Likely cause / Quick check / Fix / Pass criteria (X/Y/N placeholders).

Metric: false pulses Metric: mis-trips Metric: Vgs bump Gate: X/Y/N

1) “CMTI rated 150 kV/µs, but false turn-on still happens—suspect Cbarrier or gate loop first?”

Likely cause: Gate loop / Kelvin return and the closure path are converting injected current into Vgs bump; Cbarrier alone rarely explains “system-only” false turn-on.

Quick check: Measure Vgs referenced to Kelvin return (TP1↔TP2) and align with SW node edges (TP3); confirm whether Vgs bump timing matches dv/dt transitions and whether TP2 bounce is large.

Fix: Tighten gate loop and Kelvin routing first; then add/verify Miller clamp return reference and strengthen turn-off path (Rgoff + controlled damping) before changing barrier assumptions.

Pass criteria: False turn-on count = 0 over Y minutes / N switching events; off-state Vgs bump < X V margin under worst dv/dt and temperature corner.

2) “A stronger Miller clamp made EMI worse—check clamp return path or Rg split first?”

Likely cause: Clamp return reference is noisy (wrong ground/return), turning clamp action into extra HF current loops; or Rgon/Rgoff split is pushing more HF content into the wrong edge.

Quick check: Compare clamp node activity vs TP2 Kelvin return bounce; if EMI worsens when clamp engages, the clamp return is likely injecting HF current into a larger loop.

Fix: Re-anchor clamp return to the intended quiet Kelvin reference; then refine Rgon/Rgoff split and add HF damping (bead / local snubber) instead of globally increasing Rg.

Pass criteria: EMI margin improves by X dB with no increase in false pulses (0 over N events) and no thermal penalty beyond X °C rise over Y minutes.

3) “DESAT keeps reporting short-circuit but the device is not heating—blanking too short or dv/dt is corrupting the sense loop?”

Likely cause: dv/dt is pulling the DESAT sense reference or node, creating false Vce/Vds events; or blanking window is too short for the switching transient.

Quick check: Time-align TP4 (fault/DESAT) to TP3 (SW node) and gate waveform; if faults cluster at turn-on/turn-off edges and disappear when dv/dt is reduced, it is likely a mis-trip.

Fix: Stabilize DESAT sense reference/return and reduce dv/dt coupling first; then extend blanking to cover the transient while re-validating short-circuit protection response time.

Pass criteria: Mis-trip count = 0 over Y minutes at worst dv/dt; short-circuit response still meets X µs maximum detection/turn-off window (placeholder).

4) “Same board is fine at room temp, but false triggers increase at high temp—UVLO chatter or threshold drift?”

Likely cause: UVLO threshold/hysteresis behavior at temperature corners causes supply-edge chatter; leakage and reference drift increase susceptibility to dv/dt injection.

Quick check: Run a temperature sweep while logging TP4 faults and rail stability; correlate mis-trips with undervoltage events or ripple bursts on the secondary supply.

Fix: Increase UVLO stability (hysteresis/hold-off policy if configurable), improve secondary rail decoupling and return integrity, and re-check clamp reference under temperature.

Pass criteria: Mis-trips = 0 across temperature range for Y minutes; UVLO transitions are clean (no repeated toggles) and Vgs bump < X V under worst dv/dt.

5) “Long PWM input wiring causes occasional missing pulses—input filtering/thresholds or isolation-side ground bounce?”

Likely cause: Input threshold/glitch filtering is being crossed by ground bounce; or long-line ringing is creating extra transitions that are filtered/clipped inconsistently.

Quick check: Correlate missing pulses with TP5 (primary ground bounce) and the input edge timing; verify whether the input level crosses the threshold during bounce windows.

Fix: Improve primary-side reference stability and input return; add controlled edge conditioning at the source (short return, controlled impedance) rather than aggressive filtering that distorts duty timing.

Pass criteria: Missing edge count = 0 over N input pulses at worst-case wiring; PWM duty error < X% over Y minutes (placeholder).

6) “Negative turn-off bias removed false triggers but efficiency dropped—optimize Rgoff first or reduce negative bias amplitude?”

Likely cause: Larger gate swing increases driver loss and may force harder transitions; the original false turn-on root cause may be a weak turn-off path and closure loop, not insufficient margin.

Quick check: Compare gate charge/drive power before/after -Vg and check whether Vgs bump margin is already met without the full negative amplitude.

Fix: Strengthen turn-off path (Rgoff + clamp reference + HF damping) and tighten Kelvin loop; then reduce -Vg amplitude to the minimum that preserves off-state margin.

Pass criteria: False turn-on = 0 over N events while drive loss stays below X W (placeholder) and temperature rise < X °C over Y minutes.

7) “Double-pulse test passes, but the full system still false-triggers—system common-mode loop or measurement reference error?”

Likely cause: System-level closure path changes (chassis coupling, harness routing, grounding) are re-routing injected current; or measurement reference is wrong, creating a false Vgs bump narrative.

Quick check: Repeat measurements with strict Kelvin reference and log TP5 bounce; compare bench vs system installation conditions while keeping the same trigger definition and bandwidth.

Fix: Control the closure path (return/partition) and re-validate with the TP map under real installation; do not “solve” by only slowing edges unless thermal impact is acceptable.

Pass criteria: False turn-on = 0 in the installed system over Y minutes; measurement repeatability shows < X V difference in Vgs bump across setups (placeholder).

8) “Only one phase is problematic—layout asymmetry or different power-loop parasitics?”

Likely cause: Asymmetric Kelvin return / clamp reference routing or phase-to-phase differences in parasitic coupling are changing injected current magnitude and closure impedance.

Quick check: Capture the same TP1/TP2/TP3 waveforms for all phases using the same probe method; compare Vgs bump timing/amplitude and TP2 bounce between phases.

Fix: Make the gate loop and return geometry symmetric; standardize damping components and placement; re-check partition boundaries around the isolation slot per phase.

Pass criteria: Phase-to-phase delta in Vgs bump < X V and mis-trips = 0 across all phases over N cycles / Y minutes.

9) “Fault recovers then immediately re-triggers—auto-retry too aggressive or latch/clear policy wrong?”

Likely cause: Retry occurs before the system returns to a stable state (rails/thermal/loop), creating repeat triggers; or clear policy releases faults into the same dv/dt corner condition.

Quick check: Log fault timing relative to UVLO events and switching edges; confirm whether the second trigger happens within a consistent short window after re-enable.

Fix: Add a controlled hold-off after fault clear and require stable rails before re-enable; re-validate blanking/threshold behavior during recovery transitions.

Pass criteria: After a fault, no re-trigger within X ms hold-off and mis-trips = 0 over N recovery cycles (placeholder).

10) “Slowing switching removes false triggers but temperature rises—add clamp or rebuild Kelvin loop first?”

Likely cause: Slower edges reduce injection spectral energy but increase switching loss; the root cause is typically off-state margin and closure loop control rather than edge rate alone.

Quick check: Compare Vgs bump and TP2 bounce before/after slowing edges; verify whether a clamp/turn-off strengthening would meet margin without large switching-loss penalties.

Fix: Prioritize Kelvin loop integrity and clamp return reference; then apply targeted HF damping. Use edge slowing only as a last step within thermal limits.

Pass criteria: False turn-on = 0 while temperature rise < X °C and switching efficiency stays above X% (placeholder) over Y minutes.

11) “After swapping isolated power module, false triggers increased—secondary noise or ground reference change?”

Likely cause: Secondary rail ripple/noise changed driver thresholds and clamp behavior; or reference/return routing changed the closure path for injected current.

Quick check: Measure secondary rail ripple and correlate with Vgs bump and TP4 faults; compare TP2 bounce and reference points before/after the module swap.

Fix: Improve secondary decoupling and return integrity, and re-anchor clamp/Kelvin references; if required, choose a bias solution with lower no-load noise and predictable return behavior.

Pass criteria: Mis-trips = 0 over Y minutes; secondary ripple stays below X mVpp and Vgs bump < X V under worst dv/dt (placeholders).

12) “Same driver, different batches behave differently—BOM tolerance or assembly/contamination?”

Likely cause: Component tolerance/impedance band shifts (Rg, bead, damping parts) or assembly contamination/leakage altering reference/closure paths near the isolation boundary.

Quick check: Compare BOM lot codes and measure key parts (Rg value, bead impedance class if available); inspect isolation slot/keep-out for residue and verify creepage surfaces are clean and dry.

Fix: Lock tolerances and approved alternates, control assembly cleanliness around the isolation boundary, and add production screening using the same TP-based evidence definition.

Pass criteria: Across N boards, false pulses = 0 and mis-trips = 0 over Y minutes; Vgs bump distribution stays within X V spread (placeholders).