Scope Guard

• Covered: how to size clearance/creepage using inputs (OVC/PD/CTI/altitude/coating), and how to implement them on PCBs using slots, keep-outs, barriers, coatings, and tolerance-aware layout rules.
• Covered: how to document and verify distances so they are measurable and review-ready (drawings, inspection evidence, worst-case accounting).
• Not expanded here: insulation class selection (basic/reinforced), impulse/surge withstand, hi-pot and partial discharge test methods. Link out only: Basic/Reinforced · Impulse/Surge · Production Tests

What this page delivers

1. A repeatable workflow: inputs → standards lookup → required distances → PCB implementation → verification evidence.
2. PCB techniques that reliably increase effective creepage/clearance: slots, barriers, keep-outs, coating strategy, and tolerance-aware rules.
3. Audit-ready documentation approach: how to “measure” and freeze separation distances in drawings, DRC rules, and inspection records.

H3 · Clearance (air gap)

• Definition: the shortest path through air between conductive parts on different potentials.
• Primary drivers: overvoltage environment (OVC), peak stress definition, and altitude (air pressure).
• Typical failure pattern: air breakdown is triggered by insufficient margin under reduced pressure, sharp geometry, or underestimated peak stress.

H3 · Creepage (surface path)

• Definition: the shortest path along an insulating surface between conductive parts.
• Primary drivers: pollution degree, material group / CTI, surface condition (residues, moisture films), and coating quality (coverage consistency).
• Typical failure pattern: surface leakage initiates on contamination, then progresses via tracking/carbonization, creating a conductive “highway” that bypasses nominal geometry.

H3 · Counting mistakes that cause audit failures

1. Measuring creepage as a straight line. Creepage must follow the surface, including around slots, steps, and edges.
2. Ignoring solder fillets, copper burrs, and sharp corners that reduce the real minimum distance and increase local field concentration.
3. Letting silkscreen, solder mask bridges, or contamination cross the isolation boundary without a defined keep-out and cleanliness policy.
4. Using nominal CAD distances as “proof.” Verification must account for worst-case stack-up (placement, process, and residue).

Gate rule (process)

• PD must be declared with an explicit environment assumption (contamination type, condensation probability, maintenance policy).
• CTI / material group must be traceable to a datasheet or supplier declaration for the actual surface (laminate + solder mask + coating).
• If any item is “unknown,” treat it as worst-case until evidence is provided and recorded.

H3 · Pollution Degree (PD): how to decide it in real deployments

• PD is an environment model: it reflects how likely an insulating surface becomes a conductive film due to contamination + moisture.
• The practical split is condensation risk: repeated temperature cycling and sealed volumes can create moisture films even when air looks “dry.”
• Maintenance assumptions matter: filtration, periodic cleaning, and enclosure strategy should be written down, otherwise PD cannot be defended.

H3 · CTI / material group: why it changes creepage requirements

• CTI is a proxy for tracking resistance: higher CTI surfaces resist carbonized “tracks” that turn leakage into a permanent short path.
• The relevant surface is not only the laminate: solder mask, residues, and coatings jointly define the effective tracking behavior.
• If CTI evidence is missing, creepage should be sized conservatively and flagged as a risk until the surface system is documented.

H3 · “Pollution upgrade” mechanisms seen in the field

• Dust + humidity → conductive moisture film → surface leakage rises first, often before any visible damage.
• Flux / ionic residues → invisible contamination → conductivity appears only under humidity or after thermal cycling.
• Salt fog / coastal air → electrolyte film → leakage becomes stable and aggressive even at moderate humidity.
• Oil mist → persistent film → difficult to remove → creepage margin erodes without any geometry change.

1. Condensation expected during temperature cycling (Y/N)?
2. Enclosure “breathes” moisture in/out (pressure changes, vents) (Y/N)?
3. Dust accumulation likely (fans, open vents, industrial floor) (Y/N)?
4. Salt fog / coastal exposure likely (Y/N)?
5. Oil mist / coolant / lubricant aerosols likely (Y/N)?
6. Cleaning/maintenance is periodic and specified (Y/N)?
7. PCB surface is washed/verified for residues in production (Y/N)?
8. Conformal coating is applied with coverage verification (Y/N)?
9. Sustained high humidity (long seasonal exposure) expected (Y/N)?
10. In-service contamination can remain for months without intervention (Y/N)?

H3 · Define voltage terms (working vs peak/transient)

• Working voltage (Vwork): the maximum continuous steady-state value for the insulation barrier.
• Peak voltage (Vpeak): the highest expected voltage during normal operation, including controlled switching events.
• Transient definition: record the project-specific peak event category (placeholder), but do not mix it with impulse/surge test waveforms handled elsewhere.

H3 · OVC determines the expected air-gap stress level

• OVC is a classification of the installation environment and its overvoltage exposure. Higher OVC generally implies higher expected air-gap stress and tighter clearance requirements.
• OVC should be justified by deployment notes (panel wiring, cable exposure, system boundary). If justification is absent, treat it as a risk and size conservatively.

H3 · Altitude reduces air breakdown margin (clearance must increase)

• Reduced air pressure at altitude lowers breakdown strength, so the same geometry can fail even if it passes at sea level.
• Altitude derating must be applied not only to PCB trace-to-trace gaps, but also to the tightest air routes around packages and connectors.

Workflow gates (must be locked in this order)

1. PD locked with assumptions + evidence (Y/N).
2. CTI / material group locked for the actual surface system (Y/N).
3. Surface path rule locked (slot/step/mask bridge/edge counting).
4. Coating claim locked: any “equivalent PD reduction” must follow the applicable standard and review policy.

• Creepage is the shortest path along the insulating surface between conductive parts. It is not the straight-line spacing.
• Slots force the route to detour and can increase effective creepage if the slot is continuous and the route cannot “jump” across surfaces.
• Steps / ledges must be counted by “wrapping” the surface; the route follows the actual contour.
• Solder mask bridges are a common audit dispute: a project must lock a counting rule and evidence for mask integrity and coverage.
• Board edges can become the shortest surface route in dense layouts; check edge-to-edge paths explicitly.

Required vs effective creepage (the only pass rule)

Required creepage comes from PD/CTI/Vwork lookup. Effective creepage comes from the shortest realizable surface route on the as-built geometry. Acceptance is Effective ≥ Required, documented with the route and assumptions.

• Coating can reduce moisture film formation and contamination attachment, improving surface robustness — but any claim must be aligned with the applicable standard and audit policy.
• If a project treats coating as a risk reducer, coverage must be verifiable (coverage area, thickness target, pinhole/void checks), otherwise it cannot be used as a sizing basis.
• Record coating status as a binary, auditable input (Y/N) with evidence references; avoid informal “it should help” assumptions.

• Sharp corners / narrow necks concentrate surface stress and are frequent starting points for leakage and tracking.
• Local contamination sources (residue, dust traps, vent paths) create a stable film that shortens the effective surface route.
• Progression: wet film → leakage current → localized heating → carbonized track → permanent short surface path.

• Altitude ↑ → air pressure ↓ → air breakdown strength ↓.
• A geometry that passes at low altitude can fail at high altitude without any PCB changes.
• Derating must be explicitly applied via a standard-aligned method and recorded as part of sizing evidence.

• Requirements must state Target altitude = X m (deployment maximum, not typical).
• Design records must include the correction method / multiplier (placeholder) and the standard edition used.
• Certification/test statements must reflect the declared altitude condition; if altitude is omitted, assumptions become undefined and difficult to audit.

• PCB spacing is updated, but connector pin-to-pin air gaps remain the minimum.
• Slots are added on PCB, but the tightest path is around a package body / module edge.
• Enclosure brackets or standoffs create an unexpected short air route.
• Mechanical tolerance eats the minimum gap; altitude derating must include tolerance reserve.

Technique map (what each knob controls)

• Slots: force surface route detours → increases effective creepage.
• Barriers: block or reroute the shortest path across assemblies.
• Keep-outs: prevent copper/mask/silkscreen from creating a new shortest route.
• Guard rings: manage surface leakage route on the isolation side (not an EMI topic).

• A slot is effective only when it forces the shortest surface route to go around it.
• Lock edge-to-copper around the slot; a tight copper edge can become a new shortest route and tracking start point.
• Ensure the slot is continuous across the intended isolation corridor; partial slots may not change the shortest path.
• Acceptance requires a shortest-route snapshot showing the pre-slot path X and the post-slot path X’.

• Barriers reroute the shortest path across assemblies; the barrier surface can also become a creepage surface.
• Include mechanical tolerance reserve; the minimum gap is the as-built gap, not the nominal CAD gap.
• Verify coverage at the true minimum points: near connector pins, package edges, and any mounting features.
• Acceptance: document the minimum air route and surface route with a labeled geometry snapshot.

• Copper keep-out must include traces, pours, vias, test pads, thermal copper, and any copper features that could reduce the minimum spacing.
• Mask opening keep-out prevents exposed edges from becoming a weak surface region; lock the project’s mask counting rule consistently with creepage sizing policy.
• Silkscreen keep-out prevents bridge-like markings across the isolation corridor that can accumulate contamination.
• Acceptance: DRC must flag any layer that crosses the isolation corridor (copper/mask/silkscreen).

• A guard ring provides a controlled collection route for surface leakage, reducing unpredictable leakage paths across the isolation corridor.
• Place the guard on the intended side only; it must not cross the isolation gap or violate keep-out rules.
• Guard is not a substitute for spacing; it must be applied only after required/effective creepage and clearance are satisfied.
• Acceptance: guard continuity and keep-out compliance are checked by DRC and by geometry snapshot.

• Serviceability: potting reduces repair access and changes field diagnostic strategy.
• Thermal: potting alters heat paths and can create new stress points; thermal policy must be documented.
• Voids/bubbles: local voids can become weak spots; inspection/controls must be defined.
• Aging: shrink/crack over life can re-expose a surface route; lifetime assumptions must be consistent with the safety case.

• Clearance remains an air rule: surface treatment cannot be used as an informal substitute.
• Edge thinning: coating is often thinner at edges and near tall components; thin regions can become leakage weak points.
• Pinholes: a single pinhole can create a continuous leakage route under humidity; inspection is mandatory for any safety claim.

Shortest-path hijackers (what to check first)

• Package body / lead root becomes the creepage surface.
• Connector housing creates a new surface route between terminals.
• Solder fillet growth reduces air gap (clearance) vs CAD nominal.
• Placement/tilt shifts the minimum gap toward one side (worst-case stack-up).

• Minimum separation is defined by the as-built geometry, not only copper-to-copper spacing.
• Datasheet package drawings define body/lead dimensions that can create the true shortest surface route.
• Document the measurement point pairs (pin-to-pin / pad-to-pad / body-to-body) to make review and inspection reproducible.

• Connector terminal pitch and housing surface can form a shorter route than the PCB corridor.
• For isolation modules/transformers, treat the external body surface as part of creepage routing; do not assume PCB-only routing.
• Promote key connectors/modules to critical characteristics for incoming and outgoing inspection.

• Clearance can be reduced by solder fillet growth and by sharp solder peaks near the isolation corridor.
• Worst-case stack-up must assume placement shift toward the same side (do not average away the risk).
• Residues and localized contamination change the surface condition; inspection points must record evidence (photo ID + point pairs).

• Isolation boundary: show the corridor and the point pairs that define the minimum gap.
• Keep-outs: list copper/mask/silkscreen constraints; show slots and edge-to-copper rules.
• Inputs: link PD/CTI/coating policy (Y/N) and altitude assumption to the drawing set.

• Use fixed measurement point pairs and a defined method (microscope/fixture template — placeholders) so results are reproducible.
• Layered checks: incoming (connectors/modules), in-process (solder shape), outgoing (critical minimum gaps).
• Record X/Y/N plus photo ID for each critical point pair; avoid “freehand” interpretation during audit.

1. Tighten keep-outs (fastest, low risk): prevent copper/mask/silkscreen crossings.
2. Add/extend slots (strong geometry): force surface route detours for creepage.
3. Change package/connector (higher impact): remove the shortest-path hijacker.
4. Add barriers (needs mechanical alignment): document tolerance reserve and minimum points.

Design checklist (Design Gate)

Bring-up checklist (Bring-up Gate)

Production checklist (Production Gate)

Bucket · Motor / Inverter

Primary knob: clearance-first when altitude/transients dominate; reinforce creepage with slots where surface routes are unavoidable.

Bucket · BMS / HV Systems

Primary knob: creepage-first when pollution/condensation dominates; enforce cleanliness + coating coverage gates.

Bucket · Medical

Primary knob: balanced—avoid relying on “coating as a blanket fix”; prioritize geometry + auditable inspection points.

Bucket · Industrial I/O

Primary knob: creepage-first for surface contamination; enforce incoming connector pitch + outgoing minimum-gap sampling.

Bucket · EV Onboard Charger (OBC)

Primary knob: clearance-first when altitude is a requirement; creepage is maintained by geometry and controlled coating where appropriate.