This page is a build-and-debug guide for a pressure / differential pressure transmitter front end: it focuses on measurable evidence, repeatable workflows, and design decisions that survive production and field conditions.

Each section ends with evidence fields (nodes, waveforms, registers, or logs). Those fields are intended for fast verification and repeatable troubleshooting. No scope creep

The transmitter can be treated as a chain of error injection points. The goal is to define module boundaries, identify which errors dominate at each boundary, and name the first evidence to capture before changing hardware or firmware.

• Excitation boundary: confirm VEXC accuracy and noise; excitation drift often looks like span drift if the reference strategy is inconsistent.
• Bridge boundary: confirm VBRIDGE± differential level and common-mode pickup; long leads make CMRR and input filtering critical.
• Analog boundary: confirm INA_OUT noise floor and settling; offset/1/f dominates near zero and during deep filtering.
• ADC boundary: confirm raw codes RMS noise and line-frequency rejection at the chosen data rate; “24-bit” is not ENOB.
• Loop boundary: confirm ILOOP vs VLOOP (compliance headroom); loop dropout can alias as measurement instability.
• HART boundary: confirm HART_INJ amplitude and check that injection return path does not modulate analog ground or reference nodes.

• Span drift that tracks excitation noise/temperature usually points to VEXC / reference strategy before sensor nonlinearity is blamed.
• Zero drift with strong time dependence often points to INA offset/1/f or thermal gradients near the front end.
• Hum pickup that changes with cable routing points to common-mode coupling and insufficient rejection at the input boundary.
• Ripple only when HART is active points to injection return path modulating analog ground/reference nodes.
• Reading instability at low loop voltage points to compliance headroom and loop stage dropout behavior.

Bridge sensors produce a ratio signal (mV/V). Many “mysterious drift” cases are not caused by the bridge itself, but by a scale mismatch between excitation (VEXC or IEXC) and the ADC reference (VREF), or by thermal gradients that break the assumed tracking.

Excitation strategies (and what they silently inject)

• Fixed voltage excitation (VEXC constant): bridge output scales with VEXC. If VREF is independent, span follows VEXC drift.
• Fixed current excitation (IEXC constant): output depends on bridge resistance; bridge R(T) becomes an error source and can look like span drift.
• Ratiometric reference: the ADC reference tracks excitation (or is derived from the same scale path), cancelling first-order excitation drift.

What still drifts (even with ratiometric)

• Bridge tempco & creep: intrinsic resistance and sensitivity shifts with temperature/time.
• Package / mounting stress: mechanical stress changes effective strain coupling and zero.
• Humidity / contamination: surface leakage and insulation changes can create slow offsets.
• Wiring & contacts: lead resistance and contact stability can distort effective excitation and symmetry.

Evidence fields to capture (turn drift into a diagnosis)

In a transmitter, “low drift” is not a single number. The dominant error often lives in the low-frequency region (0.1–10 Hz), where offset drift, 1/f noise, bias-current imbalance, and common-mode conversion create pressure-equivalent error that looks like sensor drift.

Key pitfalls and how to make them measurable

• Bias-current error grows silently: higher bridge resistance or unbalanced input resistors increase bias-induced offset. Check offset vs simulated source impedance.
• CMRR collapses via asymmetry: mismatch in input RC/filter/protection leakage converts CM noise into DM. Check CM injection sensitivity, not only “CMRR spec”.
• Chopper ripple becomes visible: ripple can leak into the ADC passband if filtering and sampling strategy are not coordinated. Check ripple amplitude at INA_OUT.

First measurements (a minimum SOP before redesign)

• Shorted-input noise: measure 0.1–10 Hz RMS under the intended gain and ADC filter settings; this predicts low-frequency stability.
• Step response: apply a small differential step and record settling time and overshoot; auto-zero settling issues appear here.
• CMRR injection test: inject a known common-mode ripple onto bridge leads and measure output sensitivity (µV_out per V_cm).
• Leakage sensitivity: repeat zero measurement across temperature; leakage-related drift often grows strongly with temperature.

Evidence fields to capture (mechanically verifiable)

“24-bit” describes the code width, not the usable resolution. The usable resolution is determined by the chosen data rate (SPS), digital filter configuration, reference noise, and the input network. ADC selection becomes deterministic only when noise, throughput, and line-frequency rejection are treated as a single constraint set.

ENOB vs data rate (what changes when SPS changes)

• Higher SPS: less averaging and shorter digital filtering → higher RMS noise → lower ENOB in practice.
• Lower SPS: more averaging and deeper filtering → lower RMS noise → higher usable resolution, but longer settling/latency.
• sinc/comb filters: can place notches at specific frequencies and strongly shape group delay; response time must be proven with a step test.

Reference strategy (where “drift” often hides)

• External reference: strong absolute stability, but excitation drift will still move bridge output unless compensated or made ratiometric.
• Ratiometric reference: cancels first-order excitation drift by sharing scale, but reference-path noise and coupling become visible in the codes.
• Coupling reality: reference noise can be injected through supply/ground, digital activity, or loop/HART coupling paths; this must be validated with evidence fields.

Input sampling network & anti-alias constraints

• Symmetry matters: asymmetric input RC or protection leakage converts common-mode interference into differential error.
• RFI/EMI conditioning: input networks must attenuate RF without creating slow settling or gain error across temperature.
• ΣΔ is not magic: digital filtering does not remove all aliased or injected components; validate with line-frequency and step-settling measurements.

Evidence fields (minimum set to claim “usable resolution”)

An error budget is a mechanical checklist that converts every contributor into a common unit (%Span) and separates what calibration can remove from what remains as residual, noise, and long-term drift. The result is an auditable path from bridge mV/V to transmitter accuracy claims.

Budget components (minimum list)

• Bridge: sensitivity tolerance, tempco, long-term stability (creep/stress sensitivity).
• Excitation: accuracy and drift (and whether ratiometric cancels it at first order).
• INA: offset/gain error/drift, 0.1–10 Hz noise, bias/leakage-induced imbalance, CM→DM sensitivity.
• ADC: gain/offset, INL, measured RMS noise at chosen SPS, and verified line-frequency rejection.
• Temperature sensor: absolute accuracy, self-heating, placement gradient vs the bridge and analog front end.
• Calibration residuals: fit error and quantization/resolution limits; coefficient integrity (CRC/version) influences production consistency.
• Post-cal drift: humidity/leakage and mechanical stress gradient (often dominates long-term stability).

Reusable error budget template (copy into a spreadsheet)

Each row must include unit, conversion to %Span, calibratable vs residual, and a measurement field that validates the assumed value.

Aggregation (worst-case vs RSS)

• Worst-case: sum of absolute maxima (conservative upper bound for specification and safety margin).
• RSS: root-sum-square for independent contributors (useful for typical performance expectations).
• Decision use: the largest rows dominate design choices; reduce the dominant row before optimizing minor contributors.

A production-grade compensation strategy is built around two layers: (1) sensor/bridge compensation that stabilizes the raw transfer function, and (2) electronics/system compensation that removes remaining temperature-dependent offsets and gain errors. The model is only as reliable as the coefficient governance: CRC, versioning, write protection, and a safe update policy.

Model options (choose for stability + governance, not for “fit vanity”)

• Polynomial (2–4th): compact and fast; must avoid extrapolation outside validated temperature range.
• Piecewise linear: stable and bounded; uses breakpoints and segment slopes; resistant to edge blow-up.
• LUT + interpolation: robust for complex curves; requires fixed axis definition and interpolation method compatibility across firmware.

Update policy (avoid “bricking accuracy”)

• Factory-only coefficients: best consistency; field access limited to bounded zero trim with strict guardrails.
• Field recalibration: allow only with explicit rules: stable temperature conditions, limited write count, full record capture, and rollback path.
• Failure behavior: if CRC/version fails, force a safe degraded mode (flag diagnostics, freeze output mapping or fall back to safe defaults).

Evidence fields (mechanical, auditable)

Calibration that achieves an accuracy specification is not a single action; it is a controlled workflow with stabilization criteria, point sequencing, hysteresis handling, and traceable artifacts. For differential pressure transmitters, the workflow must explicitly cover positive/negative DP points and define overpressure behavior and recovery checks.

DP-specific requirements (positive/negative points and hysteresis)

• Signed DP coverage: include both positive and negative pressure points around zero to validate sign transition and symmetry.
• Hysteresis handling: define whether rising/falling curves are averaged, separately modeled, or treated as a bounded residual term.
• Overpressure behavior: after an overpressure event, verify zero shift and define whether the unit requires recalibration or enters a diagnostic state.

Production flow (warm-up, stabilization, sequencing)

• Warm-up: allow analog and reference domains to reach steady behavior before collecting coefficients.
• Stabilization criteria: accept a point only when output slope and temperature change rate remain within thresholds over a time window.
• Sequencing: zero → positive points → negative points → return points (hysteresis check) → optional overpressure + recovery check.

Traceability artifacts (minimum calibration record structure)

The loop stage must be designed as a “non-interference subsystem”: it must meet compliance voltage and transient requirements without injecting supply/ground disturbance into the measurement chain. The deterministic approach is a worst-case headroom budget, a bounded output-generation method, and explicit fault behavior that is stable under real burdens and wiring.

Compliance voltage and headroom (budget, not a datasheet number)

• Burden voltage: loop current × burden resistor dominates the DC drop at 20 mA.
• Wiring drop: loop current × wiring resistance grows with distance and conductor gauge; include connectors and terminal blocks.
• Barrier drop: safety barriers/isolators add voltage drop and may alter AC impedance for HART.
• Driver headroom: the loop driver needs a minimum internal voltage to regulate current; insufficient headroom causes dropout and oscillatory behavior.

Fault behaviors (bounded and testable)

• Open loop: define detection via loop voltage behavior and current regulation failure; latch or retry policy must not create output chatter.
• Short / overload: define current limit, thermal protection, and recovery policy; avoid fast oscillation during overload.
• Over/under-range signaling: support a standard alarm-current convention (e.g., NE43-level behavior) at a high level without compromising DC accuracy.
• Non-interference rule: during fault entry/exit, measurement-domain sampling should remain bounded (freeze window or controlled filter state reset).

Evidence fields (mechanical acceptance)

HART should be “boringly reliable”: stable communications across burden and wiring variations, without injecting FSK energy into the measurement domain or destabilizing the DC current regulation loop. The deterministic method is to control the injection point and impedance, partition filtering between analog and digital, and validate success rate under disturbance while watching DC accuracy simultaneously.

Keeping measurement clean (filtering partition)

• Analog partition: keep HART energy in the loop domain; prevent coupling into ADC reference and sensor front end via supply/ground return paths.
• Digital partition: ensure decimation and notch strategies do not alias HART-related interference into the low-frequency measurement band.
• Ground separation: define measurement ground vs loop return to prevent “FSK rides on the wrong reference”.

Evidence fields (minimum)

Industrial robustness is not only about surviving events; it is about surviving events without creating hidden bias in the measurement chain. Long cables, lightning transients, ground offsets, and wiring mistakes must be translated into controlled energy paths, bounded saturation behavior, and diagnostic evidence that makes intermittent field failures reproducible.

Input protection that does not “leak into bias”

• Leakage becomes offset: clamp/TVS leakage and protection-path currents can translate into a measurable zero shift, especially with higher bridge impedance.
• Placement matters: protection near the connector controls energy entry, while protection near the INA can create direct leakage into the measurement node.
• Symmetry matters: mismatched protection impedance converts common-mode disturbance into differential error.
• Acceptance idea: verify zero stability after high-temperature/high-humidity stress; leakage-driven drift should be visible as a repeatable bias shift.

RFI filters that do not destabilize INA/ADC

• Two-stage partition: connector-side common-mode energy management, then near-INA differential filtering for fine control.
• Corner selection: choose filter corners that suppress RF ingress without creating excessive settling time or interacting badly with ΣΔ latency.
• Source impedance control: added series resistance and capacitance must not create instability or long recovery tails after transients.
• Verification: inject common-mode ripple and confirm that INA/ADC do not show ringing, step anomalies, or unexpected drift.

Surge/ESD: where the energy goes and what saturates first

• Energy path definition: surge current should be directed into controlled clamps and return paths, not through measurement references or sensitive inputs.
• First saturators: TVS/clamps, barrier elements, front-end protection switches, and loop driver headroom are typical “first-to-hit” components.
• Post-event behavior: define bounded recovery (no chatter), rail/reference monitoring, and a clear diagnostic state when accuracy cannot be trusted.

Diagnostics worth implementing (minimum set)

Evidence fields and last-fault log (make “intermittent” reproducible)

• Fault flags: sensor open/short, INA sat, ADC clip, ref/excitation low, loop open/short (as applicable).
• Monitors: VREF, VEXC, key rails (measurement vs loop), ILoop sense, temperature code.
• Last-fault snapshot: code + timestamp/tick + rail/ref/excitation + ILoop + raw ADC + status bits + counter.
• Policy: define latch vs auto-clear and hysteresis to prevent chatter; define “accuracy not trusted” state when monitors fail.

Each answer points back to the evidence chain on this page: excitation/reference monitors, INA/ADC status, ΣΔ filter settings, loop headroom, HART coupling, and last-fault logs. Use the checks as a minimal sequence to isolate the dominant cause before changing calibration models.