dv/dt Injection & Protection for Isolated Gate Drivers
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Core idea: dv/dt injection is displacement-current noise that becomes a failure only after it closes an unintended return loop and pushes a sensitive node across a threshold inside a timing window. Protection means controlling the path, shrinking the loop, and enforcing safe defaults under worst-case slew.
H2-1 · Scope & Boundary (dv/dt Injection & Protection)
Card A · What dv/dt injection is
Definition: dv/dt injection is unintended disturbance driven by displacement current (through parasitic capacitance and shared impedance) that appears on logic, gate, or supply-reference nodes.
Why it matters: it can create false edges, false turn-on, resets, and isolated-link bit flips—even when “signal integrity looks fine” at steady state.
Card B · What this page will / will not cover
Intent: lock the boundary so content never overlaps with sibling pages.
In-scope (this page must solve):
- Injection paths: coupling + return-path closure (barrier capacitance, shared impedance, loop area).
- Symptom → root cause mapping: false turn-on, resets, isolated link flips, measurement artifacts.
- Protection levers: layout/loop control, gate-drive hardening (Miller clamp), isolator I/O hardening, bias & PI, verification.
- Acceptance language: pass/fail thresholds and stress recipes (corner coverage).
Out-of-scope (only referenced, not expanded):
- Device internal process details and modulation/encoding internals.
- Full EMC/ESD standard clause-by-clause interpretation.
- Complete isolated power topology design; only dv/dt-related coupling/loop points are discussed.
Boundary rule: if a paragraph cannot be explained as “coupling + loop closure + threshold window”, it does not belong on this page.
Reader self-check: identify (1) dv/dt source node, (2) sensitive threshold node, (3) unintended return path. If any is unknown, the next section defines the model to find it.
H2-2 · dv/dt Mental Model & Terminology
Card A · Mental model (one framework used everywhere)
Step 1 — Source: dv/dt is created by switching edges at nodes like SW/half-bridge midpoint, drain/collector, and motor phase nodes. Faster edges increase dv/dt and shift the energy toward higher frequencies.
Step 2 — Coupling current: “Injection” is not mysterious radiation—most failures start as displacement current. The only formula needed here is I = C · dv/dt (concept only): higher dv/dt or larger parasitic C creates higher injected current.
Step 3 — Loop closure: injected current must return. The return route (shared ground, shared supply impedance, chassis/bond path) determines where a voltage disturbance forms and which thresholds get crossed.
Step 4 — Failure trigger: a glitch is only a failure when it (a) crosses a threshold and (b) lands inside a sensitive timing window (e.g., turn-off interval, comparator decision instant, reset sampling window).
Card B · Key terms (definitions + engineering meaning)
- dv/dt: edge slew rate at a switching node; higher dv/dt increases displacement current and timing sensitivity.
- Displacement current (I = C·dv/dt): the dominant “injection engine” through parasitic capacitances.
- Barrier capacitance (Cbar / Cpar): sets how much common-mode current crosses an isolation boundary.
- CMTI: device-level tolerance against fast common-mode transients; necessary but not sufficient without loop control.
- Loop area: larger unintended loops convert injected current into higher disturbance and radiate more energy.
- Ground bounce (ΔV = I·Zshared): shared impedance turns return current into reference shifts and false thresholds.
- Threshold window: the time interval where a node decision is vulnerable (gate turn-off, reset sampling, comparator decision).
What to observe in real systems: common-mode current signatures, ground reference movement, glitch amplitude/width, and whether glitches align with a vulnerable timing window rather than appearing uniformly.
H2-3 · Injection Paths (Coupling + Return Path Closure)
Card A · Coupling element checklist (C / L / Zshared / near-field)
Goal: break every “dv/dt problem” into an actionable chain: coupling element → victim node → return-path closure → observable clue. If a path cannot be expressed this way, it is not a diagnosable injection path.
Capacitive coupling (C) — displacement current across parasitic C
Coupling elements: Cgd/Cds, transformer/winding parasitics, barrier capacitance (Cbar), safety Y-cap.
Victim nodes: gate node, isolator input threshold, reset/interrupt pins, high-impedance analog nodes, clocks.
Return closure: injected common-mode current returns through shared ground/supply impedance or chassis/bond paths.
Observable clue: narrow glitches aligned to dv/dt edges; strong sensitivity to measurement reference and “where ground is defined.”
Inductive coupling (L) — magnetic pickup from high di/dt loops
Coupling elements: power loop and gate loop magnetic fields; any loop area that can “receive” flux.
Victim nodes: nearby gate traces, sense traces, isolator input traces, long return loops.
Return closure: the victim loop itself closes the disturbance (loop area is the amplifier).
Observable clue: strong sensitivity to geometry (trace routing, loop area, harness position) even when dv/dt is unchanged.
Common-impedance coupling (Zshared) — reference shift and ground bounce
Coupling elements: shared copper, vias, planes, supply rails, decoupling return segments (shared Z).
Victim nodes: anything judged against a reference (logic thresholds, comparators, reset sampling, isolator inputs).
Return closure: dv/dt-driven current (and power current) flows through the same impedance segment as the victim reference.
Observable clue: “signal looks fine” on one reference, but crosses threshold on another; multiple logic anomalies correlate to the same event.
Radiated near-field — edge injection into high-impedance structures (keep brief)
Coupling elements: strong E/H fields close to fast edges; long/high-impedance structures act as antennas.
Victim nodes: high-impedance pins, long traces, floating test points, reset/clock lines.
Return closure: depends on the surrounding structure; often changes with chassis/harness geometry.
Observable clue: sensitive to distance/orientation/shielding more than to probe reference changes.
Card B · Most vulnerable nodes (what gets pushed across thresholds)
dv/dt injection becomes a failure at nodes where a small disturbance can cause a decision error. The list below is organized by why the node is vulnerable, not just by name.
Threshold nodes (crossing Vth changes state)
Examples: gate node (Vgs), isolator input threshold, reset pin, interrupt pin.
Typical outcome: false turn-on, chatter, asynchronous resets, spurious interrupts.
High-impedance nodes (small current creates large ΔV)
Examples: comparator inputs, ADC sampling nodes, sense amplifiers, floating test pads.
Typical outcome: sampling glitches, false protection triggers, transient measurement corruption.
Asynchronous decision nodes (sensitive timing windows)
Examples: reset sampling windows, watchdog inputs, edge-triggered interrupts, latch pins.
Typical outcome: “random” events that actually correlate to switching edges.
Clock/reference nodes (small jitter/glitches cause large system effects)
Examples: clock pins, reference rails, logic thresholds tied to moving grounds.
Typical outcome: link errors, metastability, timing slips, protocol-level symptoms with physical roots.
Card C · Return-path closure patterns (fast path classification)
Common closure patterns:
- Shared ground segment: return current flows through the same copper used as logic/gate reference (ground bounce).
- Supply/decoupling return: transient current shares a decap loop with a sensitive rail, creating VDD dips.
- Chassis/bond path: return routes shift with cable/chassis bonding; behavior changes between bench and system.
3-question triage:
- Is the glitch tightly aligned to dv/dt edges? → likely C-driven.
- Does changing the measurement reference drastically change “glitch size”? → likely Zshared.
- Does geometry (loop area / trace routing / harness pose) dominate the change? → likely L or near-field.
H2-4 · Failure Modes & Symptom → Root Cause Map
Card A · Symptom map (Symptom → likely path → quickest check)
Many dv/dt failures look like firmware or protocol problems. The goal here is to pull each symptom back to the physical path category (C / L / Zshared / near-field) and run the fastest discriminating check.
False turn-on / unexpected switching
Likely path: gate-node injection (C) and/or Zshared reference shift.
Quickest check: measure Vgs(off) with Kelvin reference; confirm whether a threshold crossing is real or reference-induced.
Intermittent reset / brownout during switching
Likely path: Zshared coupling (supply/ground bounce) or C-driven current into control rails.
Quickest check: log VDD transient and reset pin behavior aligned to dv/dt edges (same timebase).
Isolated link chatter / bit flips
Likely path: input threshold crossing (C/Zshared) and near-field pickup on high-impedance inputs.
Quickest check: add temporary deglitch at the input (for classification only) and observe if chatter collapses.
Sampling glitch / measurement spikes
Likely path: high-impedance node injection (C/near-field) and return closure through shared analog reference (Zshared).
Quickest check: compare the same node using two references (system ground vs local analog/Kelvin ground).
Protection mis-trigger (DESAT/SC/UVLO) without real fault
Likely path: threshold window hit by dv/dt event; reference motion or injected spikes into sense pins.
Quickest check: correlate mis-triggers with switching edges and inspect sense pin waveform with correct probing.
Debug discipline: validate measurement first, then classify the path, then run one hypothesis at a time (change one variable per experiment). Multi-variable changes produce false confidence.
Card B · False turn-on vs true shoot-through (avoid misdiagnosis)
Definitions (use consistent acceptance language)
False turn-on: dv/dt pushes Vgs (or an equivalent threshold node) across Vth briefly, creating unintended conduction.
True shoot-through: overlapping conduction of high-side and low-side devices that produces a large, sustained current event.
Minimum discriminating evidence (what to check first)
Check 1: is the observed Vgs crossing referenced correctly (Kelvin source/emitter)?
Check 2: does current/thermal/protection behavior match real overlap, or is it a narrow transient without energy?
Check 3: does the event align with a vulnerable window (turn-off interval, blanking time, comparator decision)?
Common traps (why teams chase the wrong root cause)
Trap: probe reference creates “fake” threshold crossings (ground bounce misread as gate voltage).
Trap: protocol-level errors blamed on firmware while the physical path category remains unclassified.
H2-5 · Quantify: Specs, Budgets, and Pass/Fail Thresholds
Card A · Budget worksheet (variables that must be written down)
Purpose: convert “should be robust” into numbers that can be reviewed, tested, and accepted. The worksheet below is the minimum set needed to quantify dv/dt injection risk.
dv/dt target classes (use as stress level language)
- Class A (moderate): ~20–50 kV/µs
- Class B (high): ~50–150 kV/µs
- Class C (extreme): >150 kV/µs
Higher dv/dt increases displacement current approximately linearly for the same effective coupling capacitance.
Budget worksheet fields (fill before claiming “robust”)
- Stress inputs: dv/dt (rise & fall), switching voltage, event repetition rate.
- Coupling + loop: Ceq sources (Cbar/Y-cap/area), loop geometry, Zshared segment(s).
- Victim tolerance: Vth margin, reference definition (GNDs vs Kelvin), sensitive timing window.
- Observation definition: what counts as a glitch (amplitude/width), where it is measured, and how it is counted.
How key specs are used (not datasheet paraphrase)
- CMTI (±): device survival line under fast common-mode steps; necessary, not sufficient without loop control.
- Propagation delay / skew: shapes vulnerability windows (dead-time overlap risk, edge-alignment sensitivity).
- Barrier capacitance: first-order driver of common-mode current (Icm ≈ Ceq·dv/dt).
Card B · Acceptance examples (define pass/fail windows)
Rule: acceptance must specify reference, window, and counting. Otherwise “glitch amplitude” comparisons are meaningless.
Glitch amplitude / width (at a defined reference)
Amplitude: < X mV (measured vs defined reference: GNDs or Kelvin)
Width: < Y ns (equivalent time above threshold, not just visible ringing)
Event counters (per N switching edges)
False edges: 0 / N switching events
Output chatter: 0 / N events (or < X per 10^6 edges)
Reset count: 0 within Y minutes (or 0 within N stress cycles)
Window definition (where failures actually happen)
Window: define the vulnerable interval (turn-off, blanking, reset sampling, comparator decision).
Counting rule: only count events inside the defined window to avoid mixing unrelated noise.
H2-6 · Layout & Loop Control (Minimize Gate Loops, Compact Current Loops)
Card A · Do/Don’t layout constraints (reviewable, not slogans)
Goal: reduce dv/dt injection by controlling loop area and eliminating shared impedance at threshold references. Each rule is written to be auditable in layout review.
Gate loop (Driver → Gate → Kelvin return)
- Do: keep the gate loop as a tight closed loop with a dedicated Kelvin source/emitter return.
- Do: keep gate loop routing away from the power loop and switching node copper.
- Don’t: allow gate return current to share the power ground segment (creates Zshared-induced Vth shift).
Power loop (half-bridge current loop)
- Do: minimize the half-bridge switching current loop area to reduce di/dt magnetic coupling.
- Do: keep high di/dt copper compact and local; avoid long, wide “antenna” shapes.
- Don’t: run sensitive traces parallel to switching copper over long distances.
Return path discipline (no cross-gap returns)
- Do: provide a tight, adjacent return reference for every fast edge signal (signal + return as a pair).
- Don’t: create “across-the-gap” returns where the signal crosses but the return detours (loop explosion).
Card B · Barrier keepout checklist (reduce unintended C across the gap)
Goal: keep the isolation boundary from becoming a large unintended coupling capacitor. This checklist focuses on dv/dt injection risk (not full safety-standard text).
Keepout items (audit in layout review)
- Across-gap routing: avoid traces crossing the barrier gap that force a detoured return (loop expansion).
- Copper area facing copper: minimize large facing planes/pours across the barrier (raises Ceq).
- Metal parts: heatsinks/shields near the barrier can increase coupling; treat as coupling structures.
- Capacitors near barrier: placement can create strong common-mode coupling paths (classify as Ceq source).
- Y-cap usage: only as needed for EMI; recognize it intentionally conducts common-mode current.
- Reference mixing: prevent control reference from sharing the switching return segment (Zshared injection).
Layout review gate (pass before tape-out)
- Gate loop and power loop can be drawn as closed loops with clearly defined returns.
- No signal crosses a gap without a tight adjacent return strategy.
- All across-barrier facing copper areas are identified as Ceq sources and minimized.
- Kelvin reference points are explicit for threshold measurements (Vgs, reset, isolator inputs).
H2-7 · Gate-Drive Countermeasures (Miller Clamp + Gate Shaping)
Card A · Knob ladder (Level 1–4, from mild to aggressive)
Purpose: reduce dv/dt-driven gate lift by applying countermeasures in a controlled escalation order. Each level targets a specific part of the injection chain and has defined side effects.
Miller false turn-on mechanism (what is being suppressed)
Source: switching-node dv/dt drives displacement current through Cgd.
Gate lift: injected current produces ΔV on the gate loop impedance (driver pull-down + loop).
Failure condition: Vgs(off) crosses the effective threshold during a vulnerable timing window.
Level 1 · Gate shaping (mild)
Knobs: split Rg (turn-on/turn-off), diode bypass shaping, stronger controlled pull-down.
What it attacks: reduces the gate-loop impedance seen by injected current.
Side effects: switching speed changes → loss/EMI/thermal direction shifts.
Level 2 · Miller clamp (stronger)
Knobs: internal or external clamp to a low-impedance node.
What it attacks: provides a low-Z sink path so injected current does not lift the gate.
Side effects: clamp loop must be short and correctly referenced; otherwise effectiveness collapses.
Level 3 · Negative turn-off (-Voff, aggressive)
Knobs: negative gate bias to increase off-state margin.
What it attacks: increases Vth margin against dv/dt-driven lift (does not remove the injection source).
Side effects: tighter absolute-rating constraints and bias supply complexity.
Level 4 · Structural fixes (go back to loops)
Trigger: Level 1–3 still fail → dominant cause is usually loop geometry or shared impedance.
Action: return to loop control (Kelvin reference, compact gate loop, avoid Zshared).
Side effects: requires layout iteration; often the highest leverage.
Card B · Pass criteria examples (gate-specific acceptance)
Rule: acceptance must define reference (Kelvin vs system ground), window (when dv/dt stress occurs), and counting (per N edges).
Waveform criteria (Kelvin referenced)
Vgs(off) peak: < X V during dv/dt edge window
Above-threshold duration: < Y ns (effective time crossing the decision threshold)
Energy / event criteria (system-visible)
False turn-on energy: < Y mJ (integrate Vds·Id over the defined window)
False turn-on count: 0 / N switching edges
Coordination checks (avoid “fix creates new failure”)
DESAT/SC: no spurious trips caused by gate shaping or clamp dynamics.
UVLO/dead-time: deterministic behavior across PVT; no vulnerable window expansion beyond acceptance limits.
H2-8 · Barrier/Logic Hardening (Isolator Inputs/Outputs Under dv/dt)
Card A · Input hardening recipe (filter → threshold → deglitch)
Purpose: when dv/dt primarily attacks logic thresholds, hardening must remove glitches before they become decisions. The chain below provides escalating knobs with predictable tradeoffs.
Level 1 · RC conditioning (analog deglitch)
What it does: reduces short glitch amplitude by slowing the input transition.
Design handle: choose τ relative to the minimum valid pulse width (placeholders: τ, X ns).
Tradeoff: slows edges and adds delay; must not break valid timing.
Level 2 · Schmitt threshold / hysteresis
What it does: prevents small reference motion from repeatedly crossing the decision threshold.
Design handle: ensure hysteresis exceeds the expected dv/dt-induced ΔV margin (placeholder: X mV).
Tradeoff: changes switching points; must be compatible with logic levels and noise margins.
Level 3 · Glitch filter (minimum pulse width)
What it does: rejects pulses shorter than a defined width threshold.
Design handle: min pulse width > X ns; count events per N edges for acceptance.
Tradeoff: adds deterministic delay; may mask narrow legitimate pulses if misconfigured.
Card B · Fail-safe definition (power-up/down must be deterministic)
Goal: avoid “software-looking” failures by defining hardware-default behavior under undervoltage and power transitions.
Fail-safe items (write as acceptance language)
- Default state: output must be a defined state under UVLO/power-down (0/1/Hi-Z, placeholder).
- No chatter: no toggling during power ramp or UVLO region (0 events within defined window).
- Deterministic release: output transitions only after the defined valid-supply condition is met.
- Diagnosable behavior: optional fault indication pin/state (define what “fault” means, placeholder).
Channel tradeoffs (selection logic only)
Differential vs single-ended: differential signaling often improves common-mode resilience but increases interface constraints.
Edge-rate control: slower edges can reduce false thresholds at the cost of timing margin.
Cbar vs CMTI: lower Cbar reduces Icm, but sufficient CMTI is still required; both must satisfy the budget chain.
H2-9 · Isolated Bias & Power Integrity Under dv/dt
Card A · Power symptom map (power issues disguised as signal failures)
Purpose: identify cases where dv/dt stress produces supply dips or ground bounce that cross logic thresholds. The mapping below prevents mislabeling power integrity events as “communication bugs”.
Symptom → likely power path → quickest check
- Bit flips / chatter: ΔGNDs or VDD dip at threshold reference → probe with correct Kelvin reference at the victim device.
- Random resets: VDD droop or UVLO chatter during dv/dt edges → correlate reset count with dv/dt edge timing.
- Isolator output toggles: secondary reference shift via parasitic coupling → compare output behavior vs local decoupling placement.
- Works at light load, fails at load step: rectifier/secondary loop di/dt + insufficient local energy → monitor VDD dip during step + dv/dt.
Card B · Pass criteria (define PI robustness under dv/dt)
Rule: criteria must define where referenced (Kelvin vs system ground) and when counted (dv/dt event window). Placeholders X/Y/N are used for project-specific thresholds.
Voltage / reference criteria (during dv/dt event window)
- VDD dip: < X mV (measured at the victim device supply pins, Kelvin referenced)
- GND bounce: < Y mV (between victim ground and its Kelvin reference)
- UVLO chatter: 0 events / N stress cycles
System-visible criteria (no disguised failures)
- Reset count: 0 within Y minutes (or 0 / N stress cycles)
- Output toggles: 0 false transitions / N switching edges
- Error counters: no bursts correlated to dv/dt edges (counting window defined)
Power–signal co-design (dv/dt-focused tradeoffs)
Regulate → isolate: primary can be quieter, but parasitic coupling can still inject common-mode disturbance into the secondary reference.
Isolate → regulate: secondary can define a cleaner threshold reference, but requires strong local PI and deterministic startup behavior.
Decision basis: choose the path that keeps ΔVDD/ΔGND below threshold margin during dv/dt windows.
H2-10 · Verification: Test Setups, Probing Pitfalls, Stress Recipes
Card A · Measurement do/don’t (avoid self-inflicted glitches)
Purpose: ensure dv/dt injection is measured, not created by probing. The rules below make results repeatable and comparable.
Probe discipline (repeatable results)
- Do: use a short ground spring; avoid long ground leads that form an antenna loop.
- Do: use the same reference point for comparisons (Kelvin vs system ground must be explicit).
- Do: match probe bandwidth and scope sample rate to the expected glitch width (do not under-sample).
- Don’t: measure Vgs or VDD relative to a remote ground (turns ground bounce into “signal”).
- Don’t: change the probing geometry between runs (loop area changes the observed spike).
Stress methods (ordered by implementability)
- Double pulse: controlled dv/dt + di/dt event reproduction for gate/energy metrics.
- Switch-node step injection: isolate dv/dt as an input stimulus and observe logic/PI crossings.
- Common-mode injection: system-level disturbance reproduction for end-to-end robustness.
Card B · Stress matrix (corners + metrics + counting rules)
Purpose: prevent “one good run” from hiding corner failures. The matrix defines stress corners and outputs for every run.
Stress corners (combine systematically)
- VIN: low / nominal / high
- Temperature: cold / room / hot
- Load: light / nominal / peak + load-step
- dv/dt class: A / B / C (rise and fall tested)
- Repetition: event rate / switching frequency corner
Metrics (must include window + counting)
- Glitch amplitude/width: < X mV / < Y ns (window defined)
- False edges: 0 / N switching edges
- Reset count: 0 within Y minutes (or 0 / N cycles)
- Protection triggers: 0 spurious trips (counted and timestamped)
- Correlation: events must be correlated to dv/dt edges, not to probe artifacts
H2-11 · Engineering Checklist (Design → Bring-up → Production)
A stage-gated checklist that turns dv/dt injection control into measurable actions: close the unintended loop, harden the threshold, and prove it under stress before production.
Design Gate — “Make dv/dt injection paths hard to exist”
- Gate loop compact: driver OUT → gate resistor → gate → Kelvin source/emitter return (no sharing with power loop).
- Power loop compact: half-bridge commutation loop minimized; keep di/dt loop away from logic/isolator nodes.
- Barrier keepout: no copper “plate area” across the isolation gap; avoid accidental capacitance (Cbarrier growth).
- Return-path discipline: any fast edge line must have tight-coupled return; forbid “across-gap return”.
- Miller clamp footprint: internal or external clamp option. Examples (driver family): UCC21750, ISO5852S-Q1, ADuM4135, Si823x.
- Rg split option: separate Rg(on)/Rg(off) pads to tune dv/dt and ringing without respin.
- Gate clamp footprint: TVS/Zener footprint reserved (V rating must match gate limit). Example TVS family: SMBJ15A-E3/52 (illustrative).
- Negative off option: provision for VEE (−2 to −5 V class) if dv/dt risk is high.
Ordering note: part numbers may require package/grade suffix (e.g., -Q1, tape/reel codes).
- Input RC + clamp: pads for R/C close to isolator input; enforce a defined glitch-width rejection window.
- Schmitt / filter decision: if edges must be preserved, select isolators with robust thresholds and defined behavior.
- Fail-safe defaults: define output state at UVLO/power-down (documented and testable).
- Example isolators (control/logic): ISO7721 (robust EMC class), ISO6721-Q1 (cost-sensitive automotive grade).
- Local decoupling placement: dedicated high-frequency caps at driver VDD/VEE pins; shortest return.
- Bias transformer / module option: reserved footprint for either a module or a transformer-driver solution.
- Examples (bias): SN6505B (transformer driver), UCC25800-Q1 (ultra-low-EMI transformer driver), NXE1S0505MC (isolated 1 W module).
- CM injection control: minimize primary-secondary capacitance (Cps) and keep rectifier current loops compact.
Bring-up Gate — “Prove one hypothesis at a time”
- Step 1: loop closure — verify the “unwanted CM loop” path is small (layout sanity + return reference checks).
- Step 2: gate node — measure Vgs(off) peak & ringing under worst dv/dt; enable/disable clamp knobs to isolate cause.
- Step 3: isolator threshold — inject dv/dt step while holding input steady; watch for false edges at isolator output.
- Step 4: bias integrity — correlate VDD dips with false switching/resets; separate power-origin vs signal-origin faults.
- Vgs(off) peak < X V during dv/dt event; false turn-on count = 0 over Y pulses.
- Isolator output glitch: amplitude < X mV and/or width < Y ns; no latch-up; no unintended state retention.
- Bias dip: ΔVDD < X mV during dv/dt; reset count = 0; UVLO events logged = 0.
- Thermal corner: above criteria hold at Tmin/Tmax, Vin min/max, and load min/max.
- Use short ground spring / coax reference; avoid long probe ground leads.
- Define a single reference point per measurement (no floating “GND” ambiguity).
- Bandwidth & sampling must match the expected glitch width (Y ns class).
- Log counters: false edges, resets, DESAT/SC trips, UVLO events (with time correlation).
Production Gate — “Make dv/dt robustness auditable”
- Golden test recipe: dv/dt stress condition set (pulse count, corner matrix, temperature points).
- Acceptance report: measured Vgs(off) peak, isolator output glitch stats, bias dip stats, trip counters.
- Traceability: PCB rev, assembly process, conformal coating/slot usage, and isolation documentation pack.
- Sampling plan: incoming sample + periodic audit (same recipe, same pass/fail thresholds).
- Ferrite bead options (signal/bias noise shaping): BLM18AG601SN1D, MPZ2012S601A (illustrative).
- Fast diode option (gate network steering/clamp helper): BAS316,115 (illustrative).
- Isolated comm ports (field/drive environments): ISO1042BDWVR (isolated CAN), ISO1410DWR (isolated RS-485).
Voltage/current ratings must be re-checked against the project’s gate limit, bus fault level, and isolation class.
H2-12 · Applications & IC Selection Logic (and Quick Pairings)
Selection logic stays at “device family + measurable thresholds”. Part numbers below are example BOM-ready references aligned to dv/dt injection risk (not a catalog).
Application Buckets → Mandatory dv/dt Thresholds
- Target: dv/dt class ≥ 50–150 kV/µs (and higher, project-defined).
- Gate driver must support strong turn-off control (clamp / split outputs / active protection).
- Bias solution must minimize Cps-driven CM injection.
- Emphasis: robust CMTI (both polarities), repeatable UVLO/fail-safe behavior.
- Field wiring and ground bounce make “logic threshold hardening” non-negotiable.
- Emphasis: immunity of the measurement path under dv/dt; avoid “measurement glitch becomes control fault”.
- Prefer architectures that isolate the modulator/bitstream directly across the barrier when appropriate.
- Emphasis: deterministic fail-safe state and bus-fault robustness (dv/dt + wiring faults).
- Power + signal isolation must be co-designed (bias dips often masquerade as “protocol errors”).
Device Family Mapping (with example part numbers)
- Single-channel, reinforced, high-power: UCC21750 (active protection class).
- Split outputs + DESAT/active protection: ISO5852S-Q1 (example orderable: ISO5852SQDWRQ1).
- Dual-channel (half-bridge), reinforced: UCC21520 / UCC21530 (dead-time/EN pin options by variant).
- Miller clamp class (single-channel): ADuM4135 (Miller clamp feature class).
- Dual isolated driver family: Si823x (example device: Si8233AB-IS family).
- Robust EMC + reinforced: ISO7721 (example orderable: ISO7721QDRQ1).
- Cost-sensitive automotive dual-channel: ISO6721-Q1 family.
- When needed: add input RC + defined glitch-width rejection (board-level).
- Isolated amplifier with ΔΣ modulator output: AMC1311 family (bitstream across barrier class).
- Isolated Σ-Δ modulator: AD7401A family.
- Isolated CAN (bus fault robust): ISO1042 (example orderable: ISO1042BDWVR).
- Isolated RS-485/RS-422: ISO1410 (example orderable: ISO1410DWR).
- Transformer driver (low-noise class): SN6505B.
- Ultra-low EMI bias transformer driver: UCC25800-Q1.
- Isolated DC-DC module (fast integration): NXE1S0505MC.
- Ferrite beads: BLM18AG601SN1D (0603), MPZ2012S601A (0805).
- TVS clamp (voltage must match): SMBJ15A-E3/52.
- Fast diode: BAS316,115.
These helper parts are examples for footprint planning; electrical values must be reselected per gate rating and measured waveforms.
Quick Pairings (dv/dt-first combinations)
- Gate driver: UCC21750 or ISO5852S-Q1 (split outputs + active protection).
- Control isolator: ISO7721 class + board-level input deglitch if needed.
- Bias: UCC25800-Q1 (low CM injection) + tight secondary decoupling.
- Pass focus: Vgs(off) peak & false turn-on count = 0 at the worst dv/dt corner.
- Dual driver: UCC21520 / UCC21530 (half-bridge control).
- Comm isolation: ISO1410DWR (RS-485) or ISO1042BDWVR (CAN).
- Bias: SN6505B class + minimized transformer Cps + local LDO/RC staging if required.
- Pass focus: no resets/false edges during stress matrix; fail-safe states remain deterministic.
- Isolated sensing: AMC1311 or AD7401A (bitstream isolation class).
- Control side: ensure digital filtering window does not mask true faults (define X/Y/N thresholds).
- Pass focus: glitch amplitude/width stats remain below thresholds under dv/dt events.
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H2-13 · FAQs (10–12) — dv/dt Injection & Protection
Only field troubleshooting & acceptance criteria are covered. Each answer uses a fixed 4-line format: Likely cause / Quick check / Fix / Pass criteria with numeric placeholders (X/Y/N).
CMTI spec looks high, but false turn-on still happens—what was missed first?
Likely cause: Displacement current closes through the gate/reference loop; Kelvin return is not enforced, so Vgs(off) crosses an effective threshold.
Quick check: Measure Vgs(off) at the device using Kelvin source/emitter as reference; map the unintended CM current return path around the barrier.
Fix: Shrink gate loop + enforce Kelvin source/emitter return + enable/strengthen Miller clamp; reduce copper/area that increases barrier coupling.
Pass criteria: Vgs(off) peak < X V and false turn-on events = 0 over Y stress cycles (dv/dt class = X1 kV/µs placeholder).
Scope shows a huge gate spike—could it be a probing artifact?
Likely cause: Long ground lead or wrong reference point converts ground bounce into an apparent “gate spike”.
Quick check: Re-measure using ground spring or differential probe; move reference to Kelvin source/emitter; keep identical bandwidth and geometry.
Fix: Standardize probing method (short return, fixed reference point) and re-baseline all acceptance thresholds using the same setup.
Pass criteria: Artifact reduction ≥ X% and residual Vgs(off) peak < Y V (same bandwidth and same reference definition).
Works at low bus voltage, fails at high bus voltage—why?
Likely cause: dv/dt increases with Vbus and edge speed; displacement current scales up and the same loop impedance produces larger threshold crossings.
Quick check: Compare measured dv/dt (V/ns) at low vs high Vbus; correlate error/false events with dv/dt edges and repetition rate.
Fix: Gate shaping (split Rg on/off) and/or stronger off clamp; if needed, introduce limited negative off bias while protecting thermal budget.
Pass criteria: Error/false event count ≤ X per hour at Vbus = Y V and dv/dt = Z kV/µs (worst-polarity tested).
False turn-on appears only at hot—what changed?
Likely cause: Threshold/drive strength shifts and timing margins shrink at temperature; bias dips and ground bounce often worsen under hot conditions.
Quick check: Log VDD dip (Kelvin) and Vgs(off) peak vs temperature; correlate with false event timestamps under identical stress.
Fix: Improve local decoupling and PI (short loops, local regulation/RC staging); retune gate network for hot corner while preserving off clamp.
Pass criteria: VDD dip < X mV and Vgs(off) peak < Y V at T = Z °C; false events = 0 over N cycles.
Adding a Miller clamp helped, but EMI got worse—what knob to turn?
Likely cause: Clamp changes the gate impedance trajectory, exposing loop resonance and increasing ringing energy in a sensitive band.
Quick check: Compare ringing frequency and overshoot before/after clamp with identical probing; check if EMI rise correlates with the same ringing mode.
Fix: Add damping (Rg tuning, optional small series ferrite on gate) while keeping off-clamp; verify loop geometry remains compact.
Pass criteria: Overshoot < X% and false events = 0 over Y cycles, while project EMI margin degrades by ≤ Z dB (project band defined).
Controller resets when switching starts—signal issue or power issue?
Likely cause: Common-mode current shifts the control-side reference, causing VDD dip or reset pin threshold crossing (power integrity origin).
Quick check: Measure controller VDD transient and reset pin behavior with the controller’s local ground reference; correlate with dv/dt edges.
Fix: Harden supply (local LDO/RC staging, shorter decoupling loops), enforce return discipline, and reduce barrier coupling area if layout permits.
Pass criteria: Reset count = 0 over Y start/stop cycles and VDD dip < X mV in the dv/dt event window.
Isolator output chatters during switching—first suspect input or output side?
Likely cause: Input threshold is crossed by an injected glitch or reference bounce; chatter is typically triggered at the receiver threshold.
Quick check: Add a temporary RC at the isolator input (close placement) and repeat the same dv/dt stress; if chatter disappears, input-side hardening is indicated.
Fix: Implement permanent deglitch (RC/Schmitt strategy) and correct return path/layout to reduce injected glitch magnitude.
Pass criteria: Chatter count = 0 and any residual glitch width < X ns under dv/dt = Y kV/µs (worst polarity).
Negative gate bias fixes false turn-on, but driver runs hotter—why?
Likely cause: Stronger sink currents and larger gate-charge swing increase driver dissipation; negative bias also increases bias supply load.
Quick check: Compare driver supply current and case temperature with/without negative bias at identical switching frequency and dv/dt corner.
Fix: Reduce negative bias magnitude to the minimum needed; retune Rg(off) and clamp strategy; improve thermal path and local decoupling.
Pass criteria: Driver temperature rise < X °C at f = Y kHz and false events = 0 over N cycles.
Same PCB, different builds: one fails dv/dt immunity—what’s the first normalization?
Likely cause: Assembly variance changes parasitics (lead inductance, placement offsets, copper voids), altering loop impedance and threshold crossing behavior.
Quick check: Photo-audit critical placements against golden sample (gate resistor/clamp/decaps/Kelvin return); compare Vgs(off) and VDD dip using identical probing.
Fix: Tighten placement tolerances, define inspection checkpoints, and add keepouts/constraints that prevent accidental loop expansion.
Pass criteria: Build-to-build failure rate < X% over N samples and false events = 0 in the defined stress recipe.
Glitch exists but doesn’t always cause failure—how to set acceptance?
Likely cause: Failure occurs only when the glitch crosses a threshold inside a vulnerable timing window; outside that window it remains harmless.
Quick check: Measure glitch amplitude and width at the victim node with correct reference; compare to threshold margin and filter/blanking window.
Fix: Increase margin (threshold/RC deglitch) and/or reduce glitch at the source (loop shrink, damping, clamp strategy).
Pass criteria: Glitch amplitude < X mV and width < Y ns with margin > Z% at worst corner; false events = 0 over N cycles.
Soft turn-off reduces stress but increases shoot-through risk—what to verify?
Likely cause: Slower turn-off extends the overlap window; dead-time/mismatch is no longer sufficient at worst temperature and bias corners.
Quick check: Under worst dv/dt and temperature, measure Vgs overlap window (or shoot-through proxy such as DC-link current spike) with fixed reference and identical bandwidth.
Fix: Retune Rg(off) and clamp strategy to shorten the tail while maintaining immunity; adjust dead-time only after confirming gate waveforms and thresholds.
Pass criteria: Shoot-through proxy events = 0 over Y cycles and overlap window < X ns at the defined worst corner.
Adding a Y-cap improved EMI, but dv/dt-related glitches increased—why?
Likely cause: Y-cap increases common-mode displacement current; the return path causes larger ground bounce or threshold crossings on the control/isolator side.
Quick check: Compare VDD dip and reference bounce with Y-cap populated vs removed under identical dv/dt stress; correlate glitch count to dv/dt edges.
Fix: Reduce/relocate Y-cap, shrink return loop area, and add input deglitch where needed; minimize barrier coupling area that amplifies CM injection.
Pass criteria: Glitch count = 0 over Y cycles and ΔVDD/ΔGND < X mV while meeting project EMI margin ≥ Z dB (project band defined).
Note: X/Y/N placeholders must be filled with project-specific limits and must specify measurement reference (Kelvin vs system ground) and counting window (ns/cycles/minutes).
