Density & Viscosity Meter: Vibration AFE and Phase/Frequency Engine

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Core idea: A modern density/viscosity meter is an evidence-driven vibration measurement system—pickup AFE + phase/frequency engine + AGC + temperature compensation—whose accuracy is proven by measurable diagnostics (lock, clipping, drift, CRC, event logs), not by “magic coefficients.”

What this page gives you: a practical block-level design map and a field-debug evidence chain so stable frequency/phase metrics can be turned into reliable density/viscosity outputs in real industrial environments.

H2-1. Page Mission and Reader Contract

Purpose: Build a modern density/viscosity meter around a vibration sensor front-end and a phase/frequency measurement engine, then prove correctness using an evidence chain (waveforms, counters, status flags, and logs). The focus is electronics and validation—not fluid chemistry, piping, or process recipes.

Core idea: Convert “density/viscosity uncertainty” into a set of measurable signals—f (resonance), phase, damping/Q proxies, temperature, and health indicators—then constrain every design decision to what protects these measurements.

Who this page is for

Instrumentation HW/FW engineers needing an implementation-ready signal chain (AFE → demod/PLL → compensation → diagnostics → industrial comms).
IC buyers evaluating feasibility, risk, and integration effort (noise, drift, lock behavior, isolation, comms robustness).

What this page delivers (engineer-grade outputs)

Reference block diagram Measurement & diagnostics checklist Signal-chain validation plan

Evidence-first acceptance criteria

Frequency is stable with a known timebase error bound (e.g., lock flag + variance + cycle-slip counter).
Phase is measured with known latency/phase-offset controls (I/Q offsets, quadrature balance, sampling alignment).
Damping/Q proxy is separated from saturation artifacts (AGC effort saturation %, clipping flags, overload recovery time).
Temperature compensation is versioned and CRC-protected (coeff revision, LUT/polynomial ID, NVM integrity flag).
Field diagnostics translate failures into actionable logs (lock loss, clipping, comm CRC counters, thermal events).

Scope boundary (keeps the page vertical and deep)

Included: vibration pickup AFEs, drive/AGC, I/Q demod or PLL/DPLL tracking, temperature compensation, calibration NVM strategy, diagnostics, 4–20 mA/HART/RS-485 with isolation.
Excluded: fluid chemistry models, installation/process constraints, full Coriolis mass-flow algorithm deep dive, compliance clause-by-clause legal interpretation.

Figure H2-1 — Reference signal chain with required evidence taps (flags/counters/logs). Minimal text; box-diagram style for mobile readability.

Cite this figure

Suggested caption: “Meter electronics signal chain and evidence taps (AFE + phase/frequency engine + compensation + industrial I/O).”

H2-2. Working Principles You Must Not Confuse

This chapter pins down the physics → signals mapping that drives electronics decisions. Density/viscosity meters become reliable only when every “process question” is translated into measurable observables and defended against electronic artifacts (timebase drift, phase delay, saturation, EMI coupling).

2.1 Common architectures (crisp, correct, and electronics-oriented)

Vibrating element density meters (tuning-fork / vibrating tube): density primarily shifts the resonance frequency f₀. Viscosity often appears as increased damping (lower Q), forcing higher drive power to maintain amplitude and changing decay behavior.

Coriolis-style vibrating tubes (context only): density can still be tied to resonance behavior, while pickoff-to-pickoff phase differences demonstrate why high-integrity phase measurement and latency control matter. (Full mass-flow algorithm details belong elsewhere.)

Oscillatory inline viscometers: viscosity correlates strongly with damping proxies (Q, ring-down time, and AGC control effort) and with phase lag between excitation and pickup.

Rule of thumb: Treat frequency f as the most robust “primary” observable for density. Treat damping/Q proxies as the practical route to viscosity—then prove the proxy is not being polluted by saturation, drift, or EMI.

2.2 What the electronics actually measures (primary vs derived, plus failure signatures)

Frequency / period (primary): The electronics measures resonance as a frequency or period output from zero-cross timing or a tracking loop (PLL/DPLL). The dominant “fake error” source is the timebase: clock drift directly biases frequency readout. The evidence chain should include lock status, cycle-slip counters, and frequency variance to distinguish real resonance shifts from tracking instability.

Phase (primary or supporting): Phase can be measured between drive and pickup (single pickup) or between two pickups (dual pickoff). The dominant “fake error” source is latency/phase delay inside analog filters, ADC timing, and digital filtering. Therefore phase measurement must publish diagnostic fields such as I/Q offset, quadrature imbalance, and phase variance rather than only a final phase number.

Amplitude / Q / damping proxies (derived, viscosity-facing): Viscosity is commonly inferred via damping-related observables such as ring-down decay time, Q estimation, or AGC (amplitude loop) control effort. These are powerful but fragile: the first corruption mechanisms are clipping, overload recovery, and control saturation. A robust design exposes AGC headroom and saturation percentage so a “viscosity drift” complaint can be separated into “real damping change” vs “loop artifact.”

Temperature (mandatory companion): Temperature affects the resonator material properties (f₀ drift), pickup sensitivity, AFE leakage/offset, and the timebase. This means temperature compensation must be engineered as a versioned model (LUT/polynomial ID) with CRC-protected coefficients. Without versioning and integrity flags, a stable-but-wrong output becomes un-debuggable.

Health diagnostics (proof of integrity): The meter should publish health indicators that convert field failures into evidence: pickup symmetry/correlation (dual pickup), loop stability/lock behavior (PLL/DPLL), saturation/clipping flags (AFE/ADC), and event logs (brownout, surge, overtemp). These allow fast triage: “unstable” becomes “cycle slips,” “jumping phase” becomes “quadrature imbalance,” and “drift” becomes “timebase/temperature coefficient mismatch.”

Evidence Table: what to publish so the system is provable

Frequency: f value + variance + lock flag + cycle-slip counter (separates real shifts vs tracking failure).
Phase: phase value + variance + I/Q offset + quadrature imbalance (separates process change vs latency artifacts).
Damping proxy: AGC effort + saturation % + clipping flag + overload recovery time (separates viscosity change vs loop artifact).
Temperature: sensor reading + model ID/version + coeff CRC status (separates real drift vs wrong coefficients).
Comms & robustness: CRC counters, timeouts, reset reasons, surge/OT event logs (separates measurement faults vs transport/power faults).

Figure H2-2 — A strict physics-to-signals mapping plus the main electronic artifacts that must be excluded by evidence fields.

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Suggested caption: “Physics-to-signals mapping for density/viscosity meters with primary observables and artifact categories.”

H2-3. End-to-End Block Diagram (Analog + Digital + Comms)

This chapter anchors the complete meter architecture so every later chapter maps to a block boundary and a measurable evidence tap. The system is organized as a closed-loop vibration instrument: excitation injects energy, the resonator converts process changes into mechanical observables, and the electronics converts those observables into provable numbers (frequency/phase/damping proxies) plus diagnostics.

Design rule: Each block must produce a field-verifiable output (flag/counter/log) that explains failures without guesswork—especially lock loss, clipping, coefficient mismatch, and comms faults.

Canonical stack (block boundaries stay stable across products)

Excitation: drive DAC/PWM → drive amplifier (H-bridge or linear).
Pickup sensing: piezo / electromagnetic / capacitive vibration sensors.
Pickup AFE: protection + biasing + low-noise gain + anti-alias + ADC.
Demod / timing: synchronous I/Q extraction or zero-cross timing.
Phase/frequency engine: PLL/DPLL, frequency counter, phase detector.
Amplitude control: AGC / constant amplitude regulation (stability + headroom).
Temperature channel: sensor + model-based compensation.
Calibration & NVM: coefficients, trims, versioning, history.
MCU/SoC: filtering, diagnostics, comms stack.
Industrial outputs: 4–20mA/HART, RS-485/Modbus, CANopen/IO-Link (as applicable).
Isolation + protection: digital isolators, surge/ESD, intrinsic safety barriers (if required).

Minimum evidence taps (publish these to keep the system provable)

CLIP / overload I/Q offset & quad LOCK & slips Freq/phase variance AGC effort & sat% Coeff ID & CRC CRC/timeouts Reset/surge/OT logs

Figure H2-3 — Canonical meter electronics stack with evidence taps. Box-diagram heavy, minimal labels, mobile-readable (≥18px).

Cite this figure

Suggested caption: “End-to-end block diagram for density/viscosity meter electronics with required evidence taps and isolation boundary.”

H2-4. Vibration Pickup Front-End (AFE) Design: Noise, Dynamic Range, Survivability

The vibration pickup AFE is commonly the limiting factor for meter accuracy because it defines the real SNR, the phase integrity seen by the tracking engine, and the system’s ability to remain valid during startup, shocks, and EMI. A robust AFE is designed around provable behaviors: controlled nonlinearity, predictable phase, recoverable overload, and measurable flags.

AFE target: Preserve the observables that feed density/viscosity computation—frequency stability, phase stability, and damping proxy integrity—while exposing clipping/overload indicators and recovery timing.

4.1 Sensor interface patterns (what the AFE must respect)

Piezo pickup: behaves like a charge/capacitive source. AFE choices (charge amplifier or very high-Z instrumentation front-end) are dominated by bias current and leakage, which turn into low-frequency drift and baseline wander that can leak into I/Q measurements and phase variance.

Electromagnetic pickup: produces a small differential voltage. The AFE must prioritize low input noise and high CMRR in the presence of strong common-mode interference. Grounding and cable ingress EMI are often the first failure causes for phase jitter and false lock loss.

Capacitive pickup: requires excitation and demodulation. It can be highly stable when properly guarded, but the AFE must control excitation feedthrough and switching artifacts that appear as I/Q offsets and harmonic contamination.

4.2 AFE “non-negotiables” (principles + measurable acceptance)

Input protection without measurement distortion: ESD/surge clamps must be placed so they do not inject nonlinear leakage into the measurement node. Acceptance: THD/IMD stays bounded and post-ESD offset/drift remains within spec.
Low-frequency stability (1/f matters): For baseband/low-IF I/Q, 1/f noise and bias drift translate into phase noise and I/Q bias. Acceptance: phase variance and I/Q offsets remain stable across time/temperature.
Anti-alias strategy with phase integrity: Filters set bandwidth and also impose group delay. Acceptance: phase output remains consistent across operating frequency range, and latency is predictable or calibratable.
Saturation observability: ADC clipping and amplifier overdrive must be detectable and loggable. Acceptance: clipping flag, overload counter, and overload recovery time are measurable under injected stress.

Validation checklist (evidence fields that connect directly to accuracy)

Input-referred noise: noise density + integrated noise in the measurement band → predicts frequency/phase jitter.
Linearity: THD/IMD near the resonant band → protects I/Q purity and stable phase estimation.
Overload behavior: overload recovery time + clip counters → prevents false viscosity trends from saturation artifacts.
Common-mode sensitivity: CMRR at key frequencies + phase variance under CM injection → prevents EMI-driven phase jitter.

Figure H2-4 — AFE box diagram with key artifact injection points (LEAK / 1/f / DELAY / CLIP) and validation metrics.

Cite this figure

Suggested caption: “Vibration pickup AFE blocks, artifact tags, and evidence metrics (noise/linearity/recovery/CMRR).”

H2-5. Drive Path + Amplitude Control Loop (AGC): Keeping the Resonator “Honest”

The drive path must excite the resonator without injecting measurement bias. In practice, the dominant risks are spurs that fold into the measurement band, overdrive that changes the apparent damping proxy, and startup transients that create false lock/false viscosity trends. A correct architecture makes these risks observable via flags, counters, and loop telemetry.

Drive/AGC rule: Maintain a comparable vibration state (amplitude + spectral purity) while publishing loop evidence: setpoint, control effort, saturation time, time-to-lock, and loop error RMS.

5.1 Drive methods (selection depends on spur risk and efficiency)

Sinusoidal drive (DAC + linear amp): clean spectrum and predictable phase; simplifies demod and reduces spur-driven phase jitter. Primary risks are thermal drift and soft limiting under headroom loss.
PWM/ΣΔ + filter: high efficiency, but switching spurs can leak or mix into the baseband/IQ path. Requires a filter strategy that controls both attenuation and phase delay consistency.
H-bridge resonant drive: efficient for higher power; switching artifacts and asymmetry (dead-time, mismatch) can introduce harmonic content that contaminates phase and damping proxies.

5.2 AGC / constant amplitude loop (what is controlled, what can go wrong)

Control variable: AGC can regulate drive amplitude, drive power/current, or an in-loop amplitude estimate. The most stable approach is to regulate an amplitude estimate that is aligned with the measurement engine (I/Q magnitude or envelope), while exposing estimate quality indicators to avoid silent bias.

Stability constraints: loop bandwidth must respect resonator Q and the measurement update rate. Too-fast AGC injects amplitude ripple and phase disturbance; too-slow AGC allows amplitude drift that pollutes damping proxies and long-term trends. Startup and reacquire behavior must be explicitly bounded by clamps and logged timing.

Diagnostics to log (required evidence fields)

AGC setpoint Control effort SAT time CLIP count t_lock Loop error RMS Reacquire count Spur proxy

Figure H2-5 — Drive method options with an AGC feedback loop and required evidence taps (spur proxy, effort/sat, clip, t_lock).

Cite this figure

Suggested caption: “Drive/AGC architecture for resonator excitation with spur and saturation observability.”

H2-6. Phase/Frequency Engine Options: What to Choose and Why

The phase/frequency engine converts pickup waveforms into frequency, phase, and amplitude observables that feed density/viscosity computation. Selection must match hardware reality: waveform purity, noise level, timebase quality, available compute, and the need for field diagnostics. A correct implementation produces numbers plus confidence evidence (variance, lock status, offsets, slip counters).

Selection rule: Clean waveform + low compute → Zero-cross. Noisy environment or phase needed → I/Q demod. Strong tracking + diagnostics → PLL/DPLL (often combined with I/Q).

Option A: Zero-cross timing + digital filtering

Pros: simple implementation and minimal compute. Cons: sensitive to noise and waveform distortion; phase accuracy is limited by delay and threshold behavior. Required evidence: period jitter estimate and outlier-rejection counters to detect noise-driven timing errors.

Option B: I/Q demodulation (lock-in style)

Pros: robust in noise; clean amplitude and phase extraction. Cons: requires a coherent reference and DSP resources; susceptible to I/Q offsets and quadrature imbalance if not monitored. Required evidence: I/Q offsets, quadrature error proxy, and amplitude/phase variance.

Option C: PLL/DPLL-based tracking

Pros: smooth frequency output and strong diagnostics (lock status, reacquire timing, slip counts). Cons: loop dynamics must be tuned; bandwidth misconfiguration can follow noise or lag real changes. Required evidence: lock flag, cycle-slip counter, reacquire time, and loop mode ID.

Minimum evidence fields (engine-level observability)

Jitter / variance I/Q offsets Quad error LOCK flag Slip count Reacquire time Loop mode ID

Figure H2-6 — Three engine options (ZC, I/Q, DPLL) mapped to required evidence fields (jitter, offsets, lock/slips/reacquire).

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Suggested caption: “Phase/frequency engine selection with observability fields for field validation and debugging.”

H2-7. Temperature Compensation and Drift: Model, Sensors, and Calibration Strategy

Temperature compensation must be engineering-first: identify every temperature injection path, choose sensors based on stability and thermal coupling, and implement a calibration plan that keeps electronics calibration separate from process calibration. A robust design also treats coefficients as audited assets with versioning, CRC, and protected “golden factory” data.

Compensation contract: Publish raw vs compensated observables, a model/version ID, and at least one residual/quality indicator so drift can be distinguished from true media change.

7.1 Where temperature enters (injection paths + what gets biased)

Resonator material properties

Primary source of frequency drift (f vs T). Can also reshape Q/damping proxies and create hysteresis between heating/cooling trajectories.

Pickup sensitivity drift

Changes amplitude estimate and SNR. Typical symptom: AGC effort and phase variance change with temperature at constant media.

AFE offset / bias drift

Shifts I/Q offsets and raises low-frequency noise. Can mimic viscosity changes unless I/Q offsets and variance are observable.

Clock drift (timebase)

Biases absolute frequency readout and long-term stability. Must be tracked via timebase mode ID and self-check/error proxies.

7.2 Compensation architecture (sensor → model → calibration layers → audited NVM)

Sensor choice: PT100/1000 (stability, needs analog front-end), NTC (cost, nonlinearity and aging), or silicon temperature sensor (integration, thermal placement dominates). Target is repeatable coupling to the resonator temperature rather than best datasheet accuracy.
Model structure: polynomial (simple but risky outside range), piecewise-linear (controlled, production-friendly), or LUT (strong but requires strict version/CRC). Add hysteresis handling when heating/cooling paths differ.
Calibration plan: factory multi-point for electronics domain (sensor + AFE + timebase), plus optional field trim overlay. Keep sensor/electronics calibration separate from process/media calibration so field updates do not destroy traceability.
NVM layout: coefficient versioning + CRC; protected “golden factory” region plus field overlay region; wear leveling if updates are frequent; expose which region is active and whether CRC passed.

Minimum evidence fields (drift must be diagnosable)

raw f/φ vs T comp f/φ model ID coeff version CRC OK residual I/Q offset timebase ID

Figure H2-7 — Temperature injection paths mapped to sensor/model choices, calibration layers, and audited NVM (version + CRC).

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Suggested caption: “Temperature compensation architecture with traceable coefficients and diagnosable drift paths.”

H2-8. Signal Conditioning Pipeline: From Raw Metrics to Stable Density/Viscosity Outputs

A reliable density/viscosity output requires a conditioning pipeline that is explicit about what it rejects, what it smooths, and what latency it introduces. The pipeline must expose engineering truth: update rate, group delay, and step response time constant, along with validity flags that prevent silent “pretty numbers” when the signal chain is compromised.

Pipeline contract: Provide raw vs filtered f/φ metrics, filter mode/state, and a latency estimate so field data can be interpreted correctly.

Typical pipeline (what each stage prevents, and what it costs)

Outlier rejection (spike guard): blocks EMI spikes and clip-induced jumps; must publish outlier counters and rejection ratio to avoid hidden freezes.
Decimation: reduces compute/bandwidth; must declare effective update rate and prevent aliasing when decimating phase/frequency streams.
Moving average vs IIR: MA offers predictable group delay; IIR offers shorter delay but requires a declared time constant and stable step response behavior.
Temperature compensation stage: apply on raw observables or post-filter depending on noise/lag trade; must expose compensated vs uncompensated metrics.
Density/viscosity computation: uses a declared model/version; should publish minimal feature vector proxies and validity checks.
Output shaping: rate limit, alarm thresholds, and hold-last-value behavior; must publish status and invalid-data flags for industrial outputs.

Do not hide latency (engineering truth)

Update rate

Output refresh frequency after decimation and smoothing; must be explicitly published (Hz).

Group delay

End-to-end delay introduced by filters and windowing; publish estimated delay (ms).

Step response time constant

Time to reach 63% (or 90%) after a step; publish effective time constant (ms/s).

Validity rules

Invalid-data flags, hold-last-value, and alarm states must be surfaced to prevent silent bias.

Evidence fields (minimum set for debugging)

raw f/φ filtered f/φ outlier count filter mode ID filter state latency est update rate invalid flags

Figure H2-8 — Conditioning pipeline with explicit latency (update rate, group delay, step τ) and mandatory evidence fields.

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Suggested caption: “DSP pipeline for stable density/viscosity output with published latency and validity evidence.”

H2-9. Self-Test, Diagnostics, and “Evidence Chain” for Field Debug

Field failures must be converted into measurable facts. A density/viscosity meter should expose a compact evidence chain: loop vital signs, signal-path health, pickup integrity indicators, and audited configuration/state. This prevents “stable but wrong” outputs and enables short, repeatable debug actions.

Evidence-chain rule: Every measurement output must be accompanied by status flags, counters, and at least one trend proxy so failures are diagnosable without disassembling the instrument.

Must-have diagnostics (minimum implementation set)

Loop vital signs

PLL/DPLL lock status; lock-lost count; reacquire time; cycle-slip count; AGC error RMS; saturation %; clip/overload flags.

Amplitude-loop margin proxy

Error RMS and control-effort distribution; clamp-hit counters; time-to-lock; loop-mode ID for consistent interpretation.

Pickup symmetry / health

Dual-pickup correlation score; gain mismatch indicator; phase consistency check; imbalance flags for mechanical or wiring faults.

Sensor faults + drift

Open/short detection; bias/leakage drift proxy; temperature sensor ID/config mismatch; I/Q offset drift indicators.

Event log (what happened, when)

Brownout/reset reason codes; surge/ESD hit counters (if supported); overtemperature events; watchdog resets; comms fault bursts.

Traceability / configuration audit

Coefficient version + CRC; active bank (factory/field overlay); write count; model ID; timebase ID; firmware build ID.

Field debug playbook (short and actionable)

No reading / unstable: check LOCK first, then SAT/CLIP, then noise/outlier ratio. A non-locking engine is not a measurement; resolve drive/AGC/timebase before interpreting density/viscosity.
Wrong density but stable: suspect coefficient version, NVM CRC, active bank, or sensor ID mismatch before chasing noise. A stable but incorrect number is usually configuration/traceability failure.
Viscosity drift over days: separate contamination/mechanics vs electronics drift using trends: rising drive effort/power and changing pickup gain/correlation points to contamination/structural change; rising I/Q offsets or phase variance points to electronics/thermal coupling.

Evidence fields (minimum readout set)

LOCK SLIP cnt t_reacq SAT% CLIP cnt err RMS corr score gain mismatch event log coeff ver CRC OK active bank

Figure H2-9 — Evidence-chain layers mapped to symptom-driven field debug actions and traceability audit (version/CRC/bank).

Cite this figure

Suggested caption: “Field diagnostics evidence chain and short playbook for measurable debugging.”

H2-10. Industrial Communications and Output Stage: 4–20mA, HART, RS-485 (and Isolation)

Industrial interfaces must preserve measurement integrity in the presence of long cables, ground shifts, EMC, and transient events. The output stage should therefore be designed as an integrity-preserving boundary: fault detection, error counters, isolation strategy, and controlled noise coupling back into the analog front-end.

Integrity rule: Every output path must expose error counters and fault flags, and isolation power must be engineered so switching noise cannot silently corrupt AFE metrics.

10.1 Output patterns (constraints + failure modes + what must be detectable)

4–20mA current loop

DAC/current driver + compliance voltage budgeting + loop open/short detection. Required observability: compliance margin, DAC saturation, driver OT, loop current error.

HART overlay (on 4–20mA)

Analog path linearity and impedance must support modem coupling without distorting the loop signal. Required observability: frame errors (or SNR proxy), modem status, analog saturation flags.

RS-485 / Modbus

EMC and grounding dominate reliability. Isolation placement and TVS/CM choke choices affect both robustness and noise return. Required observability: CRC error counters, timeouts, frame errors.

(Optional) CANopen / IO-Link

Same integrity principles apply: isolation + EMC + counters. Keep implementation evidence consistent across protocols.

10.2 Isolation choices (digital isolation + isolated power, and noise return paths)

Digital isolation: isolate SPI/UART/RS-485 signals to tolerate ground shifts; choose devices and layout for high CMTI. Publish isolation fault flags and bus-level error counters.
Isolated power (flyback): switching ripple and parasitic capacitance can couple noise back into the measurement domain. Control the return path and publish isolated-rail UV/OV events and reset reasons.
Grounding strategy: separate measurement ground from noisy output ground, and define a single controlled reference path across the isolation boundary to avoid silent common-mode injection.

Evidence fields (communications + output integrity)

CRC errors timeouts frame errors loop open compliance margin DAC sat driver OT iso fault iso rail UV/OV

Figure H2-10 — Industrial outputs split by an isolation boundary, with noise-return awareness and mandatory error counters/flags.

Cite this figure

Suggested caption: “4–20mA/HART/RS-485 output integrity with isolation and observable comms/fault evidence.”

H2-11. EMC, Surge, Safety (Intrinsic Safety / SIL) — Without Breaking Measurement

EMC and safety design must be treated as a signal-integrity problem. The objective is twofold: survive ESD/EFT/surge and grounding disturbances, while keeping pickup phase, amplitude, and noise characteristics within the measurement error budget. The only credible proof is an evidence chain captured during compliance tests.

Rule of thumb: Put “big energy” protection at the cable/metal boundary (chassis reference), and keep the measurement front-end protected with minimal parasitics and observable quality indicators.

11.1 Surge/ESD protection partitioning (where clamps go without distorting pickup)

Cable ingress (energy dumping zone)

Prefer robust clamps to chassis/shield so surge current does not share the analog reference. This is where higher-capacitance parts are acceptable.

Measurement domain (precision zone)

Use low-leakage, low-capacitance protection and avoid nonlinear elements inside the pickup measurement bandwidth. Add clipping/saturation flags instead of “overprotecting” into distortion.

Comms/output domain (noisy zone)

Protect long interfaces (4–20mA, RS-485) aggressively; keep their return currents away from AFE ground. Add fault detection and counters for remote diagnosis.

What breaks measurement

TVS capacitance adds poles/zeros; clamp nonlinearity creates demod bias; CM/DM filters can add phase shift that corrupts phase engines.

11.2 Grounding strategy (analog ground vs chassis vs loop ground)

Separate references explicitly: define AGND (AFE/ADC/demod), CHASSIS (shield/PE/metal), and LOOP/FGND (field wiring return). Document which signals reference which ground.
Keep surge current out of AGND: route cable shield and protection returns to CHASSIS with short, low-inductance paths. Avoid sharing vias/planes with AFE reference.
Control where domains meet: if a single-point tie is required, place it intentionally (near ingress or an isolation boundary) and validate that burst/surge does not move the measurement baseline.
Make ground problems observable: log resets/watchdog events and correlate with comms CRC/timeouts and measurement quality indicators.

11.3 Cable ingress filtering (CM/DM filters and phase impact)

Common-mode (CM)

CM chokes and shield termination reduce EFT/ESD coupling. Validate that the choke does not resonate or saturate under surge/burst conditions.

Differential-mode (DM)

DM RC/LC filtering can improve robustness but may introduce group delay and phase distortion. This must be accounted for in phase/frequency engines.

Phase integrity checks

During EFT/burst, log phase variance, outlier ratio, and lock-loss count. A pass/fail without these fields is not measurement-safe.

Design for predictability

Prefer simple, well-damped networks; avoid “mystery resonances.” Use consistent reference planes and controlled return paths at the connector.

11.4 Intrinsic safety / SIL considerations (only when applicable)

Intrinsic safety is an energy budget: energy-limiting components (resistors, fuses, zeners/barriers) can reduce drive margin and change pickup loading. Validate lock time, saturation %, and measurement quality under the limited-energy configuration.
SIL-style observability (practical): treat “unsafe measurement” as a detectable state: lock loss, persistent clipping, or CRC failures must raise status flags and force a defined safe output behavior (e.g., hold + alarm).
Do not hide degradation: if EMI conditions force degraded mode, expose it with a quality indicator and event tags.

Evidence fields (what to capture during EFT/burst and surge)

surge cnt ESD/EFT tag reset reason watchdog cnt LOCK lost phase var outlier ratio corr score comms CRC timeouts

Example BOM (MPN examples commonly used in similar meters)

Note: Exact ratings depend on interface voltage, surge level, and insulation requirements; treat these as reference starting points and validate parasitics against the pickup bandwidth.

Function	Where used	MPN examples	Selection notes (measurement-safe)
Low-capacitance ESD diode	High-impedance pickup inputs / sensor leads	TI TPD1E10B06; Nexperia PESD1CAN; onsemi ESD9B5.0ST5G	Prefer low C, low leakage; keep outside the sensitive gain node when possible.
RS-485 TVS array	RS-485 A/B lines at connector	Semtech SM712; Littelfuse SM05 series (select per bus)	Place at ingress; return to chassis/quiet reference; verify failsafe behavior.
Higher-power TVS (surge)	Cable ingress / supply or loop interface	Littelfuse SMBJ33A, SMBJ58A (examples); Vishay SMBJ series	Use where energy is dumped; keep TVS capacitance away from pickup measurement nodes.
Gas discharge tube (GDT)	High-energy surge at ingress (as applicable)	Bourns 2038-xx-SM series	Good for large surge; coordinate with TVS/MOV to control follow current.
MOV (mains/field surge)	Supply/field wiring (when relevant)	Bourns MOV-14D series (example family)	Not for precision nodes; ensure proper derating and safety approvals.
Common-mode choke	Comms cable ingress (RS-485 / sensor cabling if needed)	Würth Elektronik 744232 series (example family)	Check resonance and saturation; validate phase impact if used near measurement signals.
Ferrite bead	Local filtering / segmentation	Murata BLM21 series (example family)	Use to steer HF currents; avoid creating unintended resonances with large capacitors.
Digital isolator	SPI/UART across isolation boundary	TI ISO7741; Analog Devices ADuM1401	Choose for CMTI; keep return paths controlled; log iso fault if available.
Isolated RS-485 transceiver	Robust Modbus/RS-485 node	TI ISO3082; Analog Devices ADM2587E	Reduces ground-shift issues; validate EMC with cable tests; expose CRC/timeout counters.
4–20mA loop transmitter	Analog current output stage	TI XTR115 / XTR116 / XTR117	Budget compliance voltage; implement loop open detect and DAC saturation flags.
HART modem IC	HART overlay on 4–20mA	Analog Devices AD5700 / AD5700-1	Maintain analog linearity/impedance; log frame errors and modem status.
Isolated power (flyback controller)	Isolation supply for comms domain	ADI LT8302; TI UCC28740 (flyback controller example)	Switching noise can couple back; measure Q-indicators during EFT/burst to prove safety.
eFuse / hot-swap (protection)	Supply segmentation / surge response	TI TPS2660 (example family)	Use event logs (fault, retry) to correlate with measurement disruptions.

Figure H2-11 — EMC and surge partitioning with explicit grounding domains and evidence fields to prove measurement integrity during EFT/burst.

Cite this figure

Suggested caption: “Measurement-safe EMC partitioning and evidence capture plan for density/viscosity meters.”

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H2-12. FAQs (Diagnostics-First, Evidence-Linked)

Each answer follows the same field-debug pattern: a short conclusion, what to measure (evidence fields), and a first fix. MPN examples are provided where the interface choice commonly affects robustness or measurability.

Mapping tags reference earlier chapters (H2-4…H2-11) so each FAQ points back to a specific evidence chain.

Frequency is stable but density is wrong—calibration model or timebase error?

H2-7 H2-6

Answer: A stable frequency with wrong density is usually a model/coeff bank mismatch or a timebase offset. Measure (1) timebase ID/ppm (or clock status) and (2) coeff model ID + version/CRC + active bank. First fix: validate the reference clock path, then reload the correct coefficient bank and model version before re-running multi-point calibration.

Phase jumps occasionally—pickup saturation or PLL cycle slip?

H2-4 H2-6

Answer: Phase spikes are most often caused by input clipping/overload or cycle slips in the tracking loop. Measure (1) ADC clip count / AFE overload flag and (2) slip count / lock-lost events with reacquire time. First fix: reduce pickup gain or drive amplitude to remove saturation, then retune PLL/DPLL bandwidth and slip detection thresholds.

Viscosity output drifts with temperature even after compensation—sensor placement or coefficient versioning?

H2-7

Answer: Residual temperature drift is usually temperature sensor placement (not tracking the resonator body) or wrong coefficient set. Measure (1) temperature channel ID/location and (2) coeff version/CRC and active bank, plus drift vs temperature slope after compensation. First fix: correct the sensor thermal coupling/placement, then enforce coefficient versioning with CRC and bank audit on boot.

Startup takes too long to lock—AGC bandwidth or resonator Q change?

H2-5 H2-6

Answer: Long lock time is commonly AGC/startup ramp tuning or a real Q decrease (contamination or mechanical change). Measure (1) time-to-lock and AGC error RMS/effort trajectory, and (2) drive power required to reach setpoint. First fix: adjust AGC bandwidth and startup slope, then investigate Q drop if drive effort trends upward across units.

Noise floor is fine in lab, bad in cabinet—cable ingress EMI or ground reference?

H2-11 H2-4

Answer: Cabinet noise is typically ingress coupling or ground reference movement. Measure (1) phase variance/outlier ratio correlation with cabinet switching events and (2) comms CRC bursts or reset reasons (ground bounce). First fix: improve shield-to-chassis termination and ingress CM filtering, then validate AFE CMRR and ensure noisy returns do not share the AFE reference plane.

4–20mA output is correct but comms drops—RS-485 isolation or burst susceptibility?

H2-10 H2-11

Answer: Correct loop current with comms drop points to RS-485 ingress/EMC or isolation supply instability under burst. Measure (1) CRC/timeouts during EFT/burst and (2) iso fault / isolated-rail UV events. First fix: harden RS-485 protection and CM filtering, then upgrade isolation robustness (e.g., ISO3082 or ADM2587E class) and verify counters remain flat in burst tests.

MPN examples: TI ISO3082; ADI ADM2587E; Semtech SM712 (RS-485 TVS).

After surge test, readings shift permanently—ESD clamp leakage into high-Z pickup?

H2-4 H2-11

Answer: A permanent shift after surge often indicates leakage or bias shift in high-impedance pickup protection or front-end biasing. Measure (1) pickup offset/bias drift proxy and I/Q DC offsets and (2) surge event count/time alignment with the shift. First fix: replace or relocate protection to the ingress zone and use low-leakage, low-capacitance parts at the pickup input; then re-baseline and recalibrate.

MPN examples: TI TPD1E10B06; Nexperia PESD1CAN (low-C ESD).

Stable density but viscosity becomes “sticky”—is the damping proxy computed wrong?

H2-8 H2-5

Answer: “Sticky” viscosity usually means the damping proxy (drive effort, decay time, or Q estimate) is filtered or temperature-compensated in the wrong order, or is being rate-limited. Measure (1) raw vs filtered damping proxy and (2) AGC control effort vs amplitude estimate consistency. First fix: define a single canonical proxy with clear units, then move filtering/compensation to a stable stage and tune rate limits to avoid bias.

CRC passes but device reports old calibration—NVM overlay vs golden region logic?

H2-7

Answer: If CRC is OK but calibration looks old, the issue is typically bank selection priority or an overlay commit rule, not data corruption. Measure (1) active bank ID and version monotonicity and (2) boot-time load log (which region was chosen and why). First fix: enforce deterministic selection (newest valid overlay wins), and make updates atomic with version increments before switching pointers.

Two pickups disagree—mechanical misalignment or AFE gain mismatch?

H2-4 H2-9

Answer: Disagreement between pickups should be separated with a swap test. Measure (1) correlation score and gain mismatch indicator and (2) whether the error follows the channel after swapping inputs. First fix: if it follows the channel, recalibrate AFE gain/offset and check wiring/connector integrity; if it follows the sensor position, investigate mechanical alignment, mounting stress, or contamination affecting one pickup path.

Lock is true but output oscillates—filter dynamics or control loop interaction?

H2-8 H2-5

Answer: True lock with oscillating output indicates filter group delay, rate limiting, or interaction between AGC and output shaping. Measure (1) filter state/latency estimate and (2) AGC error RMS periodicity aligned with output swings. First fix: reduce filter aggressiveness (lower Q, adjust cutoff), then decouple AGC and output smoothing time constants so only one loop dominates the visible dynamics.

How do I prove data quality to the customer?

H2-9 H2-10

Answer: Data quality is proven by exporting a compact quality report, not by asserting accuracy. Measure (1) quality indicators (lock, phase variance, outlier ratio, pickup correlation) and (2) traceability fields (coeff version/CRC, active bank, event log, comms error counters). First fix: publish these fields over the service interface and include them in EFT/burst test reports to demonstrate stability and recoverability under stress.

MPN quick list (common interface/robustness parts)

4–20mA transmitter: TI XTR115 / XTR116 / XTR117
HART modem: Analog Devices AD5700 / AD5700-1
Isolated RS-485: TI ISO3082; ADI ADM2587E
RS-485 TVS: Semtech SM712
Low-cap ESD for sensitive inputs: TI TPD1E10B06; Nexperia PESD1CAN

Ratings and footprints must be selected per voltage level, cable environment, and required approvals; validate capacitance/leakage against the pickup bandwidth and bias network.