Precision sampling across an isolation barrier is not “adding one isolator”—it is a closed loop of
clock jitter, AFE linearity, isolated power noise, partition/return paths, and
measurable validation gates.
The winning recipe controls coupling paths (Cbar/Y-cap/shield), budgets jitter+ripple+spurs end-to-end, and proves it with repeatable pass criteria.
ScopeSystem RecipeNo Cross-Topic Spillover
Definition & Scope Boundary
High-precision sampling across an isolation barrier is a system problem: accuracy is preserved only when
clock jitter, barrier coupling, isolated power noise,
and front-end drive errors are budgeted and validated together.
What this page answers
How to isolate clocks and power without killing SNR/ENOB (dominant degradation paths + fixes).
The system recipe for precision sampling across isolation (clock + AFE + power + partition + validation).
Where to start when results degrade (jitter vs ripple vs return-path coupling triage).
In-scope (must be covered)
System-level paths that degrade sampling fidelity after isolation:
Clock additive jitter / skew → wideband SNR loss and channel mismatch.
Isolated power ripple / leakage / return-path changes → spur maps locked to DC-DC tones and low-frequency drift.
AFE driver & protection nonlinearity → rectification spurs and sensitivity to input/common-mode sweeps.
Out-of-scope (explicitly not covered)
ADC architecture encyclopedias (SAR/ΔΣ). Only clock/sync requirements are referenced.
Protocol-specific implementation deep-dives (e.g., full JESD204 guides). Only timing budgets are referenced.
Isolator internal encoding/implementation details (owned by the dedicated clock isolator / device-class pages).
Fast boundary card: solves vs. does not solve
Solves: (1) identifies the dominant degradation path, (2) provides a budgeting workflow,
(3) defines validation gates and probe points.
Does not solve: (1) deep ADC internals, (2) isolator internal mechanisms,
(3) protocol-by-protocol bring-up manuals.
Scope map: this page focuses on the system recipe (clock + AFE + power), supported by
partition/return and validation gates. Device internals live in the dedicated subpages.
Core IdeaThree KnobsClosed Loop
Core Idea: Preserve Sampling Fidelity Across the Barrier
Precision sampling across isolation is preserved by a closed-loop design:
Clock sets the timing floor, Power shapes the noise floor,
and Return Path decides how common-mode energy becomes spurs.
Non-negotiable principles
Knob #1 — Clock first: sampling fidelity is often lost to additive jitter and multi-channel skew before any other error dominates.
Controls: ENOB/SNR at higher input frequencies, inter-channel coherence.
First moves: isolate at the right point in the clock tree; avoid multiple unsynchronized isolation points; budget skew early.
Knob #2 — Power–signal co-design: isolated power noise couples into references, front ends, and thresholds, creating spur patterns that look like “mystery” performance loss.
Measure first: spur map vs DC-DC enable/disable and load steps; reference noise at the ADC/AFE pins.
First moves: choose switching frequency bands away from sensitive FFT bins; post-regulate (LDO) and damp filter resonances; split rails (analog/digital/reference).
Knob #3 — Partition & return: the isolation barrier blocks DC conduction, not displacement currents; return-path decisions determine whether common-mode energy becomes input-referred error.
Controls: EMI-driven spurs, dv/dt sensitivity, “works on bench, fails near switching” behavior.
Measure first: spur sensitivity to switching events, shield bonding state, and Y-cap changes.
First moves: enforce primary/secondary partition; define a single intentional CM return (or none); use safety Y-caps sparingly and with leakage constraints.
How to use the three knobs (triage order)
Start with Clock when SNR/ENOB drops broadly (especially at higher input frequencies).
Start with Power when spurs align with switching frequency/harmonics or change with load.
Start with Return Path when errors appear only near high dv/dt switching, cable/shield states, or after adding Y-caps.
Three-knob model: Clock (jitter/skew), Power (ripple/spurs),
and Partition (return/CMTI) form a closed loop around sampling fidelity.
MechanismsTriageNo ADC Internals
Error Mechanisms: How Isolation Degrades ENOB/SNR
Isolation can reduce sampling fidelity through a small set of system-level paths. The fastest diagnosis separates
wideband SNR loss (clock-driven) from tone-locked spurs (power/coupling-driven)
and low-frequency drift (leakage/return-path changes).
Signature symptom
Spur comb locked to DC-DC switching frequency and harmonics; changes with load steps, mode transitions, or rail activity.
Quick check
Toggle DC-DC enable or force a stable mode. Sweep load and observe whether spur frequencies follow the power stage.
First knobPower: select switching band, add post-regulation (LDO), and damp filter resonances on sensitive rails.
PathY-cap / EMI fixes → leakage and common-mode return changes
Signature symptom
EMI improves but low-frequency noise/drift worsens; behavior depends on chassis bonding; touch/leakage constraints become tight.
Quick check
Step Y-cap value or move the connection point (to chassis vs to local return). Track drift/noise changes and spur sensitivity.
First knobReturn + Power: define the intended CM return (or none) and then tune filtering within leakage limits.
Bridge to budgeting
Once the dominant degradation path is identified (Clock / Power / Return), budgeting assigns headroom and prevents hidden spur mechanisms
from consuming the error budget.
Injection paths: the barrier blocks DC conduction but not displacement currents. Spurs often emerge when common-mode energy
closes a return loop and is rectified by nonlinear front-end elements.
BudgetingWorkflowEngineering-Usable
Budgeting: Jitter + Noise + Spurs (System-Level)
Budgeting turns a sampling target into three controllable headrooms—Clock, AFE,
and Power—then adds a spur risk register so hidden coupling does not consume the margin.
Budgeting workflow (target → decompose → merge)
Step 1 — Define targets: set the measurable objective for the system and freeze the operating envelope.
Output: a single “target summary” line that later budgets must satisfy.
Step 2 — Decompose budgets: split the total headroom into three owners with measurable checks.
Clock budget: additive jitter and skew stability (caps high-frequency SNR and coherence).
AFE budget: input-referred noise and nonlinearity/rectification risk (caps spur formation at the front end).
Power budget: ripple/spurs after filtering at sensitive rails (caps deterministic tones and drift).
Each budget uses placeholders (X/Y) so it can be filled per project without turning this page into a textbook.
Step 3 — Merge + spur risk register: combine the three budgets and enumerate fixed-tone risks that can eat margin.
Tone placement: DC-DC fSW and harmonics vs sensitive FFT bins.
Rectification points: protection clamps, ESD devices, or input networks that convert CM energy into tones.
Return-path changes: Y-caps, shield bonds, chassis references that alter CM loop closure.
What this budgeting chapter outputs
A waterfall budget map that assigns headroom to Clock / AFE / Power / Layout.
Three budget cards with a check method and adjustable knobs.
A spur risk register that prevents hidden tones from consuming margin late in the project.
Budget waterfall: total headroom is decomposed into Clock, AFE,
Power, and Layout budgets, then validated as a merged system with a spur risk register.
Clock StrategyPlacementSkew Control
Low-Jitter Clock Isolation Strategy
Low-jitter isolation is achieved by choosing a clock-tree placement pattern, minimizing isolation points, and controlling
skew and power integrity around the distribution network. This chapter stays at the system strategy level
and does not expand device-internal clock-isolator details.
Placement patterns (choose a reusable template)
Pattern AClean → Isolate → Distribute
Preferred default when cross-barrier coherence matters. A single low-jitter root is cleaned first, then isolated once,
then distributed symmetrically on the destination side.
Best for: high-precision ADC/DAC sampling, multi-channel coherence.
Main risk: additive jitter at the isolation point.
First control: place the isolator at a stable node; keep post-isolation fanout symmetric.
Pattern BDistribute → Isolate (multi-point)
Used when physical topology forces multiple isolated endpoints. The dominant risk becomes skew drift and
phase inconsistency across isolation points.
Best for: multiple remote isolated nodes, segmented architectures.
Main risk: skew/phase consistency across endpoints.
First control: restrict the number of isolation points; explicitly budget skew and validate across temperature/startup.
Pattern CDigital Isolator + Reclock (rebuild as new root)
A cost/topology trade-off where clock information crosses the barrier digitally and is re-timed on the far side.
Treat the reclock point as the new clock root for all downstream distribution.
Best for: controlled architectures that can accept a rebuilt clock domain.
Main risk: deterministic delay changes and rebuild sensitivity to local reference/power noise.
First control: keep the rebuilt clock local; avoid mixing rebuilt and non-rebuilt branches.
Skew control (multi-channel consistency)
Skew problems typically appear as “single-channel looks fine” but multi-channel coherence fails. Control skew at three levels:
Topology: prefer single-point isolation; minimize the number of isolation points.
State consistency: aligned enable/reset sequencing so phase does not jump across boot modes.
Skew and phase consistency must be treated as a budgeted quantity (placeholders X/Y) and validated across
temperature, startup order, and supply variation.
Clock integrity checklist (minimum required)
Minimum checklist to preserve clock integrity across isolation without expanding into device internals:
Design gate
Define isolation pointSingle vs multi-pointSymmetric fanoutBypass A/B path
Bring-up gate
Bypass vs isolate FFTCold/Hot boot repeatEnable/reset alignmentLoad sensitivity
Production gate
Define test pointsPass criteria X/Y/NSupply default stateSingle-fault notes
Clock tree patterns: A minimizes skew by isolating once; B increases skew risk with multi-point isolation; C rebuilds the clock and
treats the reclock point as a new root. Each pattern trades jitter/skew/BOM risk differently.
In isolated precision sampling, common-mode energy can cross the barrier and become spurs when it hits a nonlinear point in the
protection or driver chain. The goal is to keep the AFE within linear common-mode headroom, maintain symmetry, and prevent
rectification paths that convert common-mode injection into differential error.
Diagnostic cards (Symptom → Likely cause → Quick check → First fix knob)
Each card below is written as a closed diagnostic loop with a concrete action. It avoids device-internal details and stays within
the isolated AFE boundary.
SymptomSpurs locked to fSW / harmonics
Likely cause
DC-DC ripple reaches reference/AFE rails or couples into the input network; an asymmetry (ΔR/ΔC) converts it into differential tone.
Quick check
Toggle DC-DC enable or force a stable mode; sweep load and verify whether spur spacing follows the power stage.
First fix knobPower + AFE: post-regulate sensitive rails, add damping, and enforce symmetric input filtering values and layout.
SymptomSpurs appear only during dv/dt switching
Likely cause
Barrier capacitance injects common-mode current; the current closes through an unintended return path and is rectified by clamps/ESD/protection devices.
Quick check
Compare switching quiet vs active; change shield/chassis bonding state and observe whether spur amplitude tracks the return-path change.
First fix knobPartition & Return: define a single intentional CM closure (or none) and move nonlinear protection away from the injection hot spot.
SymptomSpur grows nonlinearly with input amplitude / common-mode
Likely cause
Input clamps or protection networks enter nonlinear regions; small mismatch makes common-mode injection convert into differential error.
Quick check
Sweep input amplitude and common-mode; look for abrupt spur slope changes that indicate rectification thresholds.
First fix knobAFE: add series resistance to limit clamp current, re-place clamps, and enforce matched component pairs and mirrored routing.
SymptomLow-frequency drift worsens after EMI fixes (Y-cap/shield)
Likely cause
Added CM return paths shift the reference and bias conditions; leakage currents modulate the measurement baseline.
Quick check
Step Y-cap value or connection point; compare drift and low-frequency noise with chassis bonding states.
First fix knobReturn + Power: define the CM closure and re-isolate reference rails with filtered, low-leakage paths.
Key mechanisms to keep scope tight
Common-mode headroom: ensure injected CM motion stays inside the FDA/driver linear region.
Nonlinear points: clamps/ESD/protection are potential rectifiers; location and symmetry determine spur conversion.
Symmetry rules: ΔR/ΔC and non-mirrored routing convert CM noise into differential error.
AFE integrity map: common-mode energy can cross the barrier and become spurs when it encounters nonlinear protection/driver points
or an unintended return-path closure. Preserve symmetry and keep the driver within common-mode headroom.
Precision sampling across isolation requires a power tree that makes switching tones predictable, keeps sensitive rails locally
regulated, and prevents noisy domains from back-feeding reference and clock rails. This chapter focuses on
precision-only power strategy rather than generic topology encyclopedias.
Architecture choice (Isolate→Regulate vs Regulate→Isolate)
Option 1Isolate → Regulate
Prefer for sensitive rails where local post-regulation and short filtering loops are needed near the ADC, reference, and clock loads.
Strength: local LDO/filter near the load; shorter noise injection path.
Risk signature: fixed-tone spur from isolated DC-DC requires strong post-cleaning.
First control: DC-DC → LDO → damped filter → load, with explicit test points.
Option 2Regulate → Isolate
Used when primary-side power is already well-controlled or power density/thermal constraints dominate. Isolation remains a noise source
that must still be partitioned and filtered on the destination side.
Strength: centralized regulation and thermal handling on the primary side.
Risk signature: “isolated but still noisy” due to coupling and return-path closure.
First control: keep sensitive rails locally cleaned; define the intended return behavior across the barrier.
Switching frequency strategy (spur avoidance rules)
Switching frequency selection is treated as a spur-risk control knob. The objective is to keep tones predictable and avoid sensitive bands.
Rule: keep DC-DC fSW and main harmonics out of the sensitive measurement band (thresholds X/Y).
Rule: avoid mode-hopping/skip behaviors on sensitive rails; keep the spectrum stable under load changes.
Rule: make tones measurable with defined test points (TP) and pass criteria (X/Y/N) rather than relying on “best effort”.
Post-regulation and filtering recipes (cleaning chains)
Recipe 1DC-DC → LDO (primary cleaner)
Use for: ADC_AVDD, REF, CLK-related rails.
Purpose: reduce broadband noise and suppress fixed-tone spurs.
Validation: compare TP_before vs TP_after (noise/spur targets X).
Recipe 2DC-DC → π filter + damping (tone killer)
Use for: known spur bins aligned with fSW/harmonics.
Hard rule: add RC damping to avoid LC peaking and ringing.
Validation: rail FFT shows spur reduction without introducing new resonances.
Recipe 3Domain split (analog / digital / reference)
Use for: DRVDD and digital rails that can back-feed noise into sensitive domains.
Purpose: prevent load transients and switching currents from polluting REF/CLK/ADC rails.
Validation: spur/noise at the ADC front-end remains stable across digital activity states.
Power-tree template (rails → chain → test points)
A reusable rail template avoids ad-hoc fixes and keeps the system verifiable. Each rail is defined by goal, chain, and measurement points.
Power tree for precision: isolate power once, then split rails into sensitive domains (ADC_AVDD/REF/CLK) with local post-regulation and
damped filtering. Each rail defines a goal (X) and test points (TP) to keep validation objective.
PartitionGroundingReturn Path
Partition, Grounding, and Return Path Across the Barrier
Isolation blocks DC conduction but does not block displacement currents. Spur sensitivity is determined by where common-mode energy
closes its return loop. This chapter defines hard partition rules, identifies common “cross-gap return” mistakes, and provides
do/don’t actions that keep the loop closure point controlled.
Hard rules (non-negotiable)
Rule: enforce Primary/Secondary keep-out; no copper, plane, or stitching crosses the isolation gap.
Rule: treat chassis/shield connections as a designed variable with a defined closure point.
Rule: avoid asymmetric paths (ΔR/ΔC/routing) that convert common-mode injection into differential error.
Rule: Y-cap placement/value is a controlled element; it must be budgeted with leakage and spur impact.
Do / Don’t cards (field-ready)
Don’tCopper/plane bridge across the gap
Symptom
“Isolated but still noisy”; small layout edits cause large spur changes; sensitivity to probing and fixture grounding.
Quick check
Inspect the isolation slot boundary for copper islands, reference plane overlap, stitching vias, test pads, or mounting features.
Do
Enforce a visible keep-out zone; use slots/guards and consistent edge rules so partition violations become obvious.
Don’tMulti-point shield/chassis bonding without closure control
Symptom
Spur amplitude changes with enclosure state, cable routing, or maintenance actions; inconsistent results across labs or sites.
Quick check
Toggle bonding states (single-point vs floating) and observe whether spurs track the closure change.
Do
Define a single intended chassis/shield closure point (or a deliberate floating policy) and document it for assembly and service.
Don’tAdd Y-cap as an ad-hoc EMI fix
Symptom
EMI improves but precision degrades; low-frequency drift/noise worsens; spur sensitivity increases with chassis bonding.
Quick check
Step Y-cap value/placement and compare FFT and low-frequency noise; verify whether the loop closure moved.
Do
Treat Y-cap as a controlled return-path element with a defined closure point and measurable pass criteria (X/Y/N).
Return path anatomy: the wrong loop closes through uncontrolled bridges and multi-point chassis bonding. The controlled loop enforces
a visible keep-out and defines a single closure (with optional controlled Y-cap), making spur behavior predictable and debuggable.
EMICbarCMTIY-cap
EMI, Barrier Capacitance, CMTI: The Hidden Coupling Triangle
High CMTI does not guarantee low spurs. Coupling across the isolation barrier is often dominated by barrier capacitance (Cbar) and
where common-mode energy closes its loop. EMI fixes such as Y-caps can reduce emissions while shifting return-path behavior and
introducing leakage and low-frequency error risks.
Barrier capacitance converts fast dv/dt into displacement current (Icm). If Icm passes through an asymmetric path or a non-linear node
in the front-end chain, common-mode energy is converted into differential spurs and baseline shifts.
Injection source: dv/dt events, switching harmonics, and clock/power transitions.
Coupling element: Cbar (plus any unintended parasitic bridges).
Conversion point: protection clamps, ESD diodes, limiter networks, and any non-linear front-end node.
Loop closure: chassis/shield bonding and any Y-cap paths define where Icm returns.
CMTI rating vs real dv/dt and layout
CMTI is a device capability under defined conditions. In a precision sampling system, spur behavior is typically governed by the
actual dv/dt waveform, return-path closure, and layout symmetry rather than the CMTI headline alone.
Mismatch: real dv/dt may be sharper and richer in harmonics than the datasheet test condition.
Mismatch: loop size and closure point can change across boards, fixtures, and enclosures.
Mismatch: asymmetry (ΔC/ΔR/routing) converts CM injection into differential error even without logic upset.
Y-cap trade: EMI gain vs leakage and low-frequency error
A Y-cap is a controlled return-path element. It can reduce emissions by providing a high-frequency return, but it also introduces
leakage/touch-current risk and can worsen low-frequency baseline stability by altering the CM loop closure.
EMI gain: reduced radiated/CM emissions when a controlled HF return is created.
EMI gain: less CM injection, lower radiated coupling •
Precision cost: may require slower edges or different isolation placement •
Safety/ops: verify timing margin and channel integrity (X/Y/N)
KnobEdge-rate control (slew)
EMI gain: lower high-frequency energy and harmonics •
Precision cost: timing margin/eye may shrink; skew sensitivity increases •
Safety/ops: confirm jitter/phase-noise and setup/hold gates (X/Y/N)
EMI gain: can reduce radiation when closure is controlled •
Precision cost: multi-point closure often creates unpredictable loops and spurs •
Safety/ops: define policy (single-point/float) and enforce assembly consistency (X/Y/N)
Triangle trade-off: EMI, precision, and safety/leakage interact through coupling and return-path closure. Knobs such as Cbar, slew,
Y-cap, and bonding policy must be evaluated by explicit pass gates rather than single headline metrics.
Clock GatePower GateFFT GateImmunity Gate
Validation: What to Measure, Where to Probe, and Pass Gates
Validation must prove that isolation does not degrade sampling fidelity. The most valuable approach is a gated checklist with
explicit probe topology and pass criteria placeholders (X/Y/N) for clocks, power, sampling results, and immunity events.
Measurement setup is part of the system and must not create false spurs.
Pass-gate structure (4 gates, each with measurable TP and thresholds)
Gate 1 — Clock: phase noise/jitter, skew, and repeatability.
Gate 2 — Power: ripple and spur content before/after filtering at defined TP nodes.
Gate 3 — Sampling FFT: FFT, spur map, drift under load/temperature/switching states.
Gate 4 — Immunity: ESD/EFT/dv/dt events and resulting spur/offset steps and recovery time.
Setup: repeatable event counts •
Probe: spur/offset jumps correlated to events •
Pass: no latch-up; recovery ≤ X seconds (N events)
TestBonding-state sensitivity
Setup: step bonding policy (single-point vs float) •
Probe: spur map and rail FFT •
Pass: variation ≤ X across states
Measurement topology: use differential probing for sensitive rails/clock and keep return loops short. Long ground leads often create
probe-induced loops that appear as false spurs, so normalization (TP, bonding state, bandwidth) must come before redesign.
Convert “precision sampling across isolation” into repeatable gates that prevent ENOB/SNR regressions,
reduce debug cycles, and standardize acceptance criteria across teams.
Rule
Gate outputs are concrete artifacts: budgets, probe plan, FFT evidence, hi-pot evidence, and field logs.
No gate is considered “passed” without measurable pass criteria.
Three Gates
Design Gate
Budget locked: jitter / AFE noise / power ripple + spur risk mapped to ENOB/SNR target.
Topology decided: clock isolation placement + power tree (DC-DC → post-reg → filtering) chosen.
Partition rules: primary/secondary planes + return path policy documented (what may cross the barrier and what may not).
Risk knobs listed: Cbar, edge rate, Y-cap, shield bond—each with benefit & side effect.
Golden reference BOM: one validated pairing set frozen for debug baseline.
Scope: on-site troubleshooting and acceptance criteria only (clock / AFE / power / partition / coupling / validation).
Each answer is strictly 4 lines with measurable placeholders X/Y/N.
Data rule
Pass criteria must be reproducible: include unit, measurement window,
and repeat count (e.g., spur@bin ≤ X dBcFS, window=Y, avg=N).
Datasheet jitter looks great, but FFT spurs appear after isolation—first suspect which coupling path?4 lines
Likely cause: Common-mode injection via barrier capacitance (Cbar) closes through an unintended return path and is rectified at a non-linear AFE/protection node.
Quick check: A/B test return closure: (1) remove/disable Y-cap or change bonding state; (2) toggle dv/dt activity; (3) correlate spur amplitude with dv/dt and shielding state (same FFT settings).
Fix: Make the CM loop controlled: reduce Cbar or edge-rate energy, enforce single-point shield/chassis policy, and relocate/remove non-linear clamps from the sensitive differential node.
Pass criteria: Spur delta (isolated vs baseline) ≤ X dB at key bins, measured with window=Y and avg=N; no bonding-state sensitive spur shifts.
SNR drops only when isolated DC-DC is enabled—ripple fold-in or ground return issue?4 lines
Likely cause: DC-DC ripple/harmonics fold into the measurement band, or DC-DC switching current changes the return-path closure and injects CM energy into AFE/reference nodes.
Quick check: Lock FFT settings and compare three states: DC-DC off / DC-DC on / DC-DC on + post-reg bypassed (or extra damping). Also measure rail FFT at TP_post_filter and correlate spur bins to fSW.
Fix: Move energy out of band and block it: pick fSW away from sensitive bins, add π filter + damping (R/RC), enforce rail split (REF/AVDD separate), and keep high di/dt loops local and compact.
Pass criteria: SNR drop ≤ X dB when DC-DC toggles; rail spur@fSW (post-filter) ≤ Y dBc; repeatable across N toggles.
Spur at DC-DC switching frequency persists after LDO—filter resonance or layout loop?4 lines
Likely cause: Post-filter resonance (LDO + output cap + π filter) amplifies a narrow band, or a layout loop couples switching current into the analog/reference return.
Quick check: Sweep load and measure spur amplitude vs load; add temporary damping (small R in series with C or RC snubber) and see if spur collapses; verify measurement method (short ground spring / differential probe).
Fix: Add damping to the filter, shorten the high di/dt loop, move LDO/π filter close to the sensitive load, and separate switching ground return from analog/reference return (single-point join if needed).
Pass criteria: Spur@fSW at sample FFT ≤ X dBcFS and rail FFT@TP_post_filter ≤ Y dBc; stable within ±X dB over N load points.
Adding a Y-cap improves EMI but worsens low-frequency noise—what did the return path change?4 lines
Likely cause: The Y-cap created a new CM return closure that reduces radiated EMI but increases low-frequency leakage/ground potential modulation into the measurement reference path.
Quick check: Compare LF noise/offset drift with Y-cap removed vs present; change the Y-cap placement (near chassis entry vs near AFE) and observe whether LF noise tracks bonding/placement state.
Fix: Keep the CM return controlled and away from reference nodes: move Y-cap to the intended chassis reference point, enforce single-point bonding, and add LF isolation (separate REF rail + filtering).
Pass criteria: LF noise (0.1–10 Hz) increase ≤ X% and offset drift ≤ Y ppm/°C with Y-cap installed; leakage/touch current ≤ X µA under test state N.
Clock skew is within spec, yet interleaved channels mismatch—what timing assumption broke?4 lines
Likely cause: The system assumed matched deterministic latency across lanes; isolation/distribution changed phase alignment or introduced cycle-to-cycle variation not captured by static skew.
Quick check: Measure alignment over time and over restarts: capture phase/edge timing across N cold/warm restarts; check if mismatch correlates with PLL lock state or clock-tree placement pattern.
Fix: Force deterministic alignment: isolate at a single point before multi-lane distribution, add re-timing where appropriate, and define a calibration step (per-boot or per-temp) if required.
Pass criteria: Interleave mismatch ≤ X LSB_rms (or ≤ Y ppm gain/phase error) across N restarts; lane-to-lane phase drift ≤ X ps over Y minutes.
Works on bench, fails near inverter switching—CMTI headroom or dv/dt injection into AFE?4 lines
Likely cause: Real dv/dt events drive CM injection that is not an “upset” but an analog spur/offset mechanism via Cbar and AFE rectification points; headline CMTI does not cover the full loop.
Quick check: Trigger-correlate: log dv/dt events (switching edges) and measure synchronized spur bursts/offset steps; compare shielding/bonding states and look for sensitivity to loop closure.
Fix: Reduce injected energy and conversion: slow the offending edges (where allowed), tighten switching loops, move sensitive AFE nodes away from CM return, and harden partition/keep-out + bonding policy.
Pass criteria: Under worst-case switching, spur burst duration ≤ X ms and offset step ≤ Y LSB; no functional resets across N event injections.
Noise floor rises with longer shield—single-point bond wrong or shield acting as antenna?4 lines
Likely cause: Shield termination policy is uncontrolled: multi-point closure creates loops, or a floating/unterminated shield behaves as an antenna and couples into the return/reference.
Quick check: Compare three shield states (single-point / multi-point / float) while holding cable routing constant; measure noise floor and spur map; verify if changes track bonding state rather than signal amplitude.
Fix: Enforce a documented shield policy: choose the intended termination point (often chassis entry), keep the shield return away from REF/AFE, and add controlled HF return only if validated.
Pass criteria: Noise floor increase with max cable length ≤ X dB; spur count above Y dBcFS does not increase vs baseline; stable across N re-terminations.
Precision degrades only at cold/hot—isolated power drift or barrier leakage variation?4 lines
Likely cause: Post-reg regulation/PSRR changes with temperature, or leakage/coupling shifts (capacitive/insulation behavior) alter CM injection and LF stability.
Quick check: Run a temp sweep while recording (1) rail FFT at TP_post_filter, (2) sample FFT spur map, and (3) offset drift. Identify whether degradation follows rail noise or follows bonding/leakage sensitivity.
Fix: Improve temperature robustness: ensure post-reg headroom, choose filtering that remains damped across temp, and lock bonding/return policy to avoid temperature-amplified loop sensitivity.
Pass criteria: Across temp range Y°C, SNR/ENOB change ≤ X dB and offset drift ≤ X ppm/°C; repeatable across N cycles.
One board revision only fails—what partition rule is most commonly violated?4 lines
Likely cause: A hidden cross-gap return or reference-plane discontinuity was introduced (copper pour, stitching, shield bond move, or keep-out violation), changing CM loop closure and spur conversion.
Quick check: Visual + continuity audit against the partition checklist: verify keep-out, plane splits, shield/chassis connection point, and any “bridge” near the barrier; then A/B test bonding/Y-cap states.
Fix: Restore strict partition: remove any cross-gap copper, relocate bonding to the defined point, and ensure sensitive AFE/REF returns do not share a path with switching/CM currents.
Pass criteria: Revision-to-revision delta: spur map difference ≤ X dB and SNR delta ≤ Y dB under the same test plan; pass across N boards per revision.
Likely cause: Different bandwidth/integration limits, trigger methods, or probe loading creates apparent jitter differences; long ground leads or reference mismatch adds time noise.
Quick check: Normalize measurement settings: same integration band (Y Hz–Z Hz), same trigger source, same probe type (prefer differential), and confirm with a known reference clock.
Fix: Standardize the jitter test method in the bring-up gate: define instrument class, bandwidth, trigger, and probing topology; document calibration and repeatability checks.
Pass criteria: Cross-instrument deviation ≤ X% for jitter_rms and ≤ Y ps for skew, verified across N repeats with the same setup.
FFT looks clean but time-domain has glitches—clock loss/UVLO transient or digital burst coupling?4 lines
Likely cause: A transient event (clock loss, UVLO, or bursty digital retries) causes brief sampling corruption that spreads in time but is not obvious in averaged FFT.
Quick check: Capture time-aligned logs: monitor UVLO/PG/clock-lock pins and capture raw sample time series; correlate glitch timestamps to power/clock events and isolate-domain digital bursts.
Fix: Add event hardening: enforce clean reset/lock sequencing, add hold-off windows, and prevent bursty activity from sharing sensitive returns; log the events as black-box counters.
Pass criteria: No time-domain sample discontinuity > X LSB over N minutes; UVLO/clock-loss event count = 0 during acceptance run Y.
Compliance says spacing is fine but field shows drift—what contamination/pollution mechanism was missed?4 lines
Likely cause: Surface contamination/humidity increases leakage across or near the barrier, creating low-frequency bias errors and return-path sensitivity even when nominal spacing is adequate.
Quick check: Compare drift before/after cleaning and under controlled humidity; measure LF noise/offset vs humidity and record leakage-sensitive signatures (bonding state sensitivity, slow baseline wander).
Fix: Improve environmental robustness: define cleanliness/handling rules, add coating/guard where appropriate, and ensure the reference/return network is tolerant to small leakage changes.
Pass criteria: Under humidity condition Y%RH, offset drift ≤ X ppm over N hours; no LF noise increase > X% (0.1–10 Hz band).
