GaN HEMT Gate Driver ICs: 0–6 V Control & Fast Edges
H2-1. Definition & Scope: What a “GaN HEMT Driver” Must Guarantee
Intent: Freeze the contract for this page—what it guarantees, what it does not cover, and which metrics define “pass”.
What this page must guarantee (results, not opinions):
- Charge control boundary: convert PWM edges into a controlled gate-charge / gate-current profile (not “just a voltage”).
- dv/dt immunity: prevent dv/dt-driven false turn-on under worst-case common-mode events.
- Shoot-through prevention: no cross-conduction overlap beyond the allowed timing budget.
Metric language used throughout this page:
- 0–6 V control: Vgs range + overshoot/undershoot limits (≤ X V).
- Edge-rate: dV/dt, dI/dt targets (≤ X kV/µs, ≤ Y A/ns).
- Loop inductance / CSI proxy: ringing amplitude + settling time (≤ X V, ≤ Y ns).
- Timing determinism: propagation delay + skew (≤ X ns skew).
- CMTI: withstand common-mode dv/dt without spurious switching (≥ X kV/µs).
Not in scope (linked only, not explained here):
- Half-/full-bridge topology tutorials, multiphase sharing/interleaving details.
- Isolation safety rules (creepage/clearance) and full isolated bias design.
- Device-family deep dives for IGBT/SiC (DESAT implementation specifics).
See also (navigation only): Topologies / Isolated Gate Driver / Protection & Control.
How to use this page: start with the GaN-specific failure model (H2-2), then lock down loop/parasitics and edge control, and finally validate with measurable pass criteria (X/Y/N placeholders).
H2-2. Why GaN Is Different: Narrow Gate Window & Ultra-fast Edges
Intent: Build the single failure model for GaN gate driving—why “drive it harder” often makes it worse, and why loop inductance dominates waveform control.
Core model (use this to interpret every later chapter):
Narrow Vgs window + very high dv/dt & di/dt + tiny tolerable loop inductance → injected charge and CSI coupling produce Vgs bumps / ringing → false turn-on and shoot-through risk rises unless the driver behaves like a controlled impedance/current system.
What breaks in practice (observable symptoms):
- Gate overshoot/undershoot: Vgs leaves the intended 0–6 V region during switching transients.
- Near-threshold bumps: small Vgs spikes near Vth appear only under high dv/dt events.
- Bench vs system mismatch: waveforms look clean on a short-loop demo board but degrade in the real power stage.
Mechanisms (minimum sufficient explanation):
- Narrow gate window: overdrive increases reliability stress; underdrive increases Rds(on) and loss. With GaN, small parasitics can push Vgs outside the safe region.
- Miller injection path: switch-node dv/dt couples through device capacitances and injects charge into the gate node, creating an unintended Vgs rise.
- CSI coupling path: di/dt across common-source inductance creates a source bounce that effectively modulates Vgs and can generate ringing even if the driver output is “strong”.
- Driver = impedance/current system: peak source/sink current sets how fast Qg is moved; loop inductance determines whether the Vgs trajectory stays controlled or rings.
Engineering consequences (what must be measured, not guessed):
- Vgs envelope: overshoot ≤ X V; undershoot ≥ −Y V; settle ≤ N ns.
- Near-Vth bump: spurious gate bump ≤ X V during worst-case dv/dt.
- Timing determinism: skew/overlap budget remains valid across temperature and supply variation (≤ X ns).
H2-3. Gate Charge & Drive Current: Sizing from Qg to tr/tf (Without Overdriving)
Intent: Convert “how many amps?” into a calculable and verifiable sizing loop—target waveform → required charge movement → drive current scale → waveform acceptance.
Sizing loop (minimum sufficient model)
- Step 1 — Target: choose tr/tf = X ns or dV/dt ≤ X kV/µs based on loss/EMI limits.
- Step 2 — Charge: define the effective charge to move ΔQg = X nC during the transition region.
- Step 3 — Current scale: estimate Ig ≈ ΔQg / Δt (use Δt = X ns for the intended edge).
- Step 4 — Shape: use driver output impedance + Rg(on/off) to shape the edge into a controlled Vgs envelope, not a ringing spike.
- Step 5 — Verify: accept/reject using measurable limits (below), not “looks fine”.
Vgs overshoot < X V
undershoot > −Y V
ring settles < N ns
dV/dt < X kV/µs
Why “more amps” is not always better
- Peak current increases edge speed → higher dv/dt and di/dt.
- Higher dv/dt/di/dt amplifies parasitic coupling (Miller injection, CSI/loop effects) → larger Vgs bumps near threshold.
- GaN has a narrow gate window → small overshoot/undershoot can become a reliability or false turn-on problem.
- Conclusion: drive strength sets “how fast it can be”; controllability depends on impedance shaping and loop parasitics (expanded in H2-4).
Validation (minimum scope set)
Measure together (time-aligned): Vgs, Vds, and Id. The goal is to validate the gate-voltage envelope and the switching-node behavior in the same event window.
- Pass criteria: Vgs overshoot < X V, ring settles < Y ns, and no near-threshold bump above X V under worst-case dv/dt.
- Reject signal: improved loss but increased ringing/false bumps indicates a loop/parasitic limit rather than insufficient driver current.
H2-4. Gate Loop & Parasitics: The #1 Root Cause (CSI, Lloop, Kelvin Source)
Intent: Make “layout and parasitics” auditable. For GaN, the dominant failure mode is often the gate loop geometry and CSI—not the driver’s current rating.
Root-cause chain (minimum model)
- di/dt across common-source inductance (CSI) produces source bounce V = L·di/dt.
- Source bounce effectively modulates Vgs (gate reference shifts), creating bumps and ringing.
- The same driver and Rg can behave “stable” or “unstable” purely due to gate-loop closure geometry.
Auditable layout rules (no topology tutorial)
- Gate loop is a closed loop: Driver OUT → Gate → Source return → Driver GND. Minimize loop area, not just trace length.
- Kelvin source separation: gate return must use Kelvin source (if available) and must not share high-current power return segments.
- Rg placement: place the primary gate resistor close to the GaN gate node to damp local ringing (fine tuning is handled in edge-control chapters).
- Package/layout rule-of-thumb: compact QFN/LGA and tight driver-to-switch placement reduce Lloop sensitivity; avoid long via detours in the gate loop.
Measurement integrity (avoid “fake ringing”)
- Vgs probing: prefer differential probing or very short ground return (no long clip leads).
- Repeatability check: if ringing changes drastically with probe placement, treat it as measurement artifact until proven otherwise.
- Acceptance language: validate with ring amplitude and settling time (≤ X V, ≤ Y ns) under worst-case switching conditions.
H2-5. Edge Control without Killing Efficiency: Split Rg, Ferrite, Two-level Drive
Intent: Resolve the EMI-versus-loss conflict using measurable edge targets and a controllable knob set—no “feels fast/slow” language.
Control targets (use metrics, not intuition)
dI/dt (turn-on)
dV/dt (turn-off)
ring settle
near-Vth bump
Edge tuning is accepted only when the switching event stays inside a defined envelope: dV/dt ≤ X, dI/dt ≤ Y, Vgs overshoot < X V, settle < Y ns.
Split Rg_on / Rg_off (turn-on and turn-off are different problems)
- Rg_on primarily shapes turn-on di/dt and the current-loop excitation that drives ringing and radiated EMI.
- Rg_off primarily shapes turn-off dv/dt and reduces Miller injection risk during the off transition.
- Practical envelope: tune for dI/dt and dV/dt targets while keeping Vgs bump well below the threshold margin.
Ferrite bead / small series resistor (effective boundary)
- Effective when: the gate loop geometry is already controlled (H2-4 passes), but high-frequency ringing energy still exceeds the acceptance envelope.
- Not a substitute: if the loop is large or Kelvin return is wrong, a bead often “moves the problem” rather than eliminating it—results become temperature and placement sensitive.
- Use language: treat ferrite/series-R as a high-frequency damping knob, not an edge-rate “magic fix”.
Two-level turn-on/off (fast threshold crossing, gentle finish)
- Stage 1: strong drive quickly crosses the near-threshold region to reduce switching loss exposure time.
- Stage 2: reduced drive strength or altered impedance limits overshoot and ringing energy during the tail.
- Acceptance: improved EMI/ringing without an excessive loss penalty (define Δefficiency < N% as needed).
Vgs overshoot < X V
settle < Y ns
near-Vth bump < X V
H2-6. Shoot-through Guard: Deadtime, Interlock, and dv/dt-induced False Turn-on
Intent: Provide mechanisms and acceptance gates for half-bridge/full-bridge shoot-through prevention. Treat deadtime as a budget driven by delays and waveform reality—not a habit.
Interlock vs deadtime (division of labor)
- Hardware interlock: enforces “never both ON” at the logic level (non-bypassable baseline).
- Programmable deadtime: absorbs propagation delay mismatch, device turn-off tail, and dv/dt-induced uncertainty to prevent physical overlap.
- Acceptance language: validate with overlap and current, not only with PWM settings.
Delay / skew budget (ns-scale determinism)
Minimum safe deadtime must cover delay uncertainty and device dynamics: DT_min ≥ (tPD mismatch + jitter + drift) + turn-off tail + margin.
tPD
skew
jitter
drift
turn-off tail
Channel matching directly limits PWM resolution and efficiency because excessive deadtime increases loss and distorts effective duty.
dv/dt-induced false turn-on paths (checklist language)
- Miller injection: switch-node dv/dt couples into the gate node via capacitances, creating near-threshold bumps.
- Gate-loop / CSI coupling: di/dt-driven source bounce shifts the gate reference and increases overlap risk.
- Common-mode current: parasitic CM return paths modulate references and can trigger spurious behavior in fast edges.
Validation gate (worst-case conditions)
- Test corners: worst temperature, worst bus voltage, worst load condition.
- Observe: Vds overlap and shoot-through proxy current in the same switching window.
- Pass criteria: no overlap > X ns, peak shoot-through < Y A, and 0 events in N cycles (as required).
H2-7. Driver Supply & Gate Biasing: 0–6 V Rail Quality, Bootstrap Caveats
Intent: Prevent false triggering and gate-voltage drift caused by supply noise, droop, and reference disturbance in a narrow 0–6 V gate window.
Rail quality is part of Vgs (define acceptance, not “clean”)
- Supply ripple: specify VDD ripple (pk-pk) < X mV within a defined bandwidth (Y MHz).
- Transient droop: specify VDD droop < Y mV inside the switching event window.
- Resulting gate impact: accept only when Vgs jitter from rail injection < X V under worst-case dv/dt.
ripple < X mV
droop < Y mV
Vgs jitter < X V
Why GaN is more sensitive to rail disturbance
- Narrow gate margin: small rail excursions can push Vgs closer to threshold boundaries.
- Ultra-fast edges: dv/dt and di/dt amplify reference disturbance and couple supply noise into the gate loop.
- Practical rule: qualify rail behavior by its impact on the Vgs envelope, not only by DC voltage.
Bootstrap / charge pump: usable, but conditional (rules only)
- Refresh requirement: high-side bias must be periodically refreshed; insufficient refresh causes VDD drift and Vgs loss of margin.
- dv/dt environment: high dv/dt increases common-mode disturbance; robust local return and placement are mandatory for repeatable behavior.
- Charging path artifacts: recovery and parasitics in the charging path can inject noise; accept only when the Vgs envelope stays stable across corners.
Detailed sizing and refresh limits belong to the High-Side Gate Driver (Bootstrap/Charge Pump) subpage.
Negative bias decision frame (allowed / benefit / risk)
- Allowed: confirm the switch and driver gate limits allow negative bias across all transients.
- Benefit: increases off-state margin against dv/dt-induced bumps and coupling.
- Risk: tighter reliability margin, more complex bias generation, and more corner cases in startup/shutdown.
- Default posture: prioritize loop control and controlled turn-off; reserve negative bias as a last-stage knob when required.
Decoupling and return: placement priority (auditable)
- Priority 1: VDD-to-GND local decap must close a minimal loop at the driver pins.
- Priority 2: decap return must not cross splits or long detours (detour inductance becomes VDD droop during edge events).
- Priority 3: keep the supply injection path away from the sensitive gate reference path to reduce rail-to-Vgs projection.
H2-8. Protection & Fault Handling for GaN: OCP, OT, UVLO, Safe Disable Path
Intent: Accept protection only when it is fast, controlled, and repeatable—fault detection, turn-off behavior, and reporting must be deterministic.
Protection philosophy (acceptance-driven)
fast response
controlled turn-off
repeatable fault path
Define timing and waveform gates: tRESP < X ns/µs, Vds overshoot < Y V, and consistent behavior across N repeated fault injections.
UVLO (independent ON/OFF thresholds)
- Purpose: prevent half-conduction and unstable switching when the bias rail droops or ripples.
- Acceptance: UVLO_ON = X V, UVLO_OFF = Y V, and no chatter under worst-case rail ripple.
OCP / short-circuit paths (rule-level options)
- Sensing: shunt / current sense / fast comparator / driver-integrated protection hooks.
- Timing gate: specify detect < X ns/µs and action start < Y ns/µs as a total path budget.
- Repeatability: identical fault injection must produce the same trip latency and turn-off envelope within tolerance.
Soft turn-off / controlled dV/dt turn-off
- Goal: reduce overshoot and ringing energy while achieving a safe deactivation time.
- Acceptance: Vds overshoot < X V, ring settle < Y ns, and a defined tOFF_safe window.
Fault reporting and safe disable path (fail-safe principles)
- Signals: /FLT, /RDY, EN must default to a safe state on power loss or open-circuit conditions.
- Disable priority: the disable path must override software timing and stop switching deterministically.
- Across isolation: keep reporting and disable behavior deterministic (rules only; detailed isolation design belongs to isolation pages).
H2-9. Isolation & CMTI for GaN Systems: When You Need It and What It Breaks
Intent: Define CMTI as an auditable determinism gate under dv/dt stress, while keeping isolation details scoped to isolation subpages.
CMTI / dv/dt acceptance language (hard gate)
- Stress: qualify at dv/dt = X kV/µs (e.g., 50/100/200 kV/µs as project-defined thresholds).
- Determinism: 0 false toggles and 0 missing pulses in N switching cycles.
- Glitch bound: optional glitch width < Y ns for strict receiver immunity.
dv/dt = X
0 false toggles
0 missing pulses
glitch < Y ns
Why CMTI becomes a hard threshold in GaN systems
- Switch-node dv/dt: common-mode steps can momentarily shift receiver thresholds and references.
- Symptom signature: “bench OK, system fails” often tracks dv/dt and common-mode return geometry, not only driver peak current.
- System consequence: a single spurious edge can translate into deadtime violation, overlap risk, or protection misfire.
What isolation breaks (budget items, not opinions)
- Added delay: ΔtPD reduces PWM minimum pulse width and increases deadtime budget pressure.
- Added skew: Δskew degrades multi-channel matching in half-bridge/3-phase/multiphase systems.
- Bias complexity: isolated bias adds startup, UVLO corner cases, and layout constraints.
- Fault propagation: /FLT and disable paths can be delayed; total protection response must be re-budgeted.
When isolation is required (decision frame)
- Required: high-side floating domains, non-negotiable safety isolation, or uncontrollable common-mode environments.
- Strongly recommended: high dv/dt + strict determinism requirements (tight deadtime, multi-bridge synchronization).
- Optional: common-ground, controlled return paths, and validated dv/dt immunity that passes the determinism gates.
Integrated approaches (isolated driver / isolator+driver combo): system-level fit
- Timing coherence: tighter control of path delay and channel matching when the barrier and receiver/driver are co-designed.
- Layout reduction: fewer cross-domain interconnects can reduce coupling surfaces and ambiguity in return paths.
- Fault path clarity: more deterministic disable/reporting flow when the system is architected around a single timing domain.
Selection details remain in isolation subpages; this section defines fit criteria only.
H2-10. Interfaces & Timing: Input Robustness, Prop Delay, Skew, Jitter
Intent: Define control interfaces as acceptance criteria for noise immunity and determinism—propagation delay, skew, and jitter must be budgeted and verified.
Determinism gates (choose one definition set and stick to it)
- Propagation delay: tPD (max) = X ns across voltage and temperature corners.
- Channel matching: skew < Y ns for half-bridge, 3-phase, and multiphase coherency.
- Edge stability: jitter_pkpk < Z ns (or RMS, as a project-defined metric).
- Noise immunity: no spurious transitions under defined noise/dv/dt stress.
tPD
skew
jitter
no spurious
Single-ended vs differential inputs (selection frame)
- Differential is preferred when: long interconnects, uncertain returns, or high common-mode disturbance are present.
- Single-ended can be sufficient when: return paths are controlled, distances are short, and dv/dt immunity passes determinism gates.
- Acceptance language: use “no spurious transitions under stress” rather than “works on the bench”.
Propagation delay (tPD): the real impact
Deadtime and minimum pulse width must include the full interface contribution: DT_min ≥ (tPD mismatch + jitter + drift) + device tail + margin.
- Too small DT: overlap risk increases when total path delay shifts at corners.
- Too large DT: efficiency drops and effective duty is distorted (especially visible in synchronous stages).
Skew: multi-channel coherency gate
- Half-bridge / 3-phase: skew shifts real overlap/blanking and changes switching symmetry.
- Multiphase: skew becomes phase error and can degrade current sharing and ripple cancellation.
- Gate: enforce inter-channel skew < X ns across corners.
Jitter / edge wander: define the metric before arguing results
- Cycle-to-cycle jitter: edge deviation between adjacent cycles (captures local wander).
- TIE-style jitter: deviation relative to a reference edge (captures accumulated drift).
- Gate: pick pk-pk or RMS, then enforce jitter < Y ns under dv/dt stress.
Validation: minimum observable set (determinism proof)
- Observe: PWM source edge, post-isolator/level-shift edge, and driver input/output edges in the same time window.
- Stress: worst dv/dt and EMI conditions; enforce “no spurious” plus the jitter/skew gates.
- Statistics: 0 errors in N cycles with defined sampling bandwidth and trigger definition.
H2-11. Design Checklist: Design → Bring-up → Production (GaN Driver Focus)
This section converts GaN gate-driver risk into audit-ready gates. Each item is written to be measurable (X/Y/N) and repeatable across teams, labs, and production lines.
Intent
Enforce consistency. Prevent the most common GaN failures (false turn-on, ringing-driven overstress, shoot-through, rail-noise induced jitter) by locking geometry, knobs, timing budgets, and fault paths before scaling.
Reference MPN basket (examples): TI LMG1020 / LMG1210 / LMG1205, ADI ADuM4135, TI ISO7721, TI UCC33420, TI SN6505B, Murata BLM18AG102SN1#, Murata GRM188R72A104KA35D, Vishay CRCW06031R00FKEA, Vishay WSLT2512R0100FEA.
Design Gate (review before layout freeze)
Gate-loop geometry is locked
- CheckGate loop (driver OUT → gate → Kelvin return) is a closed, shortest-possible loop on a defined layer pair.
- Why it mattersCommon-source inductance converts di/dt into Vgs bounce → false turn-on and unstable switching.
- How to verifyAnnotate the loop outline and Kelvin return on the PCB. Review must show the loop does not cross splits and does not borrow power returns.
- Pass criteriaLoop length < X mm (or an equivalent geometric rule). Kelvin return is separate from power source return (Yes/No).
Example MPN anchors: gate resistor (Vishay CRCW06031R00FKEA as a placeholder value), ferrite bead option (Murata BLM18AG102SN1#).
Edge-rate knobs are defined (not “as fast as possible”)
- CheckTarget dV/dt and dI/dt are explicitly specified, with assigned knobs: Rg_on, Rg_off, two-level, optional bead.
- Why it mattersOverdriving increases EMI, overshoot, and dv/dt-induced false turn-on; underdriving increases switching loss.
- How to verifyWrite target wave-shape requirements (overshoot + settling) and a knob hierarchy (safe-to-try first).
- Pass criteriaVgs overshoot < X V; ringing settles < Y ns; dV/dt within X/Y bounds (placeholders).
Driver examples (choose per voltage and topology): TI LMG1020 (low-side fast edges), TI LMG1210 / LMG1205 (half-bridge drivers).
Timing + interlock budget is frozen
- CheckDeadtime is derived from worst-case propagation delay, skew, and edge behavior, not copied from a prior design.
- Why it mattersNs-level skew can erase margin, reduce PWM resolution, and allow overlap under corners.
- How to verifyBuild a timing budget table: tPD(max), skew(max), jitter(max), plus edge overlap risk at min/max temperature.
- Pass criteriaNo overlap > X ns at worst corner; skew < Y ns (placeholders). Hardware interlock present (Yes/No).
Example isolation/timing anchors: TI ISO7721 for logic isolation where required; ADI ADuM4135 when an isolated gate-driver stage is preferred.
Driver rail integrity plan exists (0–6 V is sensitive)
- CheckLocal decoupling is placed to minimize VDD loop inductance; rail ripple/droop limits are specified.
- Why it mattersRail noise directly modulates gate-drive amplitude and timing → jitter and false switching.
- How to verifyDefine the decap stack (HF + bulk) and placement priority; define the measurement point (at driver pins).
- Pass criteriaVDD ripple < X mV; droop during switching < Y mV (placeholders).
Example decap MPN: Murata GRM188R72A104KA35D (0.1µF/100V/0603) as a robust HF decap placeholder; value/voltage should match the rail.
Fail-safe control path is defined
- CheckEN/FLT/RDY logic is fail-safe (open/short defaults to safe-off), including power-up sequencing and UVLO behavior.
- Why it mattersUndefined states create intermittent shoot-through or partial conduction during brownout.
- How to verifyTest plan includes “wire-open” and “wire-short” cases for enable/fault signals and confirms safe state.
- Pass criteriaSafe-off state reached within X µs of fault; no spurious switching in N cycles (placeholders).
Example isolated bias MPNs (when isolation is used): TI UCC33420 (isolated DC/DC module) or TI SN6505B (transformer driver) + a suitable transformer.
Overcurrent sensing path is chosen and bounded
- CheckOCP method is selected (shunt + comparator, current transformer, or in-module telemetry) with a response-time target.
- Why it mattersGaN short-circuit energy margin is tight; late or noisy trips cause overstress or nuisance shutdown.
- How to verifyDefine blanking/filter constraints and a repeatable fault-injection method used in bring-up and production.
- Pass criteriaTrip latency < X ns/µs; no nuisance trip over Y minutes at rated load (placeholders).
Shunt example MPN (value placeholder): Vishay WSLT2512R0100FEA (10 mΩ, 2512). Select the resistance by current and allowable dissipation.
Bring-up Gate (lab procedure)
Start safe: low VDD + low fSW + light load
- CheckInitial switching is performed under reduced stress before stepping to rated conditions.
- Why it mattersGaN failures are often instantaneous; a safe ramp prevents first-switch damage.
- How to verifyDefine a ramp ladder (VDD, VIN, fSW, load) and a mandatory capture at each step.
- Pass criteriaNo false turn-on; Vgs overshoot < X V; ringing settles < Y ns at every ladder step.
Minimum waveform set is mandatory
- CheckVgs, Vds, Id (or equivalent current proxy), and driver VDD are captured in the same time window.
- Why it mattersWithout simultaneous capture, rail-noise induced jitter is misdiagnosed as “layout ringing.”
- How to verifyScope setup checklist: bandwidth, probe type, reference points, trigger definition.
- Pass criteriaVDD ripple < X mV and Vgs jitter < Y mV (placeholders) under worst-case switching.
Probe technique guardrails
- CheckVgs is measured using a differential method that does not add ground-lead inductance.
- Why it mattersGround-lead artifacts create fake ringing and wrong tuning decisions.
- How to verifyUse a differential probe or a coax tip method across gate-source Kelvin points.
- Pass criteriaMeasurement repeatability: waveform differences < X% across repeated captures (placeholder).
Knob order for fixes is enforced
- CheckTuning follows a safe order: Rg / two-level first, then rail decap, then structural layout changes.
- Why it mattersRandom knob changes hide root causes and break transferability to production.
- How to verifyRecord each change as a “knob delta” with before/after waveforms and numeric deltas.
- Pass criteriaEach knob change must improve a target metric by ≥ X% without violating any limit (placeholder).
Production Gate (repeatability + audit trail)
Waveform sampling plan exists
- CheckSampling count and conditions are fixed (units-per-lot and 2–3 defined operating corners).
- Why it mattersWithout a sampling plan, drift and vendor substitutions fail silently.
- How to verifyCapture the same waveform set as bring-up under standardized triggers and probe points.
- Pass criteriaAll key metrics within X/Y across sampled units; no outliers beyond N sigma (placeholders).
Fault injection is standardized
- CheckUVLO/OCP/OT behaviors are tested by controlled stimuli, not ad-hoc “abuse.”
- Why it mattersProtection must be deterministic to prevent field returns and lab-to-lab disagreements.
- How to verifyRun a fixed script: trigger → capture → record latency and turn-off envelope.
- Pass criteriaTrip latency < X; safe-off reached < Y; envelope repeatability within N% (placeholders).
Record template is enforced
- CheckEvery capture is accompanied by numeric fields and configuration metadata.
- Why it mattersScreenshots without numbers do not scale to production or failure analysis.
- How to verifyTemplate includes: conditions, probe method, trigger definition, and X/Y/N metric table.
- Pass criteriaAll required fields are present (Yes/No) and values are in-range (Yes/No).
Substitution-ready BOM is maintained
- CheckCritical items have alternates pre-qualified (driver, isolator, bead, decap, shunt).
- Why it mattersAvailability-driven substitutions can destabilize GaN edges and protection timing.
- How to verifyAlternate part test must pass the same gate set and the same numeric limits.
- Pass criteriaAlternate passes all gates with no new failure modes (Yes/No) under defined corners.
Example alternates (same function class, verify fit): decap family Murata GRM/GCJ 0603 X7R; bead family Murata BLM; shunt family Vishay WSL/WSLT.
H2-12. Application Playbooks + IC Selection Logic (Last before FAQ)
Use-case playbooks map system constraints to a “must-have spec stack,” then to the fastest validation gates. This section avoids topology tutorials and stays focused on driver-centric decisions.
How to use this section
- Pick the closest playbook.
- Adopt the priority stack (must-have specs) and knobs.
- Run the validation gates with X/Y/N limits before escalating to system-level changes.
Playbook A — High-frequency Half-Bridge (GaN)
System boundary
Fast switching edges push dv/dt and di/dt to the limit. Primary risks: false turn-on, ringing-driven overstress, and overlap under corners.
Must-have spec stack (priority)
- CMTI / dv/dt immunity headroom
- Propagation delay + skew + jitter determinism
- Gate drive range (0–6 V) + output impedance / peak drive
- Hardware interlock + deadtime control
- Edge knobs (split Rg, two-level, optional bead)
Reference MPNs (examples)
- Half-bridge driver: TI LMG1210 (200 V) or TI LMG1205 (lower-voltage half-bridge driver)
- Low-side fast-edge driver (when applicable): TI LMG1020
- Logic isolation (when required): TI ISO7721
- Isolated bias (when required): TI UCC33420 (module) or TI SN6505B (transformer driver)
- Edge components: Vishay CRCW06031R00FKEA (Rg placeholder), Murata BLM18AG102SN1# (bead option)
Validation gates (X/Y/N)
- No Vds overlap > X ns at worst corner
- Peak shoot-through < Y A
- Vgs overshoot < X V; ringing settles < Y ns
- Skew < X ns; jitter < Y ns
Playbook B — Totem-pole PFC / LLC Power Stages
System boundary
The dominant failure mode is timing-related overlap under corners. Secondary risks: uncontrolled turn-off overshoot and rail-noise induced edge drift.
Must-have spec stack (priority)
- Interlock + deadtime budget determinism
- Controlled turn-off envelope (soft/limited dV/dt where needed)
- Driver rail stability (ripple/droop limits)
- Robust fault/disable path
Reference MPNs (examples)
- Half-bridge driver family: TI LMG1210 / LMG1205 (select per bus voltage and switching frequency)
- Isolated gate-driver option (when galvanic isolation is required): ADI ADuM4135 powered from a 6 V rail
- Isolated bias: TI UCC33420 (5V/5V module) or TI SN6505B + transformer
- Current shunt (value placeholder): Vishay WSLT2512R0100FEA
Validation gates (X/Y/N)
- Overlap = 0 across temperature/voltage corners
- Turn-off overshoot < X V and controlled settling < Y ns
- No nuisance trips for Y minutes at rated load
Playbook C — BLDC Stages / Fast DC-DC
System boundary
Layout sensitivity dominates: gate-loop parasitics and rail integrity determine EMI, ringing, and false switching.
Must-have spec stack (priority)
- Edge knobs with clear metric targets (dV/dt, settling)
- Gate-loop control (Kelvin return, low CSI)
- Input robustness (noise margin, clean thresholds)
- Deterministic fault/disable behavior
Reference MPNs (examples)
- Fast-edge low-side driver: TI LMG1020 (where topology permits)
- Half-bridge driver options: TI LMG1210 / LMG1205
- Edge components: Murata BLM18AG102SN1# (bead option), Vishay CRCW06031R00FKEA (Rg placeholder)
- Rail decap placeholder: Murata GRM188R72A104KA35D (0.1µF/100V/0603; select voltage per rail)
Validation gates (X/Y/N)
- Ringing settles < Y ns and remains bounded across load steps
- Vgs overshoot/undershoot within X V envelope
- EMI tuning changes do not violate loss/thermal limits (X/Y placeholders)
IC Selection Logic (rule-based)
IF edges are aggressive (speed-first)
- THENPrioritize output impedance/peak drive + package/layout fit + edge knobs.
- VERIFYVgs envelope (overshoot + settling) and rail droop in the same capture window.
- REFERENCE MPNsTI LMG1020 (low-side fast), TI LMG1210/LMG1205 (half-bridge), Murata BLM18AG102SN1# bead option.
- PASSVgs overshoot < X V; settle < Y ns; dV/dt within bounds (placeholders).
IF high-side / floating domain requires isolation
- THENPrioritize CMTI + timing cost (delay/skew) + bias supply architecture.
- VERIFYNo spurious transitions during dv/dt stress; skew remains within budget under temperature.
- REFERENCE MPNsADI ADuM4135 (isolated driver), TI ISO7721 (logic isolator), TI UCC33420 or TI SN6505B for isolated bias.
- PASS0 false toggles in N events; skew < X ns (placeholders).
IF the environment is noisy / wiring is long
- THENPrioritize robust receiver thresholds, clean enable/fault behavior, and deterministic timing.
- VERIFYNoise injection / EFT-like tests do not produce spurious switching or fault chatter.
- REFERENCE MPNsTI ISO7721 for reinforced isolation where applicable; bias integrity via TI UCC33420 (module) as a stable isolated rail option.
- PASSNo spurious edges over Y minutes; fault path always forces safe-off within X µs (placeholders).
Always lock the “critical passive set” early
- THENTreat gate resistors, beads, decaps, and shunts as critical timing/edge parts, not generic BOM fillers.
- VERIFYAlternates must be re-qualified against the same waveform gates and numeric limits.
- REFERENCE MPNsVishay CRCW06031R00FKEA (Rg placeholder), Murata BLM18AG102SN1# (bead), Murata GRM188R72A104KA35D (HF decap), Vishay WSLT2512R0100FEA (shunt placeholder).
- PASSAlternate part introduces no new ringing modes and stays within X/Y limits (placeholders).
Note: MPNs above are reference examples. Confirm supply rails (0–6 V), package thermal limits, and latest availability before freezing the production BOM.
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H2-13. FAQs (10–12): Field Debug & Acceptance Criteria
Scope: only field debugging and acceptance criteria within this GaN driver page boundary (gate loop/CSI, edge knobs, shoot-through guard, rail/bias, protection, isolation/CMTI, timing). Each answer is fixed to four lines with X/Y/N placeholders.
Vgs looks fine on bench, but in system it rings and false-triggers—first suspect CSI or probe setup?
- Likely causeEither a measurement artifact (ground lead inductance / wrong reference) or real Vgs bounce from common-source inductance (CSI) and a shared source return.
- Quick checkRe-measure Vgs across gate–Kelvin-source using a differential/coax method; compare against a ground-lead capture and correlate Vgs bounce with Id di/dt events.
- FixLock a Kelvin source return and minimize the gate loop; place split Rg at the gate (e.g., Vishay CRCW0603 series as placeholder) and remove probing-induced loop area.
- Pass criteriaVgs overshoot < X V; undershoot > −Y V; ringing settles < Y ns; spurious gate pulses = 0 over N switching cycles.
EMI passes only with huge Rg, but efficiency collapses—what’s the first ‘two-knob’ fix?
- Likely causeA single large Rg slows both turn-on and turn-off; EMI improves but switching loss rises sharply, masking an edge-control strategy issue.
- Quick checkTemporarily split Rg into Rg_on and Rg_off and observe which edge dominates the EMI margin; compare loss vs EMI slope when changing only one edge.
- FixUse split Rg_on/Rg_off (two knobs) and/or a two-level gate drive (fast to threshold + gentle tail); optionally add a ferrite bead only in the turn-on path (e.g., Murata BLM18AG102SN1# as a placeholder).
- Pass criteriaEMI margin > X dB (or X dBµV); efficiency drop < Y % from baseline; Vgs ringing settles < Y ns; no false turn-on in N events.
Shoot-through appears only at high temp—delay drift or UVLO threshold shift?
- Likely causeTemperature-driven propagation delay/skew drift reduces deadtime margin, or rail sag shifts effective drive level while UVLO behavior stays “above trip.”
- Quick checkLog tPD/skew vs temperature and capture overlap markers (Vds overlap + peak current) while simultaneously measuring driver VDD at the driver pins.
- FixRe-budget deadtime using worst-case tPD/skew/jitter and increase deadtime by X ns if needed; harden the rail (local decap + loop reduction, e.g., Murata GRM188R72A104KA35D as a decap placeholder) and validate disable/UVLO behavior.
- Pass criteriaOverlap time = 0 (or < X ns) across temperature corners; peak shoot-through < Y A; tPD drift < X ns; Vgs(min) ≥ X V at the gate.
High-side occasionally misfires—bootstrap refresh or CMTI hit?
- Likely causeBootstrap/charge-pump bias droops due to insufficient refresh (high duty / long on-time), or a dv/dt common-mode transient exceeds the receiver/isolation immunity and injects a false transition.
- Quick checkMeasure (VBS−VS) droop and refresh interval; correlate misfires with switch-node dv/dt events; test with forced refresh (minimum off-time) to separate droop from CMTI.
- FixIf droop: increase Cboot and ensure diode/refresh constraints; if CMTI: tighten return path and use a higher-immunity isolation/driver stage (e.g., ADI ADuM4135 or TI ISO7721 as function-class anchors where applicable).
- Pass criteria(VBS−VS) droop < X V; misfires = 0 over N stress events; dv/dt stress at X kV/µs produces 0 output errors; skew remains < Y ns.
Driver UVLO never trips, yet gate undervolts—where is the droop actually happening?
- Likely causeDroop occurs locally at the driver pins due to supply loop inductance and transient current, while the upstream regulator looks stable and UVLO logic does not see the true instantaneous sag at the output stage.
- Quick checkProbe VDD directly at the driver pins (not the regulator output) and capture it in the same window as Vgs/Vds; compare pin-level droop to the upstream rail.
- FixMove/upgrade local decoupling (HF + bulk) and minimize the VDD loop; consider a stiffer local bias source for isolated domains (e.g., TI UCC33420 as an isolated bias module anchor) if the architecture requires it.
- Pass criteriaPin-level VDD droop < X mV and ripple < Y mV; Vgs(min) ≥ X V; no missed pulses or partial-drive states over N cycles.
Turn-off overshoot kills devices—too-fast dV/dt or missing clamp path?
- Likely causeTurn-off di/dt excites parasitic inductance, causing Vds overshoot; additionally, missing/weak clamp and poor gate return allow dv/dt-induced turn-on during the transition.
- Quick checkCapture Vds overshoot and ringing vs Rg_off changes; verify whether overshoot scales with turn-off speed and whether Vgs shows induced bumps during Vds transients.
- FixSlow only turn-off (increase Rg_off, add two-level turn-off) while keeping turn-on optimized; ensure a defined clamp/snubber path and tighten layout return loops; avoid “global Rg inflation” that destroys efficiency.
- Pass criteriaVds overshoot < X V above bus; ringing settles < Y ns; Vgs bump during turn-off < X V; no device failures in N thermal/stress cycles.
Only one phase fails in multi-bridge—layout asymmetry or skew mismatch?
- Likely causePer-phase gate-loop geometry differs (CSI/loop inductance asymmetry) or channel-to-channel timing skew causes unequal overlap/loss in one leg.
- Quick checkCompare phase-to-phase Vgs/Vds/Id captures under identical conditions; measure inter-channel skew and confirm whether the failing phase has a distinct ringing envelope or timing shift.
- FixEnforce symmetric placement and identical gate networks (matched Rg and bead options); use a driver path with tighter delay matching and route timing-critical paths with controlled symmetry.
- Pass criteriaPhase-to-phase skew < X ns; waveform deltas < Y %; ringing settles < Y ns across all phases; 0 phase-specific faults over N hours.
Gate stays ‘half-on’ after fault—EN path not fail-safe or latch logic wrong?
- Likely causeEnable/disable is floating or referenced incorrectly (not fail-safe), or fault-latch/auto-retry sequencing leaves a partial-drive window during recovery.
- Quick checkForce EN to a known-safe level with a defined pull device; capture EN/FLT/Vgs timing during fault and recovery; confirm the driver output state is deterministic when EN is open/shorted.
- FixAdd a fail-safe EN network (pull-down/up) and validate latch/retry mode; ensure UVLO and disable behavior force a hard-off state without intermediate levels.
- Pass criteriaAfter fault, Vgs < X V within Y ns/µs and remains off until reset; no intermediate Vgs plateau > X mV; 0 unintended pulses over N fault cycles.
Random glitches when cabinet door opens—input common-mode pickup or ground reference?
- Likely causeSingle-ended input picks up common-mode noise (E-field coupling) or a ground reference shift injects a false threshold crossing at the receiver.
- Quick checkProbe the input at the receiver reference; correlate glitches with a common-mode event; compare with a short, twisted-pair or differential-drive trial configuration.
- FixUpgrade to differential signaling and/or add isolation/robust receiver staging (e.g., TI ISO7721 as an isolator anchor); add a bounded RC filter that does not destroy timing determinism.
- Pass criteriaSpurious transitions = 0 over N door events; input noise margin > X mV; no false switching under X V/m (or equivalent) disturbance conditions (placeholders).
Scope shows no issue, but field reports sporadic resets—measurement bandwidth/window mismatch?
- Likely causeRare, fast events are missed due to insufficient bandwidth, wrong trigger, or too-short capture window; field resets are dominated by outliers rather than steady-state waveforms.
- Quick checkUse segmented memory/glitch triggers and extend observation to Y minutes/hours; capture reset line and local rail droop at the point-of-load in the same time window.
- FixRedefine acceptance to include time-windowed statistics (N events, Y duration) and add on-board logging where practical; validate by controlled noise injection instead of “waiting for it.”
- Pass criteria0 resets over Y hours; rail droop at the load < X mV; no glitch wider than X ns detected over N trigger opportunities (placeholders).
Adding ferrite fixes ringing but increases loss—what’s the correct split-Rg strategy?
- Likely causeThe ferrite adds frequency-dependent impedance that slows the transition and reduces ringing, but it also increases switching loss when applied symmetrically to both edges.
- Quick checkApply the ferrite only to the turn-on path (diode-steered network) and compare turn-off speed and loss; verify whether ringing reduction is mostly turn-on driven.
- FixImplement diode-steered split Rg: (Rg_on + ferrite bead, e.g., Murata BLM18AG102SN1# placeholder) while keeping Rg_off as a separate resistor; optionally add two-level drive to keep efficiency.
- Pass criteriaRinging settles < X ns; loss penalty < Y %; EMI margin > X dB; false turn-on = 0 over N stress events.
CMTI spec is high, still fails—first check which return path crosses the isolation boundary?
- Likely causeAn unintended return path (parasitic capacitance, Y-cap placement, or reference tie) forces common-mode current through the receiver/isolation barrier, producing false edges despite a high CMTI headline number.
- Quick checkMap the input reference and return currents: identify where the reference crosses the barrier; correlate failures with dv/dt edges; temporarily remove/relocate Y-cap or change return routing to isolate the effect.
- FixKeep the return fully on the correct side of the barrier and minimize CM current through sensitive nodes; place isolated bias close to the isolated driver (e.g., TI UCC33420) and use a high-immunity isolation/driver stage when required (e.g., ADI ADuM4135 / TI ISO7721 as class anchors).
- Pass criteriadv/dt stress at X kV/µs yields 0 output errors in N events; spurious pulses = 0; fault/disable propagation delay < Y ns (placeholders).
Data note: X/Y/N placeholders are intended to be filled with project-specific limits (device gate range, bus voltage, thermal limits, EMC targets, and lab acceptance criteria).
