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Active Miller Clamp for Gate Drivers

Active Miller Clamp for Gate Drivers

← Back to: Gate Driver ICs

Active Miller Clamp exists to prevent dv/dt-induced false turn-on during turn-off—by providing a low-impedance gate-to-source sink path for Miller current. It should be selected and verified quantitatively: clamp strength/threshold/timing must keep Vgs_peak_off below a defined margin under worst-case dv/dt and temperature corners.
Protection & Control • Active Miller Clamp

Definition & When You Need It

Active Miller clamp is a dedicated, low-impedance gate-to-source clamping path that is enabled during turn-off. Its job is not “turn-off faster”; its job is to prevent dv/dt-induced false turn-on by providing a strong sink path for Miller-injected current.

The real problem it targets appears most clearly in a half-bridge. When one device commutates, the opposite device can see a rapid VDS dv/dt. Through the Miller capacitance (Cgd/Cgc), that dv/dt injects current into the gate node. If the gate return impedance is not low enough, the gate voltage can rise above the threshold region and create a brief, unintended conduction event.

  • Typical triggers: higher dv/dt (fast hard-switching), higher effective Cgd at certain VDS, weak driver pull-down, large Rg,off, long/inductive gate loop, and elevated temperature (reduced Vth margin).
  • What it prevents: shoot-through spikes, EMI bursts tied to unintended switching, unexplained current surges during commutation, and sporadic faults that only show up under system-level dv/dt stress.
  • Why “just add gate resistor” is not enough: increasing Rg to tame EMI can raise gate impedance during turn-off, which increases the voltage rise caused by injected Miller current—exactly the opposite of what is needed for false turn-on immunity.
Key takeaway: If the switching node dv/dt is high, false turn-on is a margin and safety problem. Active clamp improves robustness by collapsing gate return impedance at the moment it matters—during off-state dv/dt events.

Related (owner pages): Split/Programmable Gate Resistors · Two-Level Turn-On/Off · Design Hooks & Pitfalls

Active Miller Clamp: Half-Bridge dv/dt → Miller Injection → Clamp Path Half-Bridge Leg HS Switch Commutates SW Node LS Switch Off-state risk dv/dt Cgd Gate Node Miller Injection Gate Driver + Clamp Driver Output (LOW) Finite sink impedance Active Miller Clamp Low-Z Gate→Source path Engages in OFF state Source / Return Goal: keep Vgs below threshold during dv/dt events → prevent false turn-on and shoot-through
Physics Model • Quantitative Intuition

Root Cause Model: Miller Injection Under dv/dt

Start with the injection mechanism. When the switching node voltage changes rapidly, the Miller capacitance between drain and gate generates an injected current:

Injected current: iinj ≈ Cgd,eff(VDS) · (dv/dt)

Gate rise: ΔVGS ≈ iinj · Zgate-return

Where that current goes is the entire problem. During an off-state dv/dt event, the injected current must return to the source through whatever impedance exists in the gate network. In practical drivers, the return path is a parallel combination of:

  • External gate network (Rg,off and series elements): increases effective impedance and converts injected current into ΔVGS.
  • Driver pull-down path (output LOW impedance): not an ideal short; finite sink strength means finite voltage rise at the gate.
  • Active Miller clamp path (when enabled): a dedicated low-impedance gate-to-source clamp that preferentially sinks injected current.

False turn-on happens when margin collapses. Even if the driver “commands OFF,” the injected current can lift VGS. If VGS approaches or crosses the effective threshold region under the instant operating condition (temperature, device spread, noise), a brief conduction pulse can occur. In a half-bridge, this pulse can coincide with the opposite device’s turn-on, creating shoot-through stress.

What makes it worse follows a clean cause→effect chain:

  • dv/dt ↑ → iinj ↑ → ΔVGS ↑ → false turn-on risk ↑
  • Cgd,eff ↑ (device size, operating VDS region) → iinj ↑ → ΔVGS ↑
  • Gate-return impedance ↑ (larger Rg,off, weaker sink, parasitics) → ΔVGS ↑
  • Temperature ↑ → Vth margin ↓ → allowable ΔVGS shrinks even if iinj is unchanged
Key takeaway: dv/dt and Cgd set the injected current; the gate-return impedance converts it into a VGS rise. Active clamp works by making the dominant return path low impedance during off-state dv/dt events.

Related (owner pages): CMTI / dv/dt Immunity · Gate Voltage & Drive Current · (This page) Active Miller Clamp

Equivalent Model: i = Cgd·dv/dt → ΔVgs = i·Z (paths: Rg_off, driver sink, clamp) Core Relations i ≈ C gd,eff · dv/dt ΔV gs ≈ i · Z gate-return Gate Node i inj from C gd due to dv/dt Source / Return Gate-Return Impedance Network Rg,off Driver sink Clamp Clamp effect Low-Z path → smaller ΔVgs Design goal: make the clamp path dominate → minimize Zeq → keep off-state Vgs below threshold
Mechanism • Timing Matters

How Active Miller Clamp Works

What makes it “active” is a dedicated clamp transistor that creates a low-impedance gate-to-source path during the off state. Instead of relying only on the driver output pull-down, the clamp provides a separate, stronger return path that preferentially sinks Miller-injected current.

Enable timing is the core design point. The clamp is typically not on for the entire turn-off transition. It turns on after the gate voltage falls below a specified threshold (often called VCLAMP_EN). This avoids slowing the main gate discharge phase and prevents contention between the output stage and the clamp path.

  • Turn-off phase (gate discharge): the output stage pulls the gate down through its sink capability and external gate network.
  • Off-state dv/dt stress: a commutating node dv/dt injects Miller current (via Cgd) into the gate node.
  • Clamp action: once enabled, the clamp provides a low-Z sink so injected current creates a much smaller ΔVGS rise.
Practical reading: If VCLAMP_EN is too high or clamp strength is too weak, VGS peaks during dv/dt events can still approach the threshold region. If the clamp engages too early, turn-off loss and waveform shaping can be impacted.

Alternatives (short comparison; details belong to owner pages):

  • Stronger pull-down: reduces gate impedance but remains limited by output-stage behavior and corner conditions. (link out)
  • Smaller Rg,off: can reduce ΔVGS but trades off EMI/ringing and turn-off stress. (link out)
  • Negative Vgoff: increases DC margin to Vth; clamp still helps against fast dv/dt injection spikes. (link out)
  • Ferrite bead: targets HF ringing; does not guarantee immunity to dv/dt-driven injection. (link out)

Related (owner pages): Split/Programmable Gate Resistors · Two-Level Turn-On/Off · Gate Voltage & Drive Current · Design Hooks & Pitfalls

Active Miller Clamp Timing: Vgs threshold-based enable and dv/dt immunity Timing View Signals: Vgs (no clamp) Vgs (with clamp) Clamp_on dv/dt event Vclamp_en Vth region dv/dt Vgs peak lower peak Clamp_on Enable after Vgs < Vclamp_en Clamp engages after threshold → preserves turn-off discharge, then holds gate low during dv/dt stress
Datasheet Map • Architecture Choices

Implementation Types & What They Imply

This section standardizes the main implementation variants found in gate-driver datasheets and explains what each variant changes in real designs. The goal is fast screening: clamp destination, clamp strength, pinout implications, and timing logic.

Common implementation variants:

  • Clamp to Source / COM
  • Clamp to −VG (negative rail)
  • Separate CLAMP pin
  • Internal-only clamp
  • Blanking / Delay logic
  • Min on-time

What each choice implies (engineering meaning):

  • Clamp to Source/COM: simplest and broadly compatible; effectiveness depends on the gate-return loop impedance to the source reference used by the clamp path.
  • Clamp to −VG: increases negative holding margin when a negative rail exists; requires predictable behavior across UVLO/fault states and clean reference management for the negative rail.
  • Clamp strength (Rclamp/Iclamp): determines how much the clamp can reduce ΔVGS for a given injected current; datasheet conditions must be mapped to the actual dv/dt corner case.
  • Separate clamp pin: can enable a more direct clamp return and better observability; layout must keep clamp return tight to the intended source reference (details belong to layout owner page).
  • Smart blanking / delay / min on-time: prevents clamp contention during the main discharge and ensures the clamp stays engaged long enough to cover the dv/dt stress window.
Datasheet reading checklist: VCLAMP_EN threshold, RCLAMP/ICLAMP (with conditions), tON/tOFF, any duty-cycle/min-on-time limits, temperature derating, and clamp behavior under UVLO/fault.

Related (owner pages): Isolation & Integration · CMTI / dv/dt Immunity · Design Hooks & Pitfalls

Gate Driver + Active Miller Clamp: Implementation Blocks and Variants Gate Driver IC (conceptual) IN / PWM Logic interface Control + Timing UVLO / fault states Blanking / delay Min on-time Output Stage Source / Sink Finite Rout Drive strength GATE Vgs Monitor Comparator @ Vclamp_en Clamp Path Low-Z transistor Gate → Return Gate sense COM / Source −VG (optional) CLAMP pin optional variant Variants: clamp destination (COM/−VG), strength (Rclamp/Iclamp), pinout, and blanking logic determine dv/dt immunity
Spec Dictionary • Standardized Terms

Key Specs (Definitions You Will Standardize)

This page standardizes active Miller clamp specifications into a consistent, reusable vocabulary. These definitions are intended to be referenced across the site without re-defining terms on every related page.

  • VCLAMP_EN
  • ICLAMP
  • RCLAMP@V
  • tCLAMP_ON
  • tCLAMP_OFF
  • Max dv/dt
  • UVLO behavior
  • Temp derating

Clamp Enable Threshold (VCLAMP_EN)

DefinitionGate-voltage level below which the clamp path is allowed to engage (typically after the main turn-off discharge).

Datasheet readMay be provided as typ/min/max; naming varies. This is an enable threshold, not the device threshold voltage and not a hard VGS clamp value.

Why it mattersIf too high, the clamp may engage late relative to a fast dv/dt event; if too early, it can interact with the main discharge behavior.

PitfallConfusing VCLAMP_EN with VTH or assuming it guarantees a maximum VGS peak by itself.

Clamp Sink Capability (ICLAMP or RCLAMP@V)

DefinitionHow strongly the clamp can sink Miller-injected current once enabled, expressed as a clamp current rating or an equivalent on-resistance at a specified VGS test point.

Datasheet readICLAMP is usually stated at a specific VGS; RCLAMP@V is an equivalent resistance derived at a stated operating point. Conditions must be aligned to the expected off-state VGS peak region.

Why it mattersThis spec directly determines how small ΔVGS becomes under a given injected current imiller.

PitfallUsing typical values only, ignoring hot-corner derating, or comparing ICLAMP numbers measured at dissimilar VGS conditions.

Clamp Propagation (tCLAMP_ON / tCLAMP_OFF)

DefinitionTime from the enable condition being met to the clamp forming an effective low-impedance path (ON), and time to release it (OFF).

Datasheet readOften measured on a standardized test circuit. Real behavior depends on the actual gate loop and how the IC implements blanking/min-on-time logic.

Why it mattersFast dv/dt injection peaks occur in short windows; if tCLAMP_ON is slow, VGS peaks can occur before the clamp becomes effective.

PitfallAssuming propagation numbers alone guarantee dv/dt immunity without checking clamp strength and threshold timing.

Max dv/dt Rating (If Specified)

DefinitionA vendor-provided dv/dt tolerance claim under stated conditions. Treat as a reference bound tied to the test setup.

Datasheet readDepends on device capacitances, gate loop impedance, temperature, and measurement configuration. Not a universal guarantee across all systems.

Why it mattersUseful as a quick screening hint, but selection should still be based on imiller, margin, and required clamp impedance.

PitfallUsing a single dv/dt line item as the sole pass/fail criterion.

Interaction with Output LOW State

DefinitionDuring turn-off and off-state stress, the gate return network is typically a parallel combination of driver sink path, external gate network, and clamp path (once enabled).

Datasheet readDriver sink current and clamp sink capability are separate mechanisms; the clamp often becomes dominant only below VCLAMP_EN.

Why it mattersTurn-off shaping is mostly set by the output stage and Rg, while dv/dt immunity is largely set by the clamp path effectiveness after enable.

PitfallAssuming “strong driver sink” alone implies strong dv/dt immunity in off-state corners.

Limits & Corner Behaviors

DefinitionHard limits and corner-state behaviors that can bound clamp usefulness and safety: max VGS, any clamp-pin current limit, temperature derating, and UVLO/fault-state clamp behavior.

Datasheet readLook for min/max across temperature, and confirm what happens to the clamp under UVLO or fault states (hold, release, or undefined).

Why it mattersMost false turn-on escapes occur at corners: hot Vth drift, higher dv/dt, and altered state-machine behavior during protection events.

PitfallIgnoring UVLO behavior or assuming clamp strength is constant with temperature.

Standard mapping rule for later chapters: convert clamp strength into an equivalent impedance near the expected off-state VGS peak region, then compare it to the required Rreq derived from the dv/dt injection model.

Related (owner pages): Propagation Delay & Matching · CMTI / dv/dt Immunity · Fault Reporting & Disable

Spec Map: V_CLAMP_EN, t_CLAMP_ON, Vgs peak under dv/dt event Spec Map on a Timing View VCLAMP_EN dv/dt event Clamp_on Vgs drops below VCLAMP_EN tCLAMP_ON Vgs_peak (no clamp) Vgs_peak (with clamp) Map specs to waveforms: VCLAMP_EN, tCLAMP_ON, clamp strength → Vgs_peak under dv/dt stress
Quantitative Flow • Pass/Fail Logic

Design & Selection Logic (Quantitative, Not Hand-Wavy)

This section provides a repeatable selection flow: estimate the Miller-injected current under worst-case dv/dt, define an allowable off-state VGS rise margin, then derive a required clamp impedance and compare it against datasheet clamp strength at corner conditions.

Step 1 — imiller ≈ Cgd,eff(VDS) · (dv/dt)
Cgd,eff from device capacitance curves (varying with VDS) or a conservative estimate; dv/dt from worst-case switching-node slope under the fastest commutation corner.
Step 2 — Allowed rise: ΔV = VTH,min − VGS,off − Margin
VTH,min uses the minimum threshold corner (including temperature drift); VGS,off is the actual off-state baseline (0 V or −V); Margin reserves noise and reference movement budget.
Step 3 — Required clamp impedance: Rreq ≤ ΔV / imiller
Target is a clamp path strong enough to dominate the gate-return network during the dv/dt stress window.
Step 4 — Datasheet mapping: Req ≈ Vtest / ICLAMP (or use RCLAMP@V)
Compare using hot-corner values (ICLAMP,min or RCLAMP,max) and align test conditions to the expected VGS peak region when possible.

Side-effect checks (screening, not a full layout chapter):

  • Threshold timing risk: if VCLAMP_EN is high and dv/dt peak happens early, clamp engagement can be late relative to the injection peak.
  • Strength shortfall risk: if Req is above Rreq at hot corner, VGS peaks can still approach the threshold region.
  • Timing logic risk: blanking or min-on-time may not cover the dv/dt stress window at the target PWM pattern; confirm the intended operating mode.
Decision hints (keep short; details belong to owner pages):
  • Req ≫ Rreq: select a stronger clamp implementation. (link)
  • ΔV too small (low VTH,min, hot corner): consider −VGOFF to increase DC margin. (link)
  • Near-miss case: modestly reduce Rg,off only if EMI/turn-off stress budget allows. (link)

Related (owner pages): Negative VGOFF & Miller · Split/Programmable Gate Resistors · SiC MOSFET Driver

Selection Flow: dv/dt + Cgd → i_miller → margin → R_req → datasheet pass/fail Input: dv/dt (worst) Switch node slope Input: Cgd_eff From curves / estimate Compute i_miller i = Cgd_eff · dv/dt Peak injection current Input: VTH_min Hot corner Input: VGS_off 0 V or −V baseline Compute allowed ΔV ΔV = VTH_min − VGS_off − Margin Derive R_req R_req ≤ ΔV / i_miller Map datasheet R_eq from I_CLAMP or R_CLAMP PASS? If FAIL: adjust knobs Clamp / −VGOFF / Rg,off YES NO Quantitative pass/fail: compute R_req from dv/dt and margin → compare to hot-corner clamp strength
System Summary • Short Conclusions + Links

System Interactions (What Changes When Clamp Exists)

This section summarizes what changes at the system level when an active Miller clamp exists. Each item provides a short conclusion and a practical application note, then links to the owner page for deeper mechanisms and tuning.

With Split Rg_on/off

What changesThe clamp reduces dependence on ultra-small Rg,off as the only way to achieve off-state dv/dt immunity.

WhyDuring off-state dv/dt stress, the clamp provides a dedicated low-impedance sink path for Miller-injected current, so immunity is no longer forced to come solely from minimizing the gate network impedance via Rg,off.

How to applyIf Rg,off is already near the EMI/ringing limit, prioritize clamp threshold and clamp strength instead of pushing Rg,off smaller.

Owner page: Split/Programmable Gate Resistors

With Negative VGOFF

What changes−VGOFF increases DC margin to VTH; the clamp still matters for fast dv/dt spikes that create short, high-current injection events.

WhyNegative bias shifts the off baseline, widening allowed ΔV, but imiller still exists. The clamp reduces the effective impedance during the dv/dt window so VGS peaks stay below the threshold region.

How to applyIf failures correlate with low-VTH/high-temperature corners, −VGOFF increases margin; if failures correlate with fast commutation spikes, clamp strength and enable timing are primary.

Owner page: Negative VGOFF & Miller

With Two-Level Turn-Off

What changesTwo-level turn-off intentionally shapes the discharge; the clamp must not take over during the shaping phase.

WhyTwo-level control changes the effective gate discharge impedance across phases. If the clamp engages too early, it can override the intended second-stage slope control and alter loss/EMI trade-offs.

How to applyVerify VCLAMP_EN occurs after the intended shaping region, so the clamp primarily acts during off-state dv/dt exposure rather than during turn-off shaping.

Owner page: Two-Level Turn-On/Off

With Deadtime / Shoot-Through Interlock

What changesThe clamp reduces dv/dt-induced false turn-on risk during deadtime when the opposite switch commutates hard.

WhyDeadtime is when one device must stay firmly off while the other side causes the largest switching-node dv/dt. A strong clamp path sinks injected current and limits VGS rise in that exact window.

How to applyVerification should focus on worst-case commutation and minimum deadtime patterns, using VGS peak-off and shoot-through spike metrics.

Owner page: Deadtime & Shoot-Through Interlock

With Isolated Drivers (CMTI Coupling Paths)

What changesClamp effectiveness depends more strongly on reference movement and common-mode transient coupling paths across the isolation barrier.

WhyIsolation parasitics can move the local source/COM reference during fast transients. The clamp can lower gate impedance, but it cannot eliminate reference shift that changes the effective VGS seen by the device.

How to applyScreen the clamp together with CMTI rating and isolation return strategy; treat “dv/dt immunity” as a system property, not a single-spec guarantee.

Owner page: Isolation & Integration · Owner page: CMTI / dv/dt Immunity

Quick rule: use split Rg and two-level control to shape switching behavior; use the clamp (and −VGOFF when needed) to keep off-state VGS below the threshold region during dv/dt stress windows.
System Interactions: Active Miller Clamp + Surrounding Blocks Gate Network (center) Driver OUT Sink/Source Split Rg Rg_on / off GATE Power FET HS/LS device Active Clamp Gate→Source dv/dt immunity −VGOFF Rail DC margin Two-Level Turn-off shaping Deadtime Interlock window Isolation CMTI paths Clamp interacts with Rg shaping, −V margin, deadtime dv/dt stress, and isolation reference motion
Bring-up Ready • Test Plan + Pass/Fail

Verification & Measurement Plan (Bring-Up Ready)

This section defines a bring-up measurement plan that verifies off-state immunity under worst-case dv/dt. The focus is trustworthy measurements: correct reference points, correct bandwidth, and metrics that map to shoot-through risk.

What to Measure

VGS(off) under dv/dtCapture VGS on the device that is supposed to be off while the opposite switch commutates hard.

Switching dv/dtMeasure the switching-node VDS slope that drives Miller injection.

Shoot-through evidenceObserve current spikes in the bridge leg or bus that indicate unintended overlap conduction.

Clamp timingConfirm clamp engagement relative to VCLAMP_EN crossing (when measurable) and relative to the dv/dt event window.

Test Setups (Worst-Case Corners)

  • Double-pulse test: controlled hard-switching to create repeatable worst dv/dt and di/dt windows.
  • Hard-switching worst case: highest bus voltage corner with the fastest commutation condition (device/driver settings that produce the steepest slopes).
  • Temperature corners: cold / room / hot to expose VTH drift and clamp strength derating.
  • Deadtime stress pattern: minimum deadtime allowed by the system timing to maximize false-turn-on sensitivity.

Pass / Fail Metrics (Placeholders)

  • Off-state VGS peak: VGS_peak_off < X V when dv/dt = Y kV/µs across temperature corners.
  • No overlap current: shoot-through spike < Z A (or within a defined acceptable transient window).
  • Clamp engagement: clamp effective within t < N ns after VGS crosses VCLAMP_EN (reference point defined below).
Measurement must state reference and bandwidth: VGS is only valid when referenced to Kelvin source (or the closest source reference), with bandwidth sufficient to capture dv/dt-driven peaks.

Instrument Traps (Common False Readings)

  • Probe capacitance changes the circuit: extra C at the gate node can reduce or reshape VGS peaks and ringing.
  • Wrong reference point: measuring “gate to remote ground” mixes source bounce into the VGS reading.
  • Bandwidth limits hide peaks: insufficient bandwidth can under-report dv/dt and VGS overshoot.
  • Ground-lead inductance creates fake ringing: long ground leads add inductive loops that display non-physical oscillations.

Related (owner pages): Design Hooks & Pitfalls · CMTI / dv/dt Immunity

Bring-up Measurement Hookup: VGS reference, VDS dv/dt node, current probe placement Half-Bridge Under Test BUS+ BUS− / COM HS FET Switch node dv/dt LS FET Off-state target SW node dv/dt Gate Driver Clamp enabled Kelvin Source VGS Probe Ref: Kelvin source VDS Probe Node: SW and rails Current Probe Bus or leg current Valid VGS requires Kelvin reference + short return; avoid long ground leads and remote grounds
Most Valuable • Symptom → Cause → Action

Failure Modes & Debug Playbook

This playbook stays strictly within active Miller clamp boundaries: clamp enable threshold, clamp strength, engagement timing, and state-machine behavior under UVLO/fault/disable. Layout is referenced only at the clamp-return level and delegated to the owner page.

Debug order (fastest isolation): measurement sanity → clamp enable/state table → Rreq vs Req (hot corner) → threshold/timing alignment → system knobs (linked pages).
SymptomStill false turn-on / shoot-through during opposite-side commutation

Likely causeClamp too weak (Req too high), VCLAMP_EN too high (engages late), clamp not enabled, or clamp released during UVLO/fault/disable.

Quick checkUse measured dv/dt to recompute imiller and Rreq, then compare against datasheet corner clamp strength (Req,hot or ICLAMP,min). Confirm enable mode and state-table behavior in the actual operating state.

Fix (priority)(1) Correct VGS measurement reference (Kelvin source) → (2) correct enable/mode/UVLO behavior → (3) select stronger clamp (lower Req, higher ICLAMP, faster tON) → (4) align threshold window (VCLAMP_EN matches the dv/dt window).

Pass criteriaVGS_peak_off < X V at dv/dt = Y kV/µs across temperature corners; no overlap spike > Z A.

SymptomTurn-off slows / switching loss rises after adding clamp

Likely causeClamp engages too early and interferes with intended discharge shaping, or creates contention with the output low stage during the shaping interval.

Quick checkMark where VGS crosses VCLAMP_EN and when clamp becomes effective; confirm it does not engage inside the intended shaping phase (for example, a two-level turn-off stage).

Fix (priority)(1) Choose a clamp threshold/timing that engages after shaping → (2) verify blanking/min-on-time behavior if specified → (3) re-validate loss/EMI trade using the corrected clamp behavior (linked owner pages).

Pass criteriaSwitching loss/temperature returns within X% of target while VGS_peak_off remains below the dv/dt stress limit.

Owner page: Two-Level Turn-On/Off

SymptomSporadic faults only at hot temperature

Likely causeClamp current derates at hot corner (Req increases), VTH shifts downward reducing ΔV margin, or UVLO/fault behavior changes clamp state under thermal stress.

Quick checkRe-run the closure using hot-corner values: Rreq (from measured dv/dt) vs Req,hot. Compare VGS_peak_off cold vs hot under identical dv/dt. Confirm clamp state in UVLO/fault/disable at hot.

Fix (priority)(1) Select a stronger clamp grade using hot-corner minima → (2) if ΔV is margin-limited, add −VGOFF as a DC margin knob (linked page).

Pass criteriaTemperature sweep: VGS_peak_off < X V for dv/dt = Y kV/µs across cold/room/hot.

Owner page: Negative VGOFF & Miller

SymptomWorks in lab, fails in system

Likely causeSystem dv/dt is higher than bench assumptions, clamp enable conditions differ by system mode, or UVLO/fault events place the driver into a clamp state not exercised on the bench.

Quick checkMeasure dv/dt in the real system and recompute Rreq; compare to hot-corner Req. Confirm clamp behavior under the exact system states (enable, UVLO, fault latch/auto-retry).

Fix (priority)(1) Re-size clamp to the system dv/dt → (2) verify clamp state-machine behavior for system fault modes → (3) for isolated drivers, screen CMTI/reference motion interactions (linked pages).

Pass criteriaSystem worst case: VGS_peak_off < X V at measured dv/dt = Y kV/µs; no overlap spike > Z A.

Owner page: CMTI / dv/dt Immunity · Owner page: Isolation & Integration

SymptomClamp indicator / clamp pin behavior looks wrong (if available)

Likely causeClamp not enabled by configuration, clamp pin current limit violated, or the driver forces a defined clamp state under UVLO/fault/disable.

Quick checkCompare observed behavior against the datasheet state table for EN/UVLO/fault. Confirm clamp pin usage and any specified clamp pin current limits.

Fix (priority)(1) Restore valid pin configuration and operating state → (2) keep clamp pin usage within datasheet limits → (3) re-test clamp engagement timing under dv/dt stress.

Pass criteriaIndicator matches the expected state table, and VGS_peak_off remains below X V at dv/dt = Y kV/µs.

10-minute quick checks
  • Measurement sanity: Kelvin source reference, short return, adequate bandwidth.
  • Clamp enabled: EN/mode pins and state-table behavior in the actual operating mode.
  • Strength closure: Rreq (system dv/dt) vs Req,hot (datasheet corner).
  • Threshold/timing: VCLAMP_EN and tCLAMP_ON aligned to the dv/dt window.
  • Fault/UVLO: clamp behavior verified during protection transitions.

Owner references: Design Hooks & Pitfalls · Layout & Grounding · Verification & Measurement Plan

Debug Flow: Symptom → Clamp Cause → Action Symptom Clamp Cause Action False turn-on Shoot-through spike Turn-off slower Loss increases Hot-only faults Corner escapes Lab OK System fails Too weak R_eq > R_req Threshold high Engages late Timing / logic t_ON / blanking State machine UVLO / fault Sanity measure Kelvin + BW Enable / table EN/UVLO/fault Re-size clamp R_req closure Align threshold Timing window Close loop: R_eq ≤ R_req If fail: strengthen / align / verify
Engineering Gates • Design → Bring-up → Production

Design Checklist (Design → Bring-Up → Production)

This checklist is written as executable gates. Each item is intended to be checked and audited. Only clamp-specific layout guidance is included; general layout and grounding details belong to the owner page.

Design Gate (Quantitative Closure)

  • Worst-case dv/dt is defined: X kV/µs (bus / load / temp state recorded).
  • Cgd,eff is sourced: Y pF (curve point or conservative estimate recorded).
  • Injected current is computed: imiller = Cgd,eff · dv/dt (value recorded).
  • Allowed rise is defined: ΔV = VTH,min − VGS,off − Margin (Margin recorded).
  • Required impedance is derived: Rreq ≤ ΔV / imiller (value recorded).
  • Corner mapping is closed: Req,hot ≤ Rreq (PASS/FAIL recorded).
  • Threshold/timing alignment: VCLAMP_EN and tCLAMP_ON meet dv/dt window (PASS/FAIL).
  • State table verified: clamp behavior under EN/UVLO/fault/disable (PASS/FAIL).

Layout Gate (Clamp-Specific Only)

  • Clamp return is referenced to Kelvin source/COM (node documented).
  • Clamp return does not share the critical segment with noisy power return (review PASS/FAIL).
  • Clamp pin (if present) follows datasheet connection and stays within pin current limits (PASS/FAIL).
  • Clamp-related test points exist (TP_G, TP_KS, TP_SW or equivalent).

Owner page: Design Hooks & Pitfalls

Bring-Up Gate (Bring-Up Ready)

  • Worst-case commutation test executed (DPT or equivalent) with dv/dt measured and archived.
  • Temperature sweep executed: cold / room / hot (waveforms archived).
  • Probe sanity confirmed: Kelvin reference, short return, adequate bandwidth (PASS/FAIL).
  • VGS_peak_off < X V at dv/dt = Y kV/µs (PASS/FAIL).
  • No overlap spike > Z A (PASS/FAIL).
  • Clamp engagement timing meets N ns criterion when measurable (PASS/FAIL).

Production Gate (Testable + Auditable)

  • dv/dt stress pattern for functional screening is defined (PASS/FAIL criteria set).
  • Clamp functionality check exists: VGS_peak_off under controlled dv/dt stays < X V.
  • UVLO/fault behavior coverage exists in validation script or production test (PASS/FAIL).
  • Audit package archived: Rreq worksheet, corner mapping, waveforms, and state-table evidence.
Engineering Gates: Design → Layout → Bring-up → Production Design Gate R_req closure VCLAMP_EN State table Hot corner Layout Gate Kelvin return Clamp pin Noisy return Test points Bring-up Gate Worst dv/dt Temp sweep Vgs_peak_off No overlap Production Gate Stress pattern Clamp check UVLO/fault Audit docs Gate discipline: compute R_req → enforce clamp return → validate worst dv/dt → production-screen with auditable criteria All pass/fail metrics use placeholders (X/Y/Z/N) to be filled per platform and risk level
H2-11 · Applications & IC Selection

Applications & IC Selection for Active Miller Clamp

This section is a “close-the-loop” map: where an active Miller clamp is must-have, and how to filter gate-driver ICs using standardized, transferable criteria (strength, threshold, timing/state behavior, and isolation/CMTI tie-ins).

1) Application Mapping: Must-have vs Recommended vs Optional

Must-have

Trigger condition: very high dv/dt + high cost of a single false turn-on (shoot-through, EMI burst, unexplained trips).

  • SiC/GaN hard-switching half-bridges (high dv/dt spikes stressing the OFF-side during deadtime)
  • High dv/dt motor drives / servo inverters (repeated deadtime windows + noisy commutation nodes)
  • Traction / PV-ESS / high-power PFC bridges (energy level makes a rare event unacceptable)
  • Multi-bridge or paralleled legs (system-level coupling makes failures sporadic and hard to reproduce)

Strongly recommended

Trigger condition: dv/dt peaks vary with harness, busbar geometry, temperature, or operating mode.

  • Platforms with field variability (lab pass but system fail due to higher dv/dt or different coupling)
  • Designs with hot-corner sensitivity (clamp strength derates, Vth shifts, margins shrink)
  • Any leg where OFF-side gate impedance must stay moderate for EMI control (clamp reduces pressure to push Rg_off too low)

Optional (only with quantified closure)

Optional only if worst-case dv/dt is intentionally controlled and a closed-loop check confirms: R_clamp_eq(hot) ≤ R_req and Vgs_peak_off stays below the chosen off-margin across the dv/dt event.

2) IC Selection Filters (Standardized Criteria)

Must-pass

  • Clamp strength closes the dv/dt loop: compute R_req from dv/dt & Cgd_eff & allowed ΔV, then require R_clamp_eq(hot) ≤ R_req.
  • Clamp enable threshold fits the off strategy: V_CLAMP_EN must engage after the gate falls below the safe region (avoid slowing turn-off) and still cover the dv/dt stress window.
  • Timing/state behavior is defined: clamp on/off timing, blanking, and behavior under UVLO / FAULT / DISABLE must match the protection philosophy.
  • Vgs limits & reference compatibility: confirm clamp reference (to COM/source or to −V rail) is compatible with the chosen +VG/−VG rails and max Vgs.

Prefer

  • Multi-bridge consistency: low channel-to-channel skew helps avoid “sporadic” false turn-on amplification.
  • Isolated stages: high CMTI and a clean clamp return reference reduce common-mode coupling into the gate loop.
  • Observability: a clamp pin or clear clamp status definition simplifies bring-up and production screening.
Selection rule of thumb: treat “active Miller clamp” as a quantified sink path for Miller current. If datasheet clamp numbers are given at room temperature only, use hot-corner assumptions before declaring pass.

3) Example Part Numbers (Active Miller Clamp Included)

The following devices are commonly used as “baseline candidates” when an active Miller clamp is required. Final selection must still pass the standardized filters above (strength, threshold, timing/state, and isolation/CMTI requirements).

Isolated, Single-Channel (SiC / IGBT focus)

  • TI: UCC21710 / UCC21710-Q1 (isolated, internal active Miller clamp, OC/soft turn-off options)
  • TI: UCC21750 / UCC21750-Q1 (isolated, DESAT + internal Miller clamp)
  • TI: UCC21759-Q1 (automotive isolated driver with active Miller clamp and protection set)
  • Analog Devices: ADuM4135 (isolated IGBT gate driver with integrated Miller clamp)
  • Analog Devices: ADuM4146 (isolated SiC gate driver with integrated Miller clamp)

Isolated, Compact / Clamp-Pin Style

  • Infineon: 1ED020I12-F2 (isolated 1200 V-class driver family entry with active Miller clamp)
  • Infineon: 1EDI20I12MF (EiceDRIVER™ compact isolated driver with active Miller clamp)
  • STMicroelectronics: STGAP2S (isolated single driver with Miller clamp function)
  • STMicroelectronics: STGAP2HD (isolated dual driver; includes Miller clamp function)
What to confirm per datasheet: V_CLAMP_EN (typ/min/max), clamp sink capability vs temperature, clamp engagement timing/blanking, and clamp behavior in UVLO/fault/disable states.

4) Mini Decision Rules (If → Then) + Owner-Page Link Map

Mini rules (replace X/Y/N with project values)

  • If dv/dt_worst ≥ X kV/µs → require R_clamp_eq(hot) ≤ R_req (quantified closure).
  • If −VGOFF is used → verify clamp reference and Vgs limits are compatible with the negative rail.
  • If two-level turn-off is used → ensure clamp enables after the shaping region (threshold alignment).
  • If multi-bridge PWM is used → enforce skew ≤ N ns (avoid sporadic amplification across legs).
  • If isolated driver is used → enforce CMTI ≥ Y kV/µs and a stable clamp return reference.

Owner-page link map (replace URLs)

Illustration: Scenario × Requirement Matrix (Clamp-driven)

A compact matrix to decide where clamp strength/threshold/timing/isolation are the dominant constraints. Symbols: ✓ Must · ◐ Recommended · ○ Optional

Active Miller Clamp Scenario Matrix Matrix of application scenarios versus clamp-related requirements: strength, threshold, timing-state, isolation-CMTI. Scenario × Requirement Matrix ✓ Must · ◐ Recommended · ○ Optional Requirements Strength Threshold Timing/State Isolation/CMTI Scenarios SiC/GaN Hard-Switch HB Motor Drive / Servo Traction Inverter PV / ESS Inverters PFC Bridge (Hard-Switch) Multi-Bridge / Parallel Legs Isolated Gate Driver Stage ✓ ✓ ✓ ◐ ✓ ✓ ◐ ◐ ✓ ✓ ✓ ✓ ✓ ◐ ◐ ✓ ✓ ◐ ◐ ◐ ✓ ◐ ✓ ◐ ◐ ◐ ✓ ✓
Use this matrix to decide what dominates the filter: clamp strength closure (R_req), threshold alignment (V_CLAMP_EN), timing/state behavior (UVLO/FAULT), and isolation/CMTI coupling robustness.

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H2-12 · FAQs (Fixed 4-line Answers + JSON-LD)

FAQs: Active Miller Clamp (Field Debug & Review Criteria)

Each FAQ is standardized to four lines: Likely cause / Quick check / Fix / Pass criteria. Placeholders X/Y/N define auditable limits without introducing new domains.

Q1False turn-on still happens with clamp—first suspect threshold or clamp strength?

Likely causeClamp not effective during the dv/dt window (V_CLAMP_EN too high / engages late) or clamp sink is too weak at hot corner (R_eq > R_req).

Quick checkCapture Vgs_peak_off during the worst dv/dt event and compare against V_CLAMP_EN timing; recompute R_req and compare to datasheet R_clamp_eq(hot) or I_CLAMP(min,hot).

Fix(1) Verify clamp enable/state in the actual mode (EN/UVLO/FAULT) → (2) align threshold/timing to the dv/dt window → (3) select stronger clamp grade (lower R_eq, higher I_CLAMP) or add −VGOFF for DC margin.

Pass criteriaVgs_peak_off < X V at dv/dt = Y kV/µs (hot corner included), and overlap spike < Z A.

Q2Clamp seems to slow turn-off—did it engage too early or fight Rg_off?

Likely causeClamp engages before the gate has exited the critical discharge region, or clamp/driver-low contention distorts the intended Rg_off shaping.

Quick checkMark the time when Vgs crosses V_CLAMP_EN and compare the dVgs/dt before/after; check if the “knee” aligns with clamp engagement rather than the intended turn-off profile.

Fix(1) Choose clamp threshold/timing that engages after the intended shaping region → (2) adjust Rg_off strategy so clamp is a dv/dt sink, not a shaping element → (3) if two-level turn-off is used, ensure clamp does not clamp during the shaping phase.

Pass criteriaTurn-off loss increase ≤ X% while Vgs_peak_off remains < Y V at dv/dt = Z kV/µs.

Q3Works at room temp, fails hot—what derates first: Iclamp or Vth margin?

Likely causeClamp sink capability derates at hot (I_CLAMP drops / R_eq rises) and Vth shifts reduce allowed ΔV margin simultaneously.

Quick checkRepeat the same dv/dt stress at hot and compare Vgs_peak_off (room vs hot); re-close the loop using hot-corner parameters (R_eq(hot), Vth_min(hot)).

Fix(1) Select clamp based on hot-corner minima → (2) add −VGOFF to increase DC margin if ΔV is limiting → (3) verify UVLO/fault behavior at hot does not disable/release the clamp during stress.

Pass criteriaAt T = X°C, Vgs_peak_off < Y V at dv/dt = Z kV/µs across N repeated commutations.

Q4Only fails at certain bus voltage—Cgd_eff changed or dv/dt increased?

Likely causedv/dt at the switching node increases with Vbus and/or Cgd_eff changes with Vds, raising the injected Miller current beyond the clamp’s effective sink capacity.

Quick checkMeasure dv/dt vs Vbus at the failure point and recompute i_miller; verify Vgs_peak_off scales with dv/dt as expected (indicating a clamp-closure issue, not a random glitch).

Fix(1) Re-size clamp to the worst-case Vbus dv/dt → (2) verify clamp threshold/timing still covers the dv/dt window at that Vbus → (3) if needed, add −VGOFF or adjust off-strategy to widen ΔV margin without breaking protection behavior.

Pass criteriaAcross Vbus = X…Y V, Vgs_peak_off < Z V at measured dv/dt, with no overlap spike > N A.

Q5Gate ringing looks worse after enabling clamp—contention with driver output stage?

Likely causeClamp/driver-low contention or a significant change in effective gate impedance shifts the damping and makes the resonance more visible (not necessarily more energetic).

Quick checkCompare ring frequency and envelope with clamp enabled vs disabled under the same dv/dt and probe reference; check whether peak energy (area under |Vgs|) increases or only the waveform shape changes.

Fix(1) Ensure clamp engages after the intended discharge region → (2) tune off-side damping (Rg_off / bead strategy) so clamp serves as dv/dt sink, not a resonant element → (3) confirm the driver output stage is not being forced into an unintended state by clamp logic.

Pass criteriaVgs ring peak-to-peak ≤ X Vpp and Vgs_peak_off < Y V at dv/dt = Z kV/µs.

Q6Clamp pin waveform is flat—disabled by fault/UVLO state machine?

Likely causeClamp is not enabled in the current mode, or the driver state machine forces clamp off/on behavior during UVLO/FAULT/DISABLE that differs from expectations.

Quick checkCross-check EN, UVLO flags, fault latch/auto-retry state, and the datasheet state table; measure clamp-related pin behavior while toggling only the state (no power stage change).

Fix(1) Correct configuration and ensure the intended clamp enable mode → (2) align protection mode (latch/auto-retry) with clamp behavior requirements → (3) validate clamp engagement under the exact fault/UVLO transitions that occur in-system.

Pass criteriaClamp behavior matches the specified state table in N transitions, and Vgs_peak_off remains < X V during dv/dt stress.

Q7Different boards behave differently—probe artefact or real parasitic path difference?

Likely causeMeasurement reference/probe capacitance creates apparent Vgs spikes, or a real difference in gate loop parasitics changes the effective R_eq path seen by Miller current.

Quick checkStandardize the probe reference to Kelvin source and repeat with the same bandwidth limit and ground method; if the delta persists, compare dv/dt and Vgs_peak_off scaling across boards.

Fix(1) Lock the measurement method as a test standard → (2) re-close R_req vs R_eq using each board’s measured dv/dt → (3) if a true delta exists, screen by the clamp-closure metrics rather than by “looks different.”

Pass criteriaBoard-to-board Vgs_peak_off variation ≤ X V at dv/dt = Y kV/µs using the standardized probe method.

Q8Half-bridge shoot-through spikes appear only during deadtime—clamp timing too late?

Likely causeClamp engages after the critical deadtime dv/dt spike (V_CLAMP_EN too high or t_CLAMP_ON too slow), allowing a transient Vgs rise to cross the effective turn-on threshold.

Quick checkOverlay deadtime window with Vgs waveform and the switching-node dv/dt event; confirm whether Vgs_peak_off occurs before clamp becomes effective.

Fix(1) Adjust threshold/timing so clamp is effective before the deadtime dv/dt spike → (2) increase clamp sink strength if R_eq is limiting → (3) validate no unintended slowdown of turn-off in the non-deadtime region.

Pass criteriaDuring deadtime, Vgs_peak_off < X V at dv/dt = Y kV/µs, with overlap spike < Z A.

Q9With −Vgoff, do you still need clamp—what does each one actually cover?

Likely cause−VGOFF increases static off-margin (DC), while clamp provides a low-impedance transient sink for fast dv/dt Miller current; either one alone may leave a gap depending on the dv/dt spike profile.

Quick checkCompare four cases under the same worst dv/dt: (A) none, (B) clamp only, (C) −V only, (D) both; record Vgs_peak_off and any overlap current spike.

Fix(1) Use −VGOFF when DC margin is limiting or hot-corner Vth shifts dominate → (2) use clamp when short dv/dt spikes dominate → (3) combine when both DC margin and spike sink capacity are needed.

Pass criteriaIn the selected strategy, Vgs_peak_off < X V at dv/dt = Y kV/µs across T = Z°C.

Q10Clamp spec says “X A”, but still fails—what test condition mismatch is common?

Likely causeClamp current is specified at a particular Vgs, pulse width, temperature, or reference condition; real dv/dt events may require higher peak sink or faster effective engagement than the spec implies.

Quick checkNormalize conditions: compare datasheet I_CLAMP/R_eq at the same Vgs and temperature corner used in the test; confirm whether the spec is typical vs minimum and whether it is a pulsed rating.

Fix(1) Use minimum/hot-corner values for closure (not typical/room) → (2) close with R_req vs R_eq rather than a single “X A” number → (3) if the dv/dt spike is ultra-fast, prioritize t_CLAMP_ON and effective impedance.

Pass criteriaUsing normalized conditions, R_clamp_eq(hot) ≤ X Ω (placeholder), and Vgs_peak_off < Y V at dv/dt = Z kV/µs.

Q11How to set pass criteria for “Vgs_peak_off”—what margin to Vth is acceptable?

Likely causePass criteria is ambiguous when Vth has wide tolerance and shifts with temperature; without a defined Vth_min corner and margin, “pass/fail” becomes subjective.

Quick checkDefine Vth_min at the worst corner used for safety review, then define a fixed margin band; verify the measurement reference and bandwidth are standardized so Vgs_peak_off is comparable.

Fix(1) Set Vgs_peak_off_limit = Vth_min_corner − Margin (Margin recorded) → (2) require the limit under worst dv/dt and temperature → (3) use the same probe reference (Kelvin) and bandwidth across all reviews.

Pass criteriaVgs_peak_off ≤ X V where X = Vth_min_corner − Margin, tested at dv/dt = Y kV/µs and T = Z°C.

Q12Clamp helps EMI but increases loss—what knob to turn first without breaking safety?

Likely causeClamp is participating in the turn-off shaping (engages too early), which can increase switching loss even though dv/dt-related EMI improves.

Quick checkSweep only one knob at a time: clamp enable alignment (threshold/timing) first, then off-shaping (Rg_off / two-level profile), while holding dv/dt stress and measurement method constant.

Fix(1) Keep clamp dedicated to dv/dt spikes by delaying/aligning engagement → (2) use off-shaping knobs for EMI control and clamp for safety margin → (3) if DC margin is needed, add −VGOFF so clamp strength can be sized without increasing loss.

Pass criteriaEMI margin ≥ X dB with loss increase ≤ Y%, and Vgs_peak_off remains < Z V at dv/dt = N kV/µs.

Measurement standard (required for disputes): Use a Kelvin-source reference for Vgs, keep probe return short, record bandwidth limit, and always report the stress condition (dv/dt, Vbus, load current, temperature). Without this, Vgs_peak_off comparisons are not auditable.

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