Synchronous Rectifier Driver ICs: Flyback & LLC Secondary
Definition & Scope Guard
Definition (engineering): A secondary-side synchronous rectifier (SR) driver/controller detects a valid conduction window on the secondary rectification path and drives SR MOSFET gates to replace diode rectification, improving efficiency only when reverse-conduction is actively prevented.
- Taxonomy of SR sensing inputs and the failure modes each one is vulnerable to.
- Engineering criteria for safe turn-on/turn-off with reverse-conduction prevention.
- Bias/UVLO readiness checks for bootstrap’d or secondary-powered SR drive.
- Bring-up probes (where to measure) and pass/fail criteria placeholders for validation and production.
Vds sensing
What it uses: MOSFET VDS and/or body-diode conduction signature.
Strength: direct “conduction opportunity” detection.
Primary risk: ringing and dv/dt injection corrupt the sense edge → false turn-on.
Current sensing
What it uses: secondary current proxy (shunt, sense FET, or inferred current direction).
Strength: explicit reverse-current awareness.
Primary risk: noise/offset drift shifts thresholds → late turn-off or missed conduction window.
Timing / winding cues
What it uses: transformer/aux timing cues to open a gate window.
Strength: immunity to some Vds ringing patterns.
Primary risk: load-mode changes (DCM/CCM/burst) shift the valid window → reverse conduction risk.
- Flyback secondary: single-ended SR, center-tap SR, and full-wave SR (secondary window varies by load mode).
- LLC secondary: SR window is strongly timing-sensitive; reverse conduction can directly disturb tank energy flow.
- Common requirement: every SR implementation must guarantee a clean sensing reference and a deterministic turn-off condition.
Where SR Drivers Win (Loss Map & Use Cases)
- SR wins when diode conduction loss dominates: low Vout + high Iout and long conduction windows.
- SR fails when timing/sensing integrity is weak: false turn-on, late turn-off, or reverse conduction penalties erase conduction gains.
- SR becomes risky at very light load (burst/skip/DCM transitions): bias refresh and decision thresholds must remain deterministic.
Conduction loss (the main reason SR exists)
Diode rectification: P ≈ Vf · Iavg (dominant at low Vout, high Iout).
SR MOSFET: P ≈ Irms² · Rds(on) · D (dominant term shifts to copper + MOSFET).
Engineering meaning: the conduction gain is real, but only if switching/timing penalties are kept smaller than the gain.
Switching + control overhead (the part that can erase the gain)
Gate-drive energy, transition overlap, and decision overhead appear with SR.
Bad windows add a penalty term: Ppenalty = reverse / false-on / ringing (placeholder).
Engineering meaning: SR efficiency is a timing problem first, a silicon Rds(on) problem second.
Use SR when
• Vout is low and Iout is high.
• Diode temperature rise is a limiting factor.
• Layout can guarantee clean Vds/current sensing reference.
Be careful when
• Light-load burst/skip is frequent.
• Secondary ringing/dv/dt is large.
• Output harness/return paths inject ground bounce into sensing.
Skip SR when
• Ultra-light-load efficiency dominates and refresh cannot be guaranteed.
• Cost/complexity budget cannot support tuning and validation.
• Reverse-conduction risk cannot be verified with production tests.
- Load profile: is the efficiency target driven by heavy load, or by light-load standby?
- Waveform stability: is the secondary window stable across DCM/CCM/burst transitions?
- Sensing integrity: can Vds/current sensing be Kelvin-clean and immune to dv/dt injection?
- Bias readiness: can bootstrap/secondary bias remain above UVLO with refresh margin at light load?
- Verification plan: can reverse conduction and false turn-on be detected as a production gate?
Measurements (bring-up)
• Probe VGS, VDS, and bias node (bootstrap/aux) across load steps.
• Confirm turn-off is deterministic (no late-off tail and no reverse current window).
• Confirm ringing does not create extra false-on edges during dv/dt events.
Pass criteria (placeholders)
• Efficiency improvement at rated load: ≥ X%.
• SR device temperature reduction at rated load: ≥ Y°C.
• Reverse-conduction events per minute: ≤ N (target: 0).
Secondary Waveforms You Must Respect (Flyback/LLC)
SR success is defined by secondary-side waveform windows. The goal is not to “understand every topology,” but to locate three engineering regions that must remain consistent across load modes: Turn-on allowed, Must turn-off, and Ringing danger.
Window summary
The SR MOSFET must conduct only during the energy transfer interval. After commutation, secondary ringing can create false VDS edges that mimic conduction opportunity.
Three regions (must be identified)
Turn-on allowed: body-diode conduction signature is valid and stable.
Must turn-off: current approaches zero / polarity reversal begins.
Ringing danger: post-turn-off oscillation crosses thresholds repeatedly.
Top risks (3)
1) Ringing false-on: Vds threshold crossings during oscillation trigger extra switching.
2) Late turn-off: tail conduction causes reverse current and extra heat.
3) Burst instability: valid windows disappear and reappear while bias refresh is limited.
Quick verification + pass placeholders
Probe: VGS, VDS, and a secondary current proxy.
Pass: false-on events ≤ N/min; reverse window ≤ X ns; bias droop ≤ Y V.
Window summary
In LLC, SR timing errors can rewrite the energy path: a wrong conduction interval can cause backfeed and waveform distortion, reducing efficiency and increasing EMI sensitivity.
Three regions (must be identified)
Turn-on allowed: secondary conduction interval is aligned to the intended commutation window.
Must turn-off: current reversal boundary; continuing conduction invites backfeed.
Ringing danger: dv/dt and tank-related oscillations corrupt Vds edges near boundaries.
Top risks (3)
1) Energy stealing: early/false-on conducts in a non-beneficial interval → extra loss.
2) Backfeed: late-off sustains reverse current → heating and degraded waveforms.
3) Light-load drift: skip/burst changes the valid window position and duration.
Quick verification + pass placeholders
Probe: VGS, VDS, and current direction proxy near zero-cross.
Pass: no sustained reverse conduction; boundary jitter ≤ X ns; event count ≤ N.
Turn-On / Turn-Off Criteria (Reverse-Conduction Logic)
SR product differentiation is dominated by decision logic: how conduction opportunity is detected, how noise is rejected, and how reverse conduction is prevented under ringing, dv/dt events, and load-mode transitions.
Priority rules (engineering safety order)
• Anti-reverse protection has priority over efficiency.
• Deterministic turn-off is more critical than early turn-on.
• When the signal is ambiguous (ringing/dv/dt), conservative gating is required (delay, limit window, or lockout).
Sensing signal
• VDS drop / body-diode signature
• Current proxy or timing gate (optional)
Most vulnerable to: ringing threshold crossings.
Tuning knob
• Threshold: sets the trigger line
• Blanking / filter: rejects post-switch noise
• Window enable (timing cue), if available
Failure symptom
• Extra switching events at light load
• Efficiency drops and SR devices warm up unexpectedly
• EMI worsens due to false-on edges
Pass criteria (placeholders)
• False-on events ≤ N/min
• Turn-on occurs only in allowed window (H2-3)
• Bias remains above UVLO by Y V
Sensing signal
• Zero-current / direction cues
• VDS reversal / rise indicating conduction opportunity ends
Most vulnerable to: dv/dt injected offsets near boundary.
Tuning knob
• Min on-time: avoids chatter in noisy zones
• Min off-time: blocks rapid re-trigger
• Boundary filter / blanking near zero-cross
Failure symptom
• Late-off: reverse current, heating, waveform distortion
• Early-off: diode resumes conduction, efficiency gain shrinks
• Instability under DCM/CCM/burst transitions
Pass criteria (placeholders)
• Reverse conduction window ≤ X ns (target: 0)
• Turn-off boundary jitter ≤ X ns
• Thermal delta across SR devices ≤ Y°C
Sensing signal
• Direction cues / boundary monitors
• Internal “allowed window” gating when supported
Most vulnerable to: ambiguous sense reference (non-Kelvin).
Tuning knob
• Conservative gating policy: delay / limit window
• Lockout thresholds and retry policy
• Fault reporting enable / latch vs retry
Failure symptom
• Backfeed signatures under load release
• “Random” faults during dv/dt or ringing bursts
• One SR device runs hotter due to asymmetry
Pass criteria (placeholders)
• Sustained reverse current: 0
• Fault-to-safe reaction time ≤ X µs
• Recovery behavior stable (no oscillation) within Y cycles
- Ringing crossings: VDS crosses thresholds multiple times in the danger zone → false turn-on.
- dv/dt injection: comparator input/reference shifts near boundaries → effective threshold drift.
- Non-Kelvin sense: sensed VDS is not the device VDS → wrong decisions.
- Mode transitions: DCM/CCM/burst moves the valid window → timing gates and filters must remain deterministic.
Drive Architectures (Bootstrap’d / Self-Powered / Hybrid Bias)
SR drivers also depend on a bias supply referenced to the SR MOSFET source. The architecture choice determines startup behavior, light-load robustness, and how likely the bias rail is to dip into UVLO or get contaminated by dv/dt noise.
Core distinction (SR context)
• The gate-drive supply must remain stable relative to the SR MOSFET source (preferably Kelvin-referenced).
• The main failure patterns are not “topology issues,” but bias droop, UVLO chatter, and noise-coupled mis-detection.
Bootstrap’d SR
Where it fits: regular conduction opportunities exist to refresh bias; light-load is not dominated by long idle gaps.
Main risks: light-load/burst refresh shortage → Vboot droop; dv/dt and ringing inject noise into the bias node.
Must measure: Vboot(min) vs UVLO-off, Vgs amplitude shrink, false-on event count ≤ N.
Self-Powered / Aux Bias
Where it fits: an auxiliary winding or secondary supply can maintain bias independent of short conduction gaps.
Main risks: aux voltage window narrows at light load; bias ripple/spikes shift effective thresholds and trigger chatter near UVLO.
Must measure: Vbias ripple + spikes timing, UVLO stability, turn-off determinism under mode transitions.
Hybrid (Bootstrap start + Aux/Integrated steady)
Where it fits: startup requires bootstrap assistance but steady-state needs robust light-load bias retention.
Main risks: handover discontinuity (bootstrap→aux) creates brief undervoltage or spikes; two paths can interact via recovery/dv/dt.
Must measure: handover Vbias continuity (no dip/spike), reverse/false events ≤ N, stable recovery within Y cycles.
- Startup reliability: how quickly bias reaches a valid gate-drive amplitude without chatter.
- Light-load retention: how well bias survives burst/skip idle gaps without crossing UVLO-off.
- Noise immunity: how strongly dv/dt and ringing couple into the bias rail and sense references.
- Cost/volume: external parts and routing complexity versus integrated bias options.
Bootstrap & Bias Design (Cboot, Refresh, UVLO)
Bootstrap and bias design must be treated as an executable workflow: define allowable bias droop, size the charge reservoir, validate refresh under burst/light-load, and verify UVLO behavior does not cause half-conduction or chatter.
Formula card (generic sizing form)
Cboot sizing (placeholder form):
Cboot ≥ (Qg_total + Iq·Ton + leakage_margin) / ΔV
Design goal: Vboot(min) must stay above UVLO_off by Y V in all modes.
Variable meanings (engineering intent)
Qg_total: total gate charge demanded per conduction event (including path losses).
Iq·Ton: driver quiescent charge draw during the ON window.
leakage_margin: leakage + temperature drift reserve for diode/cap/bias network.
ΔV: allowed bias droop (still keeping valid Vgs above minimum requirement).
Bias droop
Symptom: Vboot slowly decays at light load, then SR abruptly disables.
Likely cause: refresh opportunities are too sparse (burst/skip) or Cboot is undersized.
First check: confirm Vboot(min) never crosses UVLO_off.
UVLO chatter
Symptom: repeated enable/disable near threshold; extra switching events and unexpected heating.
Likely cause: insufficient hysteresis or noise spikes around UVLO boundaries.
First check: correlate UVLO transitions with Vgs truncation and event counters.
Bias noise injection
Symptom: false-on/false-off events align with dv/dt edges or diode recovery moments.
Likely cause: recovery spikes and dv/dt couple into bias/reference → effective threshold drift.
First check: observe Vbias spikes timing versus decision edges.
Scope probes (minimum set)
• Gate: Vgs amplitude + abnormal pulses in ringing zones.
• Bias: Vboot/Vbias min, ripple, spikes, and UVLO boundary crossings.
• Device: Vds behavior near zero-cross and in ringing danger zone.
Pass criteria (placeholders)
• Vboot_min ≥ UVLO_off + Y V across load modes.
• False-on events ≤ N/min; sustained reverse current = 0.
• Boundary jitter ≤ X ns; recovery stable within Y cycles.
Protection & Control (gm Protection, Reverse Current, Fault Paths)
SR protection must be specified as a closed behavior loop: what triggers it, what the gate does, how it is observed, and what “pass” means in verification. SR-specific risks are dominated by reverse current (backfeed), mis-timed conduction, and unstable recovery.
Scope guard (SR context)
• This section defines protection trigger → gate action → fault reporting → recovery.
• Turn-on/turn-off criteria details belong to H2-4; bias sizing/refresh belongs to H2-6; layout implementation belongs to later layout sections.
gm protection (behavioral)
Trigger: suspected wrong conduction window or reverse-current tendency (conceptual detection).
Quick check: Vgs shows controlled limiting (slew/clip/soft-off) when the event occurs; reverse signature is reduced.
Fix: increase anti-reverse conservatism (blanking/lockout); enable soft turn-off / clamp behavior if configurable.
Pass criteria: reverse peak ≤ X; sustained reverse current = 0; protection action delay ≤ Y µs.
Reverse current limiting / turn-off enforcement
Trigger: boundary cues indicating current reversal (e.g., Vds rise/reversal) beyond a safe window.
Quick check: no prolonged conduction after the reversal boundary; Vds and current proxy align with “must-off” zone.
Fix: tighten boundary timing (adaptive deadtime / min-off); add lockout after turn-off to block re-trigger in ringing zones.
Pass criteria: reverse window ≤ X ns; false re-trigger ≤ N/min; stable recovery within Y cycles.
Fault reporting & recovery (/FLT, latch vs auto-retry)
Trigger: protection event, UVLO/OTP event, or internal abnormal detection (device dependent).
Quick check: /FLT transitions correlate with gate going safe; auto-retry does not create repeated oscillation.
Fix: select latch vs retry policy; enforce a cooldown (retry period) and a clean reset condition.
Pass criteria: fault-to-safe ≤ X µs; retry period ≥ Y ms; no “retry storm” under burst conditions.
OTP / UVLO / short detection (if supported)
Trigger: temperature threshold, bias rail below UVLO-off, or abnormal event beyond blanking.
Quick check: gate remains in a safe state during the fault window; no chatter near thresholds.
Fix: increase hysteresis margin (system-level), reduce bias ripple/spikes, and align blanking with dv/dt/ringing zones.
Pass criteria: response time ≤ X ns/µs; UVLO chatter count ≤ N; recovery is deterministic within Y cycles.
Timing & Dynamics (Blanking, Adaptive Deadtime, dv/dt Immunity)
SR efficiency gain is fundamentally a timing gain. Incorrect timing converts gain into reverse current, ringing-triggered false events, and EMI risk. This section maps symptoms to knobs and verification targets.
Scope guard (SR timing only)
• Focus is secondary-side timing windows and dynamics knobs (blanking, deadtime, shaping).
• Primary PWM/control-loop algorithms are out of scope; layout details are covered in later layout sections.
Blanking / filter
Symptom: false-on or false-off in ringing zones; efficiency drops at light load.
Likely cause: threshold crossings during ringing; dv/dt injection near boundary.
Knob to turn: blanking time, filter strength, boundary margin (more conservative near danger zone).
How to verify: false events ≤ N/min; reverse window ≤ X ns; stable across modes.
Adaptive deadtime (secondary window)
Symptom: late turn-on loses gain; early turn-on risks backfeed and waveform distortion.
Likely cause: window shifts with load/temperature/mode transitions (DCM/CCM/burst).
Knob to turn: window tracking policy (conceptual), min-on/min-off, lockout after turn-off.
How to verify: conduction stays inside allowed window; no sustained reverse conduction; thermal delta ≤ Y°C.
dv/dt immunity (why sensing gets injected)
Symptom: sporadic faults or timing errors only during fast edges; “random” chatter at specific dv/dt.
Likely cause: sense/reference nodes are lifted by common-mode transients; effective thresholds drift.
Knob to turn: strengthen rejection (blanking/filter), enforce conservative lockout, prefer robust input path where available.
How to verify: under dv/dt stress, false events ≤ N; fault reporting remains deterministic.
Gate shaping (limit spikes, avoid backfeed)
Symptom: EMI peaks, strong ringing, reverse current spikes at turn-off boundary.
Likely cause: edge rate excites parasitics; hard turn-off overshoots and injects noise into sensing.
Knob to turn: slew limiting, soft turn-off, two-step behavior (conceptual), clamp/limit assistance.
How to verify: reverse peak ≤ X; ringing amplitude reduces; no additional false events introduced.
Layout & Sensing Integrity (Vds Sense, Kelvin, Noise Paths)
SR timing quality depends on what the comparator actually sees. The most common field failures come from Vds sense corruption, reference (Kelvin) bounce, and gate-loop ringing that injects noise into the decision path. This section covers SR-specific layout rules only.
Scope guard (SR layout only)
• Focus: Vds sense, Kelvin source/reference integrity, SR gate loop, and the dominant noise-coupling path.
• General power-stage layout, magnetics, and EMI “full ruleset” are out of scope here.
Red line #1: Vds sense must be device-referenced
Sense must represent the MOSFET’s real Vds, not a point polluted by high-current copper drop or shared return inductance.
Pass criteria: sense-vs-device edge alignment drift ≤ X; mis-trigger ≤ N/min.
Red line #2: Reference must be Kelvin-clean
Driver REF/VS must track Kelvin source (not “nearest ground”). Avoid crossing splits and avoid sharing the power return.
Pass criteria: REF bounce at edges ≤ X mV; UVLO chatter count ≤ N.
Red line #3: Gate loop must be minimal
Minimize the gate-drive loop area; place Rg (and optional bead) by loop definition, not by convenience.
Pass criteria: Vgs ringing p-p ≤ X V; no multi-trigger artifacts.
Best practice #1: Route sensing to control injection
Differential: pair routing, same reference, short and symmetric.
Single-ended: define REF explicitly (Kelvin source) and keep the return isolated from power current.
Goal: make injected noise appear as common-mode, not differential error.
Best practice #2: Gate shaping elements with boundaries
Rg placement: close to the gate loop to damp ringing without degrading safe turn-off.
Ferrite bead: only if the dominant issue is high-frequency ringing and turn-off safety is verified.
Verify: shaping must not increase reverse spikes or false events.
Best practice #3: Break the dominant coupling path first
Priority: geometry and reference integrity before “more filtering.”
Typical path: SW node dv/dt → parasitic C → sense trace → comparator.
Action: distance, shield-by-reference, and controlled return.
TP-A: MOSFET Vds (device-side)
Probe: close to SR MOSFET terminals.
Observe: ringing zone and boundary stability.
Pass: boundary is repeatable within X ns.
TP-B: Comparator / sense pin input
Probe: at the driver sense input.
Observe: spikes and phase mismatch vs TP-A.
Pass: injection spikes ≤ X mV; no false crossings.
TP-C: REF/VS vs Kelvin source
Probe: driver reference relative to Kelvin source.
Observe: edge-correlated bounce.
Pass: bounce ≤ X mV; chatter ≤ N.
Design Checklist (Design → Bring-Up → Production)
This checklist turns SR driver integration into a deliverable workflow. Each gate item is written as What to do → Evidence → Pass criteria with placeholders (X/Y/N) to standardize review and acceptance.
Goal
Lock boundary assumptions before hardware validation: bias availability, anti-reverse policy, protection behaviors, and SR-specific layout constraints.
Bias architecture decision
What to do: pick bootstrap/aux/hybrid and write the mode boundary (burst/light-load) explicitly.
Evidence: architecture note + waveform expectations.
Pass criteria: bias available across modes; Vboot_min ≥ UVLO_off + Y V.
Anti-reverse stance
What to do: define conservatism (prefer late-on over false-on) for reverse-risk conditions.
Evidence: criteria policy note + expected boundary behavior.
Pass criteria: sustained reverse current = 0; reverse peak ≤ X.
Protection behavior mapping
What to do: define gate action (soft-off/clamp/latch/retry) per fault category.
Evidence: protection table (behavior-level).
Pass criteria: fault-to-safe ≤ X µs; retry period ≥ Y ms.
SR layout constraints
What to do: enforce Vds sense + Kelvin reference and minimal gate loop as layout constraints.
Evidence: layout checklist sign-off.
Pass criteria: REF bounce ≤ X mV; Vgs ringing p-p ≤ X V.
Goal
Validate that what the SR driver decides matches device reality, then confirm no reverse conduction under mode transitions.
Vgs integrity first
What to do: confirm Vgs amplitude and no abnormal pulses across load modes.
Evidence: scope captures (Gate + Bias).
Pass criteria: Vboot never crosses UVLO-off; false events ≤ N/min.
Sense truthfulness (TP-A vs TP-B)
What to do: compare device-side Vds to sense-pin waveform and check for injected spikes.
Evidence: TP-A/TP-B overlays.
Pass criteria: no false crossings; alignment drift ≤ X ns.
No reverse conduction under transitions
What to do: sweep DCM/CCM boundaries and burst/skip transitions.
Evidence: reverse proxy capture + thermal observation.
Pass criteria: sustained reverse = 0; reverse peak ≤ X.
Deterministic recovery
What to do: observe /FLT behavior and gate safe-state under induced boundary stress.
Evidence: fault pin timing captures.
Pass criteria: fault-to-safe ≤ X µs; stable recovery within Y cycles.
Goal
Standardize fault injection, consistency checks, and documentation so acceptance does not depend on subjective interpretation.
Fault injection set
What to do: run short/UVLO/brownout/light-load burst stress with safe-gate verification.
Evidence: pass/fail logs + representative captures.
Pass criteria: safe gate enforced; no uncontrolled reverse events; response time ≤ X.
Consistency metrics
What to do: verify event counts and boundary stability across units and temperatures.
Evidence: counters log + statistical summary.
Pass criteria: false events ≤ N; boundary jitter ≤ X ns.
Documentation pack
What to do: freeze thresholds, fault policies (latch/retry), and scope evidence templates.
Evidence: criteria sheet + test checklist + revision control.
Pass criteria: all X/Y/N placeholders resolved and reviewed.
EMC precheck alignment
What to do: record spikes/ringing changes after timing/shaping adjustments.
Evidence: before/after captures.
Pass criteria: spike amplitude reduced; no new false events introduced.
Applications (Flyback, LLC Secondary, PSFB Secondary)
This section is application playbooks only: when SR makes sense, top SR-specific risks, key knobs, and what to measure. Topology fundamentals and primary-side control are out of scope.
Flyback Secondary SR Playbook
When to use: low-voltage / high-current outputs where diode loss dominates; efficiency or thermal headroom is tight.
Top risk: post-conduction ringing causing false turn-on; light-load burst starving bias refresh and triggering UVLO chatter.
Key knobs: blanking/filter, min on/off, lockout, conservative anti-reverse.
What to measure: Gate (Vgs), device-side Vds, sense-pin waveform, REF/Kelvin bounce; sweep DCM↔CCM and burst/skip transitions.
Pass criteria: false events ≤ N/min; reverse sustained = 0; UVLO chatter ≤ N.
LLC Secondary SR Playbook
When to use: higher power density designs where SR must minimize body-diode conduction while staying stable across operating points.
Top risk: timing errors become reverse / backfeed quickly; dv/dt injection into sensing can create mis-triggers at fast edges.
Key knobs: adaptive timing, adjustable turn-off threshold, min on/off, robust anti-bounce, controlled turn-off (soft/linear if available).
What to measure: reverse proxies at worst-case dv/dt points; thermal symmetry; boundary stability across load and switching-frequency excursions.
Pass criteria: reverse sustained = 0; reverse peak ≤ X; false events ≤ N/min.
PSFB Secondary SR Playbook (Secondary-side view)
When to use: outputs where diode loss and heat are dominant, and the SR window remains repeatable under commanded transitions.
Top risk: window boundaries shift with operating conditions; false events can appear during fast load steps or mode changes.
Key knobs: sync/CCM coordination (if supported), blanking, min on/off, lockout, deterministic fault policy (latch vs retry).
What to measure: same 3-point discipline: device-side Vds vs sense-pin, REF/Kelvin bounce, and gate integrity through transitions.
Pass criteria: commanded transitions do not introduce new false events; fault-to-safe ≤ Y µs.
IC Selection Logic (Key Specs, Fit Tests, Part Buckets)
The goal is fast fit screening without turning into a generic spec encyclopedia. Keep only SR-bound items: sensing method, reverse handling, bias robustness, timing knobs, gate capability, and protection behavior.
Fit Test (6 questions that decide the bucket)
Each question is a decision gate. Any mismatch should stop selection before tuning details.
Q1 · Topology / secondary structure
Choose: Flyback / LLC / PSFB; center-tap vs full-wave.
Outcome: single-channel vs dual-channel SR, and window style.
Pass criteria: controller supports the required channel count and sensing pins.
Q2 · Light-load mode reality
Choose: burst / skip / DCM / CCM transitions.
Outcome: bias refresh capability and false-trigger resistance requirements.
Pass criteria: no UVLO chatter; false events ≤ N/min in light-load mode.
Q3 · Reverse risk tolerance
Choose: absolute no-backfeed vs limited peak allowed.
Outcome: conservative anti-reverse logic and fast turn-off needs.
Pass criteria: sustained reverse = 0; peak ≤ X.
Q4 · Noise / dv/dt environment
Choose: high dv/dt + ringing vs clean sensing layout budget.
Outcome: sensing method (Vds / current / hybrid), min on/off, ringing detection.
Pass criteria: injected spikes do not create false crossings at the sense pin.
Q5 · Protection policy and fault behavior
Choose: latch vs auto-retry; soft turn-off requirement; fault pin behavior.
Outcome: protection feature set and recovery determinism.
Pass criteria: fault-to-safe ≤ Y µs; stable recovery ≤ N cycles.
Q6 · BOM / integration constraints
Choose: external bias allowed vs integrated bias preferred; dual SR outputs needed or not.
Outcome: bucket selection and complexity boundary.
Pass criteria: required external components fit cost/area limits.
SR-bound key specs (what matters, quickly)
Fit rule: each selected IC must provide at least one robust path to prevent false turn-on in ringing zones and must keep reverse behavior bounded by the project pass criteria (X/Y/N).
Part Buckets (examples with concrete part numbers)
These are representative starting points. Always confirm lifecycle/availability, pinout, and the actual secondary waveform set in the target converter.
Bucket A · Flyback, cost-optimized diode replacement
Use when: flyback outputs where ringing is manageable and the priority is simple, efficient diode emulation.
Must-have: robust ringing immunity or filtering/blanking; stable behavior under DCM/QR transitions.
Examples: TI UCC24610, TI UCC24612, Infineon IR1161L, MPS MP6908.
Fit tests: false events ≤ N/min in light-load; reverse sustained = 0.
Bucket B · Versatile SR driver (Flyback + LLC)
Use when: one SR family must cover flyback and LLC variants with tunable min on/off and ringing resistance.
Must-have: adjustable min on/off, strong turn-off behavior, clear fault policy options.
Examples: onsemi NCP4305, onsemi NCP4306, onsemi NCP4304A/B, onsemi NCP4308, TI UCC24612.
Fit tests: sense pin remains clean vs device Vds; lockout prevents retrigger in ringing zones.
Bucket C · LLC, dual SR outputs / center-tap full-wave
Use when: LLC with center-tap secondary and full-wave SR needs two coordinated gate outputs with interlock.
Must-have: dual channels, interlock, fast and stable turn-off near boundary conditions.
Examples: TI UCC24624, ST SRK2001.
Fit tests: no simultaneous conduction; reverse sustained = 0; boundary stability within X ns.
Bucket D · LLC, timing-sensitive / dv/dt-resistant
Use when: the LLC secondary window is highly sensitive and dv/dt injection is a major risk driver.
Must-have: anti-bounce / ringing logic; fast turn-off; controlled turn-off behavior if available.
Examples: Infineon IR11688S, TI UCC24624, onsemi NCP4308, onsemi NCP4306.
Fit tests: false events stay bounded at worst dv/dt; reverse peak ≤ X.
Bucket E · Secondary SR with CCM coordination / sync option
Use when: the SR turn-off must coordinate with commanded CCM operation or primary timing cues.
Must-have: a synchronization/coordination input (when applicable) plus deterministic lockout behavior.
Examples: TI UCC24610 (SYNC), TI UCC24612.
Fit tests: forced turn-off does not create reverse spikes beyond X.
Bucket F · Aggressive ringing environment (min on/off + ringing detection)
Use when: the layout and parasitics create unavoidable ringing and retrigger risk.
Must-have: adjustable min on/off, explicit ringing detection/handling, and stable sense pins under dv/dt.
Examples: onsemi NCP4304A/B, onsemi NCP4308, MPS MP6908 (flyback-focused).
Fit tests: retrigger count ≤ N; sense spikes do not cross thresholds.
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FAQs (Field Troubleshooting & Acceptance)
Scope: field troubleshooting and acceptance criteria only. No new topology theory. Each answer is fixed to 4 lines: Likely cause / Quick check / Fix / Pass criteria (X/Y/N placeholders).
SR efficiency is worse than diode — first suspect timing window or false turn-on?
Likely cause: late turn-on / early turn-off increasing body-diode conduction, or ringing-driven false turn-on causing reverse loss.
Quick check: overlay device-side Vds vs sense-pin waveform and gate; compare “SR on-time” vs conduction window at the same load.
Fix: tune blanking + min on/off + lockout; slow turn-on edge if needed; verify Kelvin reference integrity.
Pass criteria: efficiency improves ≥ X% at load Y; false events ≤ N/min; reverse sustained = 0.
Light-load burst causes SR misfire — refresh/UVLO or sensing noise?
Likely cause: bias refresh starvation during burst/skip leading to UVLO chatter, or dv/dt injection into Vds sense causing false triggers.
Quick check: log Vboot/Vbias minimum vs UVLO_off; count misfires per minute while observing sense-pin spikes during burst edges.
Fix: increase refresh margin (bias/boot path, leakage control), add/adjust lockout in ringing zones, and improve sense routing/reference.
Pass criteria: Vboot_min ≥ UVLO_off + X V; misfire ≤ N/min; UVLO chatter count ≤ N.
Vds sense looks clean but SR still backfeeds — criteria threshold or Kelvin error?
Likely cause: anti-reverse threshold/turn-off criterion too permissive, or Kelvin/reference bounce makes “clean” sense misleading at the decision instant.
Quick check: measure TP-C (REF/VS vs Kelvin source) at switching edges; verify turn-off happens before reverse proxy rises at worst-case dv/dt.
Fix: tighten turn-off criterion / increase conservatism (prefer late-on over false-on), add min off/lockout, and correct Kelvin routing.
Pass criteria: reverse sustained = 0; reverse peak ≤ X; REF bounce ≤ Y mV.
Gate ringing causes secondary shoot-through — Rg placement or loop inductance?
Likely cause: oversized gate loop inductance and/or Rg placed outside the minimal loop, allowing Vgs ringing to cross threshold.
Quick check: probe Vgs at the MOSFET pins; quantify ringing p-p and count any multi-trigger artifacts during edges.
Fix: minimize gate loop area, move Rg to the gate loop, optionally add bead (only after verifying safe turn-off), and re-verify Vds sense immunity.
Pass criteria: Vgs ringing p-p ≤ X V; multi-trigger count ≤ N; no overlap conduction observed.
Bootstrap/bias droops only after warm-up — leakage or diode recovery?
Likely cause: temperature-driven leakage (Cboot path or MOSFET/driver leakage) reducing bias margin, or recovery/dv/dt events injecting loss into the refresh path.
Quick check: compare Vboot_min at cold vs hot steady state; correlate droop with burst intervals and switching edge conditions.
Fix: increase bias/boot margin (cap sizing + refresh opportunity), reduce leakage contributors, and harden the refresh diode/route against dv/dt stress.
Pass criteria: hot Vboot_min ≥ UVLO_off + X V; droop per cycle ≤ Y mV; UVLO events = 0.
/FLT asserts randomly — dv/dt injection or blanking too short?
Likely cause: dv/dt-induced false detection at sense/comparator inputs, or blanking/filters too short for the actual ringing zone.
Quick check: correlate /FLT edges with switching transitions; inspect sense-pin spikes and REF bounce at the same instants.
Fix: extend/adjust blanking and lockout, improve sensing reference integrity, and confirm fault policy (latch vs retry) matches system needs.
Pass criteria: spurious /FLT ≤ N/day; fault-to-safe ≤ X µs; no false turn-on during ringing zone.
LLC passes at room temp but fails hot — threshold drift or Rds(on) effect on sense?
Likely cause: temperature shift moves the effective sensing boundary (threshold drift and/or altered Vds signature from Rds(on)), shrinking window margin.
Quick check: sweep temperature and log the boundary timing error (early/late) plus reverse proxy; compare sense-pin waveform shape vs device-side Vds.
Fix: retune thresholds/blanking for hot corner, increase conservatism for anti-reverse, and correct any layout-driven temperature asymmetry.
Pass criteria: boundary drift ≤ X ns from 25°C to Y°C; reverse sustained = 0; false events ≤ N/min.
EMI got worse after enabling SR — turn-on edge too fast or early conduction?
Likely cause: excessive gate edge rate increasing high-frequency energy, or early turn-on enlarging switching overlap and ringing excitation.
Quick check: compare spectra/spike captures with SR enabled vs disabled; check whether early-on coincides with larger SW node ringing.
Fix: apply gate shaping (Rg/edge control), shift timing away from ringing zone via blanking/min on, and ensure Kelvin/sense routing is not injecting extra noise.
Pass criteria: peak emission at target band reduced ≥ X dB (or no new fails N=0); false events ≤ N/min.
One SR MOSFET runs hotter — mismatch or asymmetrical layout/sense routing?
Likely cause: asymmetrical gate/sense routing or Kelvin reference quality causing different effective timing; device mismatch can amplify the imbalance.
Quick check: compare per-device Vgs/Vds timing and REF bounce; check thermal map under identical load.
Fix: enforce routing symmetry, equalize gate loops, re-anchor sensing to true Kelvin points, and retune timing knobs after symmetry is restored.
Pass criteria: ΔT between devices ≤ X °C at load Y; timing skew ≤ X ns.
Fails only with long output cables — ground bounce into the sense path?
Likely cause: cable-induced return impedance and common-mode currents elevate ground bounce, injecting error into Vds sense and reference.
Quick check: compare TP-C (REF vs Kelvin) with short vs long cable; check whether misfires line up with load transients and edge events.
Fix: harden reference routing (Kelvin), isolate sensitive returns from power returns, and increase immunity via lockout/blanking only after fixing the dominant coupling path.
Pass criteria: REF bounce ≤ X mV with long cable; misfires ≤ N/min; reverse sustained = 0.
SR never turns on (or turns on too late) — threshold too high or blanking too long?
Likely cause: turn-on threshold set too strict, blanking window masks the valid conduction interval, or bias is below the effective enable margin.
Quick check: verify Vboot stays above UVLO; compare expected conduction window vs actual enable timing using device-side Vds and gate.
Fix: relax turn-on threshold, reduce blanking only after confirming ringing zone is controlled, and restore bias headroom if margin is insufficient.
Pass criteria: body-diode conduction time reduced ≥ X%; late-on error ≤ Y ns; false events ≤ N/min.
After a fault, SR keeps flapping — auto-retry policy or lockout window too short?
Likely cause: retry cadence is too aggressive, lockout/min off is too short for the real ringing/settling time, or recovery criteria are not deterministic.
Quick check: record /FLT, gate, and bias during recovery; count retries and correlate with sense retriggers in the ringing zone.
Fix: slow retry rate or switch to latch where required, extend lockout/min off, and ensure recovery starts only after bias and reference are stable.
Pass criteria: retries ≤ N before stable run; recovery stable within Y cycles; no reverse sustained during recovery.
