This section routes symptoms into a three-path root model so troubleshooting starts with the correct victim node: Input, Isolation channel, or Gate injection.

The decision map deliberately uses a minimum observable set to avoid “random knob turning”.

CMTI (Common-Mode Transient Immunity)

CMTI is the ability to maintain the correct logic state during a common-mode voltage transient, for both positive and negative dv/dt. A failure event is any of the following:

• Output flip (wrong state) or a glitch that can be interpreted as a valid edge.
• False fault / false disable (e.g., /FLT toggles without a real fault).
• False turn-on condition caused by gate injection that pushes Vg beyond a safe margin.

The same “dv/dt” label can represent different physical environments. To keep this page auditable, three variables are used:

Typical datasheet CMTI tests approximate a controlled dv/dt_cm condition. System troubleshooting often starts from dv/dt_sw because it is the easiest to measure.

• Polarity gap: only one edge (positive or negative dv/dt) is emphasized; the opposite edge may be worse in the real system.
• State dependency: immunity differs by output state, load, and operating mode; switching conditions can be harsher than static tests.
• Corner conditions: temperature and supply margins (near UVLO) reduce noise margin and increase susceptibility.
• Metric mismatch: CMTI headline values do not automatically translate from dv/dt_cm to dv/dt_sw without validating coupling paths.

Use the following normalized template across design reviews and lab reports:

• dv/dt_env = X kV/µs (worst-case, include +dv/dt and −dv/dt)
• CMTI_req = Y kV/µs (requirement = dv/dt_env + margin)
• victim_node = Input / Isolation / Gate
• noise_margin = N (threshold or allowable glitch / gate bump budget)

dv/dt is not a fixed property of a switch. It is a system outcome set by drive strength, switching conditions, and parasitic networks. The same device can exhibit widely different dv/dt depending on gate-loop inductance, power-loop parasitics, and operating corners.

Define dv/dt_env using a repeatable, auditable extraction method. The objective is a system input that can be referenced in design reviews and lab acceptance.

This section is the page’s mechanism core. It classifies coupling into four orthogonal paths and provides, for each path: victim node, waveform signature, and a first-line mitigation direction.

Each failure mode is expressed as a repeatable mapping: Symptom → Likely path → Probe point → First fix direction → Pass criteria. The goal is to identify the active coupling path before changing gate resistors or adding capacitance.

Under high dv/dt, the driver can fail by misinterpreting inputs, creating spurious edges, losing state, or mis-handling fault pins. Hardening is treated as a chain of blocks. Each block is described by an auditable metric and its trade-off.

Input conditioning protects the interpretation boundary. It absorbs reference motion and rejects short dv/dt-induced glitches before they become valid edges.

• Differential vs single-ended: differential signaling improves common-mode tolerance; single-ended inputs require stronger reference control.
• Hysteresis (Schmitt behavior): increases noise margin against ground bounce and threshold drift.
• Glitch reject / deglitch window: suppresses short pulses but introduces minimum valid pulse width and added propagation delay.

Internal gating ensures that transient disturbances do not become state changes. The focus is on edge qualification and state retention under dv/dt_env.

• Edge qualify: require stable input conditions for a defined qualification window before accepting an edge.
• State hold: prevent momentary disturbances from flipping the interpreted state during high dv/dt intervals.
• Consistency across channels: ensure matching behavior so multi-leg systems do not develop skew or asymmetric susceptibility.

Output robustness is defined by the ability to keep the gate in the intended state under displacement and Miller injection currents. This section states the requirement; detailed clamp and negative-bias implementations are handled elsewhere.

• Hold-down strength: strong pull-down and low impedance reduce sensitivity to injected current.
• Output impedance stability: avoid behavior that changes significantly across temperature and supply corners.
• Predictable off-state margin: define an off-state gate bump budget aligned to the system dv/dt_env.

Fault and enable pins often become the hidden weak link under dv/dt, especially when they are open-drain or high-impedance nodes. Define pull strategies and fail-safe states explicitly.

• /FLT behavior: ensure the pin does not toggle due to dv/dt-induced reference motion; define false trip rate.
• /EN behavior: ensure disable does not assert accidentally; define default safe state if the line is floating.
• Pull-up/down strategy: specify pull strength range and reference grounding so pin thresholds are stable.

Treat driver-side immunity as a block chain. Each block owns a measurable checkpoint (hysteresis, deglitch, edge qualify, hold-down, fail-safe).

Reinforced isolation still includes barrier capacitance (Cbar). Under fast switching edges, a displacement current is injected across the barrier: I = Cbar · dv/dt. The key question is not whether current exists, but where the return loop closes.

Displacement current may return through the isolated bias path, shield/chassis bonds, optional Y-cap connections, or unintended control-ground routes. Immunity depends on providing a short, controlled, low-impedance return loop that does not disturb sensitive references.

A stable order of operations prevents “random knob turning”: Return path control first, then barrier injection reduction, then input threshold margin.

• Gate bump aligned to Vds edges: prioritize Miller clamp or off-state margin methods.
• dv/dt_env is above the target: prioritize split Rg or two-level shaping to control edges.
• Low Vth / high temperature corner sensitivity: add additional off-state margin and confirm with Vg(off) budget.
• Need fast protection but low ringing: prioritize two-level turn-off with an explicit pass window.

CMTI failures are usually loop problems: displacement current and reference motion travel through the easiest return route. The objective is to create short, predictable loops and keep sensitive references inside a quiet control island.

• Minimize loop area: driver output → gate → Kelvin return must be as tight as possible.
• Kelvin source / separate return: gate return should not share the power commutation ground segment.
• Short, direct gate routing: avoid long gate traces that add inductance and amplify gate bump.
• Local driver decoupling: keep driver supply loop compact and referenced to the driver island return.

Bonding changes where the common-mode current closes its loop. The decision is measured by return-loop control, not by “single-point vs multi-point” ideology.

Datasheet CMTI is measured under a specific setup (supply, loading, mode, temperature, and reference definition). System CMTI includes real return loops, parasitics, shield/chassis paths, isolated bias coupling, and fault/enable routing. Any weak link can fail even when the driver CMTI spec looks high.

Use the following template in a test plan, report, or design review. Fill placeholders X/Y/Z/N/M/K.

Test conditions:
- dv/dt_env = X kV/µs (both + and − edges)
- Vbus = Y V, load current = I A, temperature = Z °C
- driver mode = (HS/LS), channel count = (1/2/3)

Pass criteria:
- ISO_OUT: no state flip; no valid-edge glitch wider than M ns under dv/dt_env(+/−)
- Gate: Vg(off) bump < N V and duration < M ns (measured with defined Probe REF)
- Control rails: no reset / brownout; Ctrl Vcc/GND CM step within limit R
- Fault nets (/FLT, /EN): false trip rate < K per 10^6 switching edges

• Start from dv/dt_env: extract worst-case slope and polarity (+/−).
• Rank the risk paths: Input vs Isolation vs Gate (pick the dominant one first).
• Apply the combo list: each step includes a pass criterion placeholder (X/Y/N/M).
• Lock the probe reference: every capture is only comparable with documented Probe REF.

Do-first combo (6 steps)

1. Define dv/dt_env(+/−): extract the steepest edge slope and lock worst-case conditions (Vbus=Y, T=Z).
2. Control the CM return loop first: enforce a short, intended displacement-current loop away from the control island (Ctrl CM step ≤ R).
3. Validate isolation logic integrity: ISO_OUT must not flip; no valid-edge glitch wider than M ns under dv/dt_env(+/−).
4. Validate gate-off immunity: Vg(off) bump peak < N V and width < M ns; correlate with Vsw edges to confirm the path.
5. Check channel consistency: HS/LS propagation skew < S ns under dv/dt_env to prevent leg mismatch.
6. Freeze acceptance wording: write the pass criteria into the report (dv/dt_env, setup, node list, Probe REF).

Do-first combo (6 steps)

1. Mark the hot dv/dt nodes: primary Vsw and SR switching nodes; document the steepest edge window.
2. Lock the victim list: SR sense/drive input, /FLT, /EN, controller rails, and any opto/iso links (if used).
3. Define input-glitch criteria: any glitch < M ns must not become a valid edge (match the lab trigger definition).
4. Gate-off immunity check: Vg(off) bump < N V and < M ns at worst dv/dt; correlate to the hot node edge.
5. Return-path audit: enforce no cross-partition return through the control island (Ctrl CM step ≤ R).
6. Repeatability gate: K edges at worst window → zero false-on / zero false-trip.

Do-first combo (7 steps)

1. Define the edge-density window: the worst simultaneous switching event (phases + load transient).
2. Input noise margin audit: ensure the PWM/EN/PG nets keep noise_margin ≥ Q within that window.
3. Skew acceptance: channel-to-channel skew < S ns under the edge-density condition.
4. Ground bounce control: driver island return must not ride on power-ground bounce; forbid cross-split returns.
5. Fault-net robustness: /FLT and /EN pull strategy must hold a safe default under dv/dt injection.
6. Probe discipline: document Probe REF for PWM in, gate out, and rails to avoid false conclusions.
7. Rate metric: false-trip rate < K per 10^6 edges (production-friendly criterion).

Selection acceptance (fill X/Y/Z/N/M/S/R/K):
- dv/dt_env = X kV/µs (+ and −), Vbus = Y V, T = Z °C
- ISO_OUT: no flip; no valid-edge glitch > M ns
- Gate: Vg(off) bump < N V and < M ns
- Timing: skew < S ns under dv/dt_env
- Rails: Ctrl CM step ≤ R; false-trip rate < K per 10^6 edges

• #1 CMTI (± polarity + conditions): prioritize robustness under documented dv/dt_env(+/−).
• #2 Delay / skew stability: enforce skew < S ns under dv/dt stress.
• #3 Output stage sizing: A_peak must meet Qg/edge target without creating excessive dv/dt injection.
• #4 UVLO + fault path defaults: /FLT and /EN must not false-trigger during switching edges.
• Then package/spacing: treat parasitic capacitance and CM loop closure as first-order, not afterthought.

• Comparing only the kV/µs number: ignoring test mode, loading, polarity, and reference definition.
• Measuring without Probe REF documentation: glitches and CM steps become non-comparable.
• Validating only at room temperature / light load: missing the worst dv/dt window and corners.
• Forgetting “side nets”: /FLT, /EN, /RDY can be the first failure path under dv/dt injection.