Automotive Traction Inverter Gate Driver ICs (ASIL-Ready)
Central idea
In an automotive traction inverter, a gate driver must guarantee a deterministic safe-OFF state through supply transients and high dv/dt, using independent redundant shut-down paths and measurable reaction-time budgets. This page turns ASIL intent into proof-ready design and test criteria for UVLO, fault propagation, controlled turn-off, and validation evidence.
H2-1 · Definition & Scope: Traction Inverter Gate-Driver View
Define the driver-centric boundary: what this page must solve, what it must not expand into, and what “pass” means in review and validation.
Establish a strict boundary for gate-driver IC design and selection in an automotive traction inverter, so the page stays focused on deterministic turn-off, safety evidence, and survivability under automotive power events.
Scope anchor: Traction inverter = DC-link + 3-phase bridge + current sensing + control + gate drivers.
Driver-Centric Coverage (6 chains)
- Signal chain: PWM integrity, input structure, interlock, delay/skew control.
- Power chain: VDD/VISO/isolated bias behavior, UVLO ON/OFF thresholds, brownout-safe states.
- Protection chain: short-circuit reaction budget, controlled turn-off behavior, fault latch/auto-retry policy.
- Isolation chain: dv/dt immunity, common-mode coupling signatures, safe crossing of domains.
- Fault chain: /FLT, /RDY, /DIS paths that remain valid across isolation under stress.
- Verification chain: measurable pass criteria for review, bring-up, and production test.
Deliberately Not Covered
- Motor-control algorithms (FOC/SVPWM details), torque control, observer tuning.
- Vehicle HV architecture, full DC-link design, detailed EMC theory.
- Power module internals and device physics deep-dive (handled by switch-technology pages).
Rule: non-driver domains appear only as interface points (inputs, supplies, fault paths, and validation hooks).
Key Failure Modes (names only, validation viewpoint)
- Shoot-through: same-leg cross-conduction risk; prove interlock + timing margin.
- False turn-on: dv/dt-induced spurious gate rise; prove clamp and immunity paths.
- Short-circuit energy (SC): reaction-time budget vs SOA; prove turn-off within X µs.
- UVLO half-conduction: gate in threshold region; prove clean off-state under brownout.
- Fault propagation across isolation: /FLT or /DIS fails or chatters; prove safe signaling under dv/dt.
Output: a single, review-ready statement of what is in scope, what is out of scope, and which failure signatures must be closed.
H2-2 · System Topology & Where the Driver Sits (3-phase bridge)
Convert the inverter into auditable interfaces: six channels, each with a signal chain, a power chain, and a fault chain.
Decompose the traction inverter into verifiable driver interfaces. Every phase-leg channel must be traceable on a schematic: Signal, Power, and Fault.
Output: a review checklist that can be applied directly to the design database and test plan.
Six Channels, Three Chains Each
- 6 channels: Phase A/B/C × (High-side + Low-side).
- Signal chain: PWM_in → input conditioning → interlock → output drive.
- Power chain: VDD/VISO → UVLO → VG+/VG- rails → gate loop.
- Fault chain: DESAT/OC/OT pins → decision → /FLT report → /DIS enforce.
Symmetry rule: maintain HS/LS within-leg symmetry and phase-to-phase matching to keep timing margins and fault behavior predictable.
Where Non-Driver Domains Touch the Driver
- DC-link ripple/transients → bias stability → UVLO behavior and safe-state entry.
- Phase-node dv/dt → common-mode injection → false turn-on or fault chatter signatures.
- Current sensing (shunt / DESAT) → short-circuit detect budget and blanking needs.
- Bus voltage monitor → supervisory control input (interface only; no control-algorithm expansion).
- Thermal paths → delay/skew drift, UVLO margin drift, and protection thresholds over temperature.
Boundary rule: describe only interfaces and verification hooks, not full system design of the non-driver blocks.
Common Implementations (graded by verification impact)
- Discrete isolator + driver: flexible partitioning; verify domain crossings and skew under dv/dt; watch shared-supply common-cause points.
- Integrated isolated gate driver: tighter timing and fewer crossings; verify CMTI behavior and fail-safe defaults under supply disturbances.
- Driver with integrated isolated bias: simpler high-side power; verify bias survivability under brownout/load-dump and noise isolation vs sensing windows.
Output: pick an architecture that minimizes common-cause failure and preserves deterministic turn-off evidence.
H2-3 · Safety Goals & ASIL Hooks (what the driver must guarantee)
Translate ISO 26262 / ASIL intent into driver-enforceable mechanisms, evidence artifacts, and measurable reaction-time criteria.
Convert abstract safety objectives into a driver-centric contract: force OFF, remain OFF, report fault, and confirm OFF under worst-case conditions.
Safety state definition used across this page: deterministic turn-off with a closed evidence loop.
From Safety Goal to Driver-Readable Requirements
- Safe state: gate drive forced OFF and stays OFF (no half-conduction under brownout).
- Enforcement: a hard disable path (/DIS) that is valid across isolation and independent of PWM.
- Fault visibility: explicit fault reporting (/FLT, status flags) usable by the safety controller.
- Confirm-off: an observable criterion (VG below VSAFE, output state latched, or equivalent).
- Reaction-time budget: detect + decide + turn-off + discharge meets worst-case X µs.
Boundary rule: standard terminology is used only to define the contract; no ISO 26262 process teaching is introduced.
Hooks That Must Be Auditable
- Diagnostic coverage: pins and flags that expose undervoltage, overtemperature, desaturation/OC events.
- Latent fault detection: periodic checks of the safety path (e.g., /DIS effectiveness) and reporting integrity.
- Safe-state enforcement: hardware interlocks and hard-off behavior that do not rely on firmware scheduling.
- Fault reaction-time budget: worst-case timing evidence across temperature, supply variation, and dv/dt stress.
Each hook must link to a measurable pass criterion, not a qualitative statement.
Safety Manual / FMEDA / Diagnostic Pins (how they are used)
- Safety manual: defines allowed operating conditions (supplies, isolation usage, pin states, layout constraints) required for claimed behavior.
- FMEDA references: provides evidence anchors (assumptions and failure modes) used to justify diagnostic hooks and coverage claims.
- Diagnostic pins/flags: enable fault injection and monitoring (e.g., /FLT, RDY, UVLO, OT, DESAT/OC indicators).
Output: an “ASIL → driver mechanisms → pass evidence” list that can be copied into review notes and test plans.
H2-4 · Redundant Turn-Off Architectures (primary + secondary paths)
Make redundancy real: independent triggers, independent energy/discharge capability, independent enforcement paths, and worst-case proof to VG < VSAFE.
Define redundant turn-off as a verifiable architecture: a primary path and a secondary path that remain effective when the other fails, with explicit identification of common-cause points.
Three Independent Dimensions
- Logic redundancy: two independent triggers (PWM domain vs safety domain).
- Energy redundancy: turn-off remains possible with supply disturbance (separate discharge path or bias behavior).
- Path redundancy: a secondary hard-off path independent of the primary control chain.
Anti-pattern: “two inputs” that share the same isolator, supply, or ground reference is not true redundancy.
Worst-Case Proof Requirement
- Primary path disabled: secondary still forces OFF.
- Secondary path disabled: primary still forces OFF.
- Pass criterion: VG falls below VSAFE within X µs (worst-case).
- Worst-case axes: temperature, supply variation, dv/dt stress, and device/driver tolerance.
The budget must be decomposed: Detect (X1) + Decide (X2) + Turn-off (X3) + Discharge to VSAFE (X4).
Common Mechanisms (keep them independent)
- /DIS hard disable: bypasses PWM logic and blocks drive outputs.
- Active pull-down: low-impedance gate discharge under fault and under UVLO scenarios.
- Gate-to-source clamp: prevents dv/dt induced re-turn-on during turn-off and transients.
- Secondary shutdown driver: separate enforcement element for hard-off when the primary path is compromised.
H2-5 · Power Events: Cold-Crank & Load-Dump Strategies (driver/bias survivability)
Convert automotive supply events into deterministic driver behavior: remain OFF under brownout, survive overvoltage energy, and avoid false actions.
Translate cold-crank and load-dump waveforms into a driver-centric contract: OFF-safe behavior, no half-conduction, no spurious switching, and stable fault reporting.
Boundary rule: only driver/bias behavior is specified (UVLO, latch/freeze, reporting, survivability). System power-topology design is out of scope.
Brownout Must Force a Clean OFF State
- Deep drop: VBAT falls below UVLO_OFF → outputs must be forced OFF.
- Threshold bounce: VBAT chatters near UVLO → no on/off oscillation, no burst pulses.
- Slow recovery: ramp through thresholds → default OFF until conditions are valid and stable.
Target failure prevented: half-conduction in the threshold region (loss and heat with unpredictable torque behavior).
Overvoltage Must Not Create False Actions
- Survivability: driver/bias/interfaces must not exceed OVP limits or enter undefined states.
- No spurious fault: /FLT must not chatter from common-mode injection during the event.
- No spurious switching: PWM corruption and unintended gate rise must be prevented.
Driver-side expectation: bias OVP behavior remains controlled; enforcement paths remain valid across the event.
Strategies That Make the Behavior Deterministic
- Separated UVLO thresholds: independent UVLO_ON and UVLO_OFF to avoid threshold bounce oscillation.
- Fault latch policy: latch or hold-off during unstable supply windows (no re-enable until conditions are valid).
- Brownout freeze: freeze outputs and state machine during low-voltage jitter (prevent re-trigger storms).
- Bias OVP + clamp cooperation: bias rails must not overdrive the driver; clamp energy must not cause logic upset.
- Stable reporting: /FLT and status flags must remain readable (define deglitch policy at the interface level).
Event → Required Driver Behavior (card list, no tables)
- VBAT < UVLO_OFF → required state: OFF + report if defined → pass: VG < VSAFE within X µs.
- VBAT bouncing near UVLO → required state: freeze / latch → pass: no burst pulses; spurious transitions ≤ Y per N seconds.
- VBAT overvoltage (load-dump) → required state: no false ON + stable /FLT → pass: /FLT chatter ≤ Y; outputs remain OFF-safe.
- Recovery after event → required state: controlled re-enable per policy → pass: N-cycle repeatability; identical state transitions across N runs.
These statements are designed to be copied into review notes, validation plans, and production test requirements.
H2-6 · Isolation & High dv/dt Reality (CMTI, parasitic paths, fail signatures)
In traction inverters, isolation is not only kVrms. Immunity is defined by CMTI and the parasitic coupling paths that drive false states.
Treat high dv/dt as normal operation and focus on immunity: CMTI, parasitic coupling, and fail signatures that corrupt PWM, trigger spurious faults, or induce false turn-on.
Boundary rule: certification spacing and detailed layout rules are out of scope here; only coupling models, selection knobs, and triage outputs are covered.
What dv/dt Failures Look Like
- False turn-on: VG bumps without a valid PWM command.
- Spurious fault: /FLT chatters; DESAT/OC triggers without a true short event.
- PWM corruption: missing pulses, extra pulses, or wrong edge timing.
- Latch-up/reset: logic upset or repeated resets during fast switching edges.
These symptoms must be mapped to coupling paths before changing control software or power-stage hardware.
Practical Driver/Isolation Selection Handles
- CMTI target: 100–200 kV/µs (placeholder) with clearly defined test conditions.
- Input structure: differential or Schmitt options to resist threshold shifts and ground bounce.
- Bias noise isolation: isolated supply noise must not inject into logic thresholds or fault comparators.
- Fault pin stability: /FLT and status pins must remain stable under dv/dt (define deglitch policy).
dv/dt Failure → First Three Paths to Check (triage order)
- False turn-on → check: HS node → Cgd/Cgs → gate bump; gate clamp/pull-down effectiveness.
- Spurious /FLT → check: HS node → Ciso → logic ground shift; fault comparator reference stability.
- PWM corruption → check: common-mode return → input threshold shift; verify input structure and local ground bounce.
Pass evidence is obtained by correlating edge events with observed symptoms and confirming reduction after path mitigation.
H2-7 · Protection & Control: SC/OC/OT and controlled turn-off behavior
Traction protection is defined by reaction-time budget and controlled turn-off shape: fast enough to save the module, gentle enough to avoid secondary damage.
Convert protection features into auditable behavior: detect → decide → controlled OFF → latched safe state, with measurable timing and stable fault-to-disable paths across isolation.
Boundary rule: circuit-level parameter design (DESAT RC, clamp sizing) is referenced by link only; this section defines traction-context requirements and pass criteria.
Short-Circuit / Over-Current: Deterministic Chain
- Trigger: DESAT / OC comparator asserts under a defined condition.
- Blanking/filter: ignore early switching artifacts; avoid false trips but keep energy within limits.
- Turn-off mode: enter SOFT_OFF (controlled discharge) instead of hard slam where required.
- Policy: LATCH or AUTO-RETRY with bounded attempts and cooldown.
Traction requirement: the chain must close within a worst-case time budget (X/Y/N placeholders) without creating overvoltage spikes or re-turn-on.
“Fast but Not Explosive” Toolbox
- Two-level turn-off: fast initial pull-down to cut SC current, then gentle tail to limit dv/dt and overshoot.
- Active Miller clamp: clamps gate during OFF to block dv/dt induced false turn-on.
- −VGOFF rail: increases OFF margin in noisy environments (use only with defined rail validity conditions).
Pass evidence should reference waveform shape and “VG < VSAFE” confirmation, not only a fault pin assertion.
Over-Temperature: Safe OFF and Controlled Recovery
- OT trigger: enter controlled OFF (no transient re-enable while cooling is unstable).
- Latch policy: define whether OT is latched until power cycle or cleared by a qualified recovery rule.
- Recovery gate: re-enable only after stable conditions (time window, temperature hysteresis, attempt limit).
Goal: prevent oscillatory thermal shutdown cycles that stress the module and fault chain.
Fault Reporting & Disable Across Isolation
- /FLT: stable reporting output, usable by safety controller under dv/dt stress.
- /RDY: readiness indicator for valid bias and enable state (define what “ready” means).
- fault-to-disable: a hard path (/DIS) that forces outputs OFF even if PWM path is compromised.
- confirm OFF: observable criterion (VG below VSAFE or state latched) under worst-case.
Protection Reaction Budget Template (copy-ready)
- Detect (X): comparator/DESAT detect + filter/blanking effects (worst-case across temp & dv/dt).
- Decide (Y): internal logic + isolation propagation (if applicable) + latch policy gating.
- Turn-off (N): output stage response + controlled discharge profile (two-level/soft-off).
- Confirm OFF: VG < VSAFE within X/Y/N total window (placeholder).
The budget must be proven at worst-case axes: temperature, supply, device tolerance, and dv/dt injection.
H2-8 · Interfaces & Timing: PWM integrity, deadtime, delay matching
Convert “switch timing” into measurable parameters: delay/skew/jitter determine shoot-through risk and effective control bandwidth under worst-case corners.
Define a timing contract for traction inverters: input integrity, propagation delay matching, deadtime window, and worst-case proof of no overlap conduction.
Boundary rule: modulation/FOC algorithm details are out of scope; only interface and timing integrity requirements are specified.
Differential vs Single-Ended: Noise-First Thinking
- Differential inputs: higher common-mode rejection for dv/dt environments and long interconnects.
- Single-ended inputs: require strict threshold structure and local reference control to avoid bounce errors.
- Direct-from-isolator: define deglitch/edge qualification rules at the receiver boundary.
Validation focus: confirm no missing/extra pulses under dv/dt injection and EMI stress.
Propagation Matching Drives Safety Margin
- Arm symmetry: HS vs LS mismatch consumes deadtime margin.
- Three-phase consistency: phase-to-phase mismatch produces uneven switching stress and thermal skew.
- Deadtime design: must cover drift (temperature, supply, tolerance) at worst-case corners.
Goal: deadtime window stays positive after subtracting mismatch + jitter + safety margin.
Timing Budget Expression (list form, copy-ready)
- Isolation propagation: delay + drift ≤ X ns (placeholder).
- Driver propagation: channel delay ≤ X ns; mismatch ≤ Y ns.
- Inter-channel skew: HS/LS skew ≤ Y ns (worst-case).
- Jitter: edge jitter ≤ Z ns (placeholder definition required).
- Deadtime window: deadtime > (skew + jitter + margin) under worst-case.
- Proof: no overlap conduction confirmed at corners (temp/supply/EMI/dv/dt).
The proof path must explicitly state measurement points and corner conditions, not only typical values.
H2-9 · Layout, Grounding & Thermal Implementation (traction-specific)
Production stability is determined by gate-loop parasitics, isolation-side return control, and thermal symmetry that preserves timing and noise margins.
Convert “it runs” into “it ships”: layout partitions, controlled return paths, and thermal coupling must prevent false turn-on, spurious faults, and lifetime drift.
Boundary rule: this section is traction-focused (dv/dt, noise, symmetry, thermal drift). Device physics and generic PCB theory are out of scope.
Gate Loop Parasitics (False Turn-On Prevention)
- Kelvin source: dedicated return to the driver reference (avoid shared power return inductance).
- Min loop area: driver output → gate → source return loop kept tight and local.
- Driver island: place driver close to the power module gate pins with a clear boundary.
- Controlled damping: split turn-on/turn-off paths (or equivalent) to balance EMI vs loss.
Traction-specific note: high dv/dt and high current make inductive ground bounce look like “logic glitches”.
Ground Strategy Across the Isolation Barrier
- No cross-split return: do not allow power return currents to flow into logic/sense reference.
- Chassis bond point: define a single, documented shield-to-chassis connection location.
- CM injection control: treat barrier capacitance as a current source under dv/dt; route returns accordingly.
- Fault pin hygiene: keep /FLT, /DIS, /RDY away from switching nodes and noisy returns.
Goal: common-mode energy is diverted to a controlled path, not into thresholds or fault comparators.
Thermal Symmetry Preserves Timing Margins
- Arm-to-arm symmetry: HS/LS placement and copper/thermal path kept balanced.
- Phase symmetry: repeatable phase layout reduces mismatch and uneven stress.
- Drift awareness: driver delay and deadtime margins must survive temperature gradients.
- Hotspot discipline: isolate driver island from hot power copper where possible.
Pass outcome: timing mismatch does not grow beyond the deadtime budget at hot corners.
Layout Review Checklist (10–15 short items)
- Gate drive loop kept local; no long gate traces crossing partitions.
- Kelvin-source return routed directly to driver reference; no shared power return segment.
- Driver island clearly separated from switching node copper and high di/dt loops.
- Barrier crossing signals are minimal; each has a defined return reference.
- No “mystery” return path across the isolation split (explicitly reviewed).
- /FLT, /DIS, /RDY routed away from HS node; clean reference and spacing maintained.
- Isolated bias decoupling placed at the driver pins; shortest loop to the local reference.
- Sense routing (current/voltage) separated from gate drive; no parallel run with HS edges.
- Shield/chassis bond defined as a single point; location documented for EMC repeatability.
- Phase layout replicated; phase-to-phase mismatch minimized by placement symmetry.
- HS/LS thermal environment balanced; avoid one arm running consistently hotter.
- Keep-out around HS node enforced; no test pads/headers in the dv/dt hotspot zone.
- Isolation barrier region kept clean; no copper “bridges” that invite CM return ambiguity.
- Critical nets labeled; review notes capture “allowed” and “forbidden” crossings.
H2-10 · Validation & Production Test (Engineering Checklist + evidence)
Convert safety requirements into repeatable tests: bring-up progression, fault injection, EMC/transient immunity metrics, and production-ready evidence.
Produce a reproducible validation plan that proves: protection reaction budgets, PWM integrity under stress, and end-to-end disable/reporting paths across isolation.
Boundary rule: only driver-centric evidence is required (fault pins, disable path, timing, isolation behavior). Full system compliance documentation is referenced by linkage.
Bring-up Sequence + Fault Injection
- Single phase: confirm clean gating, no false turn-on, stable bias and status.
- Three phase: verify phase symmetry; confirm deadtime margin at corners.
- Full power: confirm controlled switching and thermal stability under sustained load.
- Fault injection: DESAT/OC, UVLO, OT, /DIS forcing; verify state machine and budget closure.
Required evidence: captured waveforms, timestamps, and OFF confirmation (VG < VSAFE) under the defined worst-case axis set.
PWM Integrity Under Stress (Metric-First)
- EFT/ESD: count spurious /FLT and missing/extra pulses within a fixed observation window.
- Load steps: verify no unintended enable/disable oscillations during DC-link disturbance.
- dv/dt corners: confirm jitter/skew remain within X/Y ns placeholders.
- Recovery behavior: confirm defined latch/auto-retry policy (bounded attempts; controlled re-enable).
The same metric definitions must be used across labs to avoid pass/fail ambiguity.
Engineering Checklist (Design gate / Bring-up gate / Production gate)
- Reaction budget defined: Detect (X) + Decide (Y) + Turn-off (N).
- Fault-to-disable path defined and independent from PWM path.
- Timing budget defined: skew/jitter/deadtime placeholders (X/Y/N).
- Layout checklist completed; forbidden return crossings reviewed and documented.
- Evidence plan created: what is measured, where it is measured, and at which corners.
- Single-phase gating verified; no false turn-on under dv/dt stress.
- Fault injection: DESAT/OC/UVLO/OT → correct state transitions and OFF confirmation.
- /FLT, /RDY, /DIS behavior verified under switching noise (no chatter beyond Y).
- Worst-case timing verified: skew ≤ X ns; jitter ≤ Y ns; no overlap conduction.
- Thermal soak confirms margins are not consumed by drift (deadtime remains positive).
- Interlock verified end-to-end (hardware enforceable OFF).
- Fault output continuity verified (pin-to-system monitoring path).
- Isolation evidence captured (driver-relevant withstand/inspection records).
- Golden waveform library established (pass envelopes for VG, delay, /FLT stability).
- Test limits documented with X/Y/N placeholders mapped to QA criteria.
H2-11 · Applications & IC Selection (Traction Inverter Gate Drivers)
Selection is constrained by traction reality: dv/dt immunity, short-circuit reaction budget, deterministic UVLO behavior, independent fault-to-disable paths, and proof-ready validation.
This section is the only place that performs practical part selection, strictly from traction-inverter constraints. It converts earlier requirements into a selection funnel and a scorecard that maps directly to validation evidence.
Boundary rule: device physics, detailed component calculations, and driver-internal circuit design are intentionally not expanded here. Use deep links to switch-technology pages for details.
SiC Traction (Hard dv/dt + Tight SC Window)
- Must survive dv/dt: high CMTI with stable input thresholds and fault pins under CM injection.
- Protection priority: short-circuit reaction budget closure (Detect + Decide + Turn-off) with controlled SOFT_OFF.
- False turn-on defense: active Miller clamp + optional −VGOFF + controlled turn-off shape.
- Timing integrity: low mismatch and stable skew across temperature corners.
Deep link: “SiC MOSFET Driver” page for gate-voltage rails and wave-shape tuning.
IGBT Traction (DESAT Discipline + Controlled Turn-off)
- DESAT clarity: programmable blanking/filter behavior and well-defined SC trip definition.
- Wave-shape safety: soft/two-level turn-off to limit overshoot and prevent secondary damage.
- Deterministic UVLO: no half-conduction during brownout or supply bounce.
- Independent shutdown: fault-to-disable across isolation must remain functional even if PWM is corrupted.
Deep link: “IGBT Gate Driver” page for DESAT and two-level turn-off implementation detail.
Traction-First Selection Order (from constraints → proof)
- CMTI / dv/dt immunity: compare only with stated test conditions; require stable /FLT and input thresholds.
- Short-circuit response time: budget closure capability: Detect (X) + Decide (Y) + Turn-off (N) (placeholders).
- UVLO behavior: separated ON/OFF thresholds + defined hysteresis; brownout must hold OFF.
- Controlled OFF tools: two-level / SOFT_OFF, Miller clamp, optional −VGOFF support.
- Fault-to-disable path: independent /DIS or equivalent hard-off path across isolation (no shared single point).
- Delay matching: HS/LS and phase-to-phase skew/jitter worst-case compatibility with deadtime proof.
- Package & creepage: safety spacing and thermal path that can be documented and produced.
Five “Do Not Get Tricked by One Number” Reminders
- CMTI trap: test conditions (dv/dt magnitude, CM swing, load) must match traction reality; otherwise comparisons are invalid.
- Matching trap: “typical skew” is not a deadtime guarantee; require worst-case drift across temperature and supply.
- UVLO trap: hysteresis and threshold separation define whether brownout causes half-conduction or chatter.
- SC time trap: “protection time” definitions differ; confirm when the stopwatch starts (fault inception vs detect assert).
- Fault pin trap: /FLT stability under dv/dt matters more than a clean pin under bench conditions.
Traction Gate Driver Selection Scorecard (100 pts)
Use the scorecard as a procurement + validation contract. Fields map directly to the test matrix and evidence pack.
Safety & Protection
- SC reaction budget support: Detect (X) + Decide (Y) + Turn-off (N).
- DESAT/OC behavior definition (blanking/filter/soft-off/latch policy).
- Controlled OFF capability (two-level / SOFT_OFF waveform discipline).
- Independent fault-to-disable path (/DIS or equivalent).
- OFF confirmation support (VG < VSAFE observation).
dv/dt & Isolation Robustness
- CMTI rating + condition notes (must match traction dv/dt reality).
- Input structure robustness (diff/Schmitt tolerance to CM injection).
- /FLT stability under dv/dt (no chatter beyond Y/window).
- Isolation architecture suitability (barrier behavior and parasitic paths).
- Iso-bias noise resilience (no false events during switching).
Timing Integrity
- Propagation delay control (HS/LS), including drift across temperature.
- Inter-channel skew worst-case ≤ X ns (placeholder).
- Edge jitter definition and worst-case ≤ Y ns (placeholder).
- Deadtime proof path: no overlap under worst-case corners.
- Three-phase consistency hooks (phase-to-phase symmetry).
Packaging & Manufacturability
- Creepage/clearance suitability for traction safety documentation.
- Thermal path and operating temperature range fit.
- Pinout practicality (layout risk, keep-out discipline).
- Production testability (observability of /FLT, /DIS, readiness).
- Evidence readiness (safety manual / diagnostics guidance availability).
Reference Candidate Parts (Gate Drivers + Key Companion Parts)
These MPNs are commonly considered in traction-class designs. Validate grade, isolation rating, and condition definitions before freezing a BOM.
Common isolated driver IC candidates (SiC/IGBT traction):
Selection emphasis: CMTI condition notes, DESAT/SC behavior definition, Miller clamp availability, and worst-case delay/skew.
When a one-module approach is required (driver + isolated supply + protection):
Use-case: reduce integration risk; still require validation of reaction budget and dv/dt immunity in the target power stage.
Common isolated bias module examples for driver-side rails (verify isolation & automotive suitability):
Traction focus: noise coupling into logic/sense, bias UVLO/OVP behavior, and recovery behavior during transients.
Practical companion part examples (verify voltage class and placement constraints):
- Gate resistors (1206 thick film): Vishay CRCW12061R00FKEA, Vishay CRCW12062R20FKEA (examples).
- Fast small-signal diodes (DESAT sense path examples): Nexperia BAV21,215; Nexperia BAS21,215 (examples).
- TVS (supply protection examples): Littelfuse SMBJ series (family), Vishay SMBJ series (family).
- MLCC decoupling examples: Murata GRM31 series (family) placed at driver pins with shortest loop.
Companion parts are shown as “MPN examples” to anchor procurement discussions; exact values depend on gate charge, rails, and transient envelope.
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H2-12 · FAQs (Traction Inverter Gate-Driver View)
Scope: field troubleshooting and acceptance disputes only. Topics are limited to ASIL hooks, redundant turn-off, cold-crank/load-dump supply events, and dv/dt-induced failures.
Pass criteria uses placeholders: X=threshold (V/ns/µs/kV/µs), Y=time window (ms/s/min), N=event count limit (times/window).
