Peak Source/Sink Current for Gate Drivers: How to Size
Core Idea
Peak source/sink current is not a marketing number—it is a practical ceiling that must be translated from Qg and target tr/tf, then verified by waveforms under real Rout/Rg, loop parasitics, and supply droop. The right choice is the smallest peak drive that meets X/Y/Z/N acceptance while keeping ringing, EMI, and gate stress within limits.
Definition & Scope (Lock the Boundary)
Peak source/sink current is an output-stage capability limit—use it as an engineering input to compute, validate, and select, not as a guaranteed gate-current value on a real PCB.
What it is
- ISOURCE(peak): short, high current burst used to charge the gate (turn-on drive).
- ISINK(peak): short, high current burst used to discharge the gate (turn-off drive).
- Practical meaning: defines the upper bound on how quickly the driver can move gate charge, under the driver’s test conditions.
What it is NOT
- Not continuous current: peak ratings are short-pulse figures; thermal and average-drive limits are separate.
- Not “gate current on the PCB”: actual gate current is constrained by ROUT + RG + parasitic L, and by VDRV droop.
- Not a single “driver strength” number: turn-on and turn-off are different problems; source and sink must be treated independently.
What this page delivers
- Compute: size required drive current from Qg and target tr/tf (separate ON vs OFF requirements).
- Validate: define measurement points and acceptance criteria (rise/fall time, overshoot/undershoot, supply droop).
- Select: interpret datasheet peak-current claims and normalize test conditions for fair comparison.
- Debunk: explain why “10 A peak” can still switch slowly, or switch faster but fail EMI/robustness.
Boundary rule (avoid cross-page overlap)
- Gate-voltage range and UVLO thresholds → cover on Gate Voltage Range and UVLO pages.
- DESAT, Miller clamp, two-level drive actions → cover on Protection & Control pages.
- CMTI/dv/dt immunity and isolation details → cover on Isolation & Integration pages.
- Propagation delay, skew, deadtime timing budgets → cover on Interfaces & Timing pages.
- Layout theory (beyond Ipk-limiting parasitics) → cover on Layout & Grounding pages.
Why It Matters (Loss • EMI • Robustness)
Peak source/sink current sets the maximum gate-charge transfer speed. That speed directly trades switching loss against dv/dt-driven EMI and false turn-on risk.
If peak current is too small
- Rise/fall time increases: the device spends longer in the linear region during transitions.
- Switching energy increases: VDS and IDS overlap longer, raising Esw and device temperature.
- Deadtime penalties grow: in bridge stages, slower edges raise the chance of diode conduction and extra loss.
- Control headroom shrinks: limited edge speed reduces achievable PWM resolution and dynamic response margin.
If peak current is too large
- dv/dt and di/dt increase: faster edges excite parasitics and elevate radiated/conducted emissions.
- Ringing and overshoot increase: loop inductance converts current slew into VGS/VDS excursions.
- False turn-on risk increases: Miller coupling plus high dv/dt can inject charge into the off device gate.
- Gate stress margin reduces: overshoot/undershoot challenges absolute maximum and long-term reliability limits.
The balancing knobs (keep speed controllable)
- Split RG,on/RG,off: tune turn-on vs turn-off independently to balance loss and robustness.
- Output impedance awareness: effective Ipk is limited by driver ROUT and supply droop; normalize conditions before comparison.
- Parasitic-limited reality: loop inductance and layout set the practical edge-speed ceiling; Ipk alone cannot override physics.
- Acceptance-driven tuning: target tr/tf while keeping overshoot/undershoot and EMI within defined pass criteria.
Pass criteria (placeholders)
- tr/tf ≤ X ns at target operating point.
- VGS overshoot ≤ Y V and undershoot ≥ −Z V (Kelvin-measured).
- EMI margin ≥ N dB at the required standard and test setup.
- Driver supply droop ≤ M V during switching bursts.
Gate Charge Refresher (Qg Curve & Current Pulse)
The first-order relation I ≈ ΔQ/Δt is only a starting point. Practical switching speed is dominated by the Miller plateau (Qgd) and the gate-current waveform is inherently segmented.
Qg decomposition (what each segment controls)
Gate-current waveform is segmented
- Pre-plateau: driver charges the input portion of the gate; VGS rises quickly until the plateau region is reached.
- Plateau: VGS is nearly constant; driver current primarily transfers Qgd and forces the VDS transition (the switching “core”).
- Post-plateau: VGS continues toward VDRV; this affects conduction margin and steady-state loss more than VDS transition speed.
Source vs sink asymmetry (minimal, sizing-relevant meaning)
- Turn-off robustness often depends on the ability to remove injected gate charge during high dv/dt transitions.
- A stronger sink path (or lower Rg,off) improves the ability to hold the off device gate below unintended turn-on conditions.
- Detailed clamp and protection behavior belongs to sibling pages (Miller clamp, DESAT, UVLO).
First-Order Sizing (From Qg & tr/tf to Ipk)
First-order sizing converts a target edge speed into a required charge-transfer rate. Use Iavg ≈ ΔQ/Δt to estimate required drive current, then close the loop with waveform validation and Rg,on/off tuning.
Inputs → outputs (normalize the sizing problem)
I ≈ ΔQ/Δt is average current (not peak)
- ΔQ should reference the intended segment (plateau sizing uses ΔQ = Qgd).
- Δt should reference the intended segment duration (plateau sizing uses Δt = tplateau).
- Peak current ratings are output-stage limits; real gate current is further limited by ROUT, RG, parasitics, and supply droop.
Split tr/tf into gate-side time budgets
- tpre: time to reach the plateau (input charge build-up).
- tplateau: plateau duration that drives the VDS transition (dv/dt-dominant).
- tpost: time after plateau to reach the commanded VGS level (margin / conduction establishment).
Conservative sizing rules (avoid “typical-only” failures)
- Use Qgd(max) or worst-case Qgd (apply factor K) rather than typical values.
- Compute separately: Ireq,on and Ireq,off (sink often needs more margin under high dv/dt).
- Express margin as placeholders: Ipk ≥ M × Ireq where M captures system variance (RG, layout, supply).
Executable workflow (compute → select → validate)
- Extract Qg,total and Qgd (use worst-case factor K).
- Choose target tr/tf and define a plateau time budget tplateau.
- Compute: Ireq,on ≈ (K·Qgd)/tplateau and Ireq,off ≈ (K·Qgd)/tplateau (separate margins).
- Pick driver class based on source/sink capability and test-condition alignment.
- Validate waveforms: tr/tf, VGS over/undershoot, VDRV droop; tune Rg,on/off to meet pass criteria.
Real Driver Output Model (Why “10 A Peak” Can Still Switch Slow)
Peak current ratings are output-stage limits measured under specific conditions. On a real PCB, gate current and edge speed are constrained by Rout + Rg + loop parasitics and by VDRV droop.
Equivalent output path (minimum model for sizing)
Peak current upper bound (first approximation)
- Useful upper bound (ignoring inductance and droop):
- This expression explains why a higher datasheet Ipk can show little benefit when Rg and trace resistance dominate the series path.
- Use it as a screening tool, then validate with waveforms (rise/fall time, overshoot/undershoot, VDRV droop).
Loop inductance sets a hard ceiling (di/dt, ringing, VGS stress)
- Gate-loop inductance limits current slew (V = L·di/dt) and converts fast drive into ringing.
- Higher di/dt increases VGS overshoot/undershoot, raising EMI and reliability risk even when switching loss improves.
- Only the Ipk-limiting mechanism is covered here; layout implementation details belong to the Layout page.
VDRV droop can “consume” peak capability
- Peak gate current is sourced from local supply decoupling; insufficient decoupling or high supply impedance causes VDRV sag during switching bursts.
- Droop reduces effective drive voltage, lowering instantaneous gate current and shifting switching timing.
- Measure VDRV at the driver supply pins with a short return path; define droop limits in acceptance criteria.
Boundary (prevent cross-page overlap)
- Protection actions (Miller clamp, DESAT, two-level drive) → see Protection & Control pages.
- Isolation/CMTI behavior under high dv/dt → see Isolation & Integration pages.
- Layout implementation rules beyond the Ipk-limiting model → see Layout & Grounding page.
Source vs Sink Asymmetry (Hard Turn-Off, Controlled Turn-On)
Turn-on and turn-off are different objectives. Many systems prioritize turn-off robustness while keeping turn-on controllable to meet EMI and reliability targets.
Why turn-off is often the priority
- High dv/dt transitions can inject charge through Miller coupling; a strong sink path helps remove injected charge faster.
- Insufficient turn-off strength increases the window for unintended conduction and cross-conduction risk.
- Detailed clamp and protection mechanisms belong to sibling pages; this section stays at the sizing-and-tuning level.
Three practical knobs (sizing and tuning)
- Higher I_SINK: select a driver with stronger sink capability when dv/dt stress is high.
- Lower Rg,off: increase discharge strength; verify VGS undershoot and ringing acceptance limits.
- Split Rg: keep turn-on softer (Rg,on) while keeping turn-off harder (Rg,off) for robust operation.
Symmetry vs asymmetry (impact paths)
- Harder turn-off can raise VGS undershoot and ringing; acceptance criteria must cap stress and EMI.
- Harder turn-on increases dv/dt and EMI; controlled slew is often preferred to avoid noise-triggered failures.
- Best practice is “minimum necessary strength” that meets measurable pass criteria—avoid unbounded peak capability.
When strong sink is required (clear triggers)
- SiC/GaN hard-switching: very high dv/dt and fast edges increase injected charge risk.
- Half-bridge high-side turn-off: loop parasitics and coupling are more sensitive to transition speed.
- Multi-leg symmetry: 3-phase and multi-bridge systems need consistent turn-off behavior across legs.
- High bus voltage / high temperature: reduced margin amplifies stress and false turn-on susceptibility.
Pass criteria (placeholders)
- Unintended conduction events: 0 over X hours at worst-case conditions.
- VGS undershoot ≥ −Z V and overshoot ≤ Y V (Kelvin-measured).
- EMI margin ≥ N dB under the required standard and setup.
- Fault/shoot-through indicators remain 0 during endurance testing.
How to Validate (What to Measure & Pass/Fail Criteria)
Validation converts peak current claims into measurable outcomes. Use a consistent measurement setup, capture the right waveforms, avoid probe-induced artifacts, and apply explicit acceptance thresholds (X/Y/Z/N/M placeholders).
Measurement targets (minimum set)
How to measure Ig (practical methods)
- Rsense method: insert a low-inductance, small series resistor in the gate path and measure differential voltage across it (trend + peak).
- Gate-loop current probe: clamp the gate loop with adequate bandwidth; use it for waveform shape and peak comparison across settings.
- Across-Rg inference: measure Kelvin voltage across Rg and infer Ig = V/R (requires true Kelvin points across the resistor).
Setup rules (avoid false ringing and false stress)
- Kelvin VGS: measure VGS between gate and Kelvin source/sense return (avoid ground-bounce inflation).
- Short return: use a ground spring or short coax return (avoid long ground leads creating fake resonances).
- Bandwidth discipline: insufficient bandwidth hides edge detail; excessive bandwidth with poor grounding manufactures ringing.
- Common reference: keep VDS and VDRV references consistent to avoid common-mode artifacts.
- Record VDRV droop: always capture supply sag near driver pins to explain “short OK, long-run drift”.
Acceptance criteria (placeholders)
- Switching time: tr/tf ≤ X ns (define measurement convention consistently).
- VGS overshoot: ≤ Y V (Kelvin measured).
- VGS undershoot: ≥ −Z V (Kelvin measured).
- Switching energy delta: ΔE_sw ≤ N% (same VBUS, ILOAD, fsw, temperature).
- Supply droop: VDRV droop ≤ M V (at driver pins).
Correlation checks (catch long-run degradation)
- Track waveforms at t=0 and after a sustained run (placeholder: T minutes) to detect drift.
- If tr/tf slows over time, prioritize checking VDRV droop and decoupling temperature rise.
- If overshoot/undershoot grows, prioritize checking gate-loop parasitics and measurement integrity.
Design Checklist (Design → Bring-up → Production)
This checklist turns the page into an executable workflow. Each stage produces concrete artifacts: sizing records, waveform logs, and production screening criteria.
Design phase (before layout freeze)
- Extract Qg,total and Qgd; apply worst-case factor K.
- Define target tr/tf and a plateau time budget; compute Ireq,on/off (placeholders).
- Select driver class by source/sink capability, VDRV range, package thermal path, and temperature grade.
- Reserve split Rg footprints (Rg,on and Rg,off) with swap-friendly pads (0 Ω options).
- Plan VDRV decoupling near driver pins (low ESL loop, short return) and define droop limit M.
- Define test points: VGS Kelvin, VDRV at pins, and optional Ig interface (Rsense footprint or probe loop).
- Create a one-page acceptance table: tr/tf ≤ X, VGS over/under ≤ Y/−Z, ΔE_sw ≤ N%, droop ≤ M.
Bring-up phase (first power-up to tuned waveforms)
- Start with conservative Rg,on/off; capture baseline VGS (Kelvin), VDS, ID, and VDRV.
- Verify waveform segmentation (pre/plateau/post) and ensure measurement integrity (short return, stable references).
- Iterate turn-on tuning toward tr target while monitoring dv/dt, overshoot, and EMI margin placeholders.
- Iterate turn-off tuning (often sink/Rg,off) to meet false turn-on robustness and undershoot limits.
- Run a sustained test (placeholder: T minutes) and compare droop and waveforms to the t=0 baseline.
- Log every change (driver, Rg,on/off, decoupling) with screenshots and conditions (VBUS, ILOAD, fsw, temperature).
Production phase (screening and root-cause paths)
- Freeze the measurement setup and probe points to avoid test-to-test variation.
- Implement production screening with pass table placeholders (X/Y/Z/N/M) and clear sampling plans.
- Archive waveforms with board revision, firmware version, and component lot identifiers.
- Use a simple fault tree for anomalies:
-
- Droop high → decoupling/impedance at VDRV pins.
- Overshoot high → gate-loop parasitics, assembly variation, or probe integrity.
- Switching time drift → Qg lot shift, temperature rise, or supply sag under burst.
Deliverables (what to store for reuse)
- Sizing record: Qg/Qgd, K, tplateau targets, Ireq,on/off, driver class decision.
- Bring-up log: step-by-step tuning history with waveform evidence.
- Production pack: test points diagram, acceptance table, and anomaly fault tree.
Application Playbooks (Peak Current Preference by Use Case)
Different applications prefer different peak-current “profiles.” Use the cards to identify whether strong source, strong sink, consistency, or controlled slew is the primary requirement, then validate with the pass criteria (X/Y/Z/N/M placeholders).
How to use this section
- Select the closest application card.
- Follow the Primary knob first (single highest-impact control).
- Apply the Pass focus items using the measurement setup and thresholds from the validation chapter (placeholders).
SiC / GaN hard-switching
IGBT (industrial / traction)
Multiphase VR (CPU/GPU VRM)
Synchronous rectifier (SR)
Common mismatches (symptom → first suspicion)
- Ipk looks high, but switching stays slow → output impedance/conditions mismatch or VDRV droop limits real current.
- Turn-on gets faster, but EMI and ringing explode → source path too aggressive for loop parasitics; move toward controlled slew.
- False turn-on risk increases → sink path insufficient or Rg,off not aligned with dv/dt environment.
IC Selection Logic (Compare Datasheets Without Getting Tricked)
Peak-current numbers must be interpreted with definition, test conditions, and output impedance proxies. Selection is complete only when the validation waveforms meet the pass table (X/Y/Z/N/M placeholders).
Datasheet checks (definition and conditions)
Three-step selection method (peak-current focused)
- Compute demand: use Qg/Qgd and target tr/tf to derive Ireq,on/off with worst-case factor K.
- Filter candidates: compare I_SOURCE/I_SINK together with Rout proxy and stated test conditions (VDRV, pulse model).
- Close the loop: validate with waveforms and pass table placeholders (tr/tf, VGS over/under, ΔE_sw, VDRV droop).
Common traps (symptom → first check)
- Huge Ipk, but still slow edges → Rout proxy is high, conditions mismatch, or VDRV droop limits real current.
- Fast on-edge, unstable behavior → source path too aggressive for loop parasitics; shift toward controlled slew / split Rg.
- Turn-off not clean → sink strength or Rg,off is insufficient for dv/dt environment.
Comparison template (fill with placeholders)
- I_SOURCE(peak): ___ · I_SINK(peak): ___
- Test conditions: VDRV ___ · load model ___ · pulse ___ · temp ___
- Rout proxy: VOH/VOL curve available? (Yes/No) · typical impedance hint? (Yes/No)
- Droop risk flag: VDRV pin droop measured ≤ M V? (Yes/No)
- Validation status: tr/tf ≤ X · VGS over/under ≤ Y/−Z · ΔE_sw ≤ N% (Yes/No)
H2-11 · IC Selection (Part Numbers) — Peak Drive Focus
This chapter provides a starter shortlist of gate-driver IC part numbers and a comparison method that stays strictly inside the “Peak Source/Sink Current” boundary: interpret peak-current claims, map to Ireq_on/off, and close the loop with waveform-based acceptance.
1) Pre-filter inputs (do this before reading any datasheet)
Electrical targets
- Qg_total & Qgd at the intended VGS and VDS conditions (use worst-case / max).
- Target tr/tf translated to gate-side segments (plateau time is the anchor).
- Ireq_on / Ireq_off computed separately (turn-off usually needs stronger sink).
- Driver supply rails (VDD, optional −VEE) and allowed droop budget.
Physical constraints
- Isolation needed? (reinforced/basic/none) and creepage/clearance package limit.
- Topology (low-side / bootstrap HS-LS / isolated HS-LS / multiphase) only as a filter.
- Gate loop parasitics: Lloop & Kelvin-source availability (limits real Ipk).
- Protection coupling (DESAT, clamp, /FLT) only if it changes turn-off behavior.
Rule of thumb: peak-current numbers are only meaningful when paired with test conditions (VDRV, pulse width/period, load model) and an implied Rout. Selection must treat “Ipk” as a capability ceiling, while the real gate current is set by Rout + Rg + Lloop + supply droop.
2) Datasheet reading checklist (peak-current definition traps)
- Peak current test conditions: confirm VDRV, pulse width, minimum period, and temperature corner.
- Source vs sink: verify whether I_SOURCE and I_SINK are separate and whether they are symmetrical.
- Split outputs / separate pins: split paths often imply different effective Rout per path and better tuning with Rg_on/off.
- Output impedance evidence: look for Rout curves, VOUT droop vs IOUT, or rise/fall time vs CL.
- Supply sensitivity: UVLO thresholds and output behavior under VDD droop (Ipk can collapse first).
- Pulse-power limits: “Ipk” may be allowed only for microsecond-class pulses; check output-stage thermal constraints.
3) Part-number shortlist by driver class (use as a first pass)
Each card lists: architecture → peak drive headline → when it helps peak-current closure.
TI UCC21750
- Use when Ireq_off is aggressive and sink strength must stay high under dv/dt stress.
- Best fit when “peak current” must remain actionable with strong turn-off behavior and fast fault reaction.
TI UCC21520
- Use when two channels must match reasonably while still providing meaningful sink strength.
- Good baseline for half-bridge stacks where Ipk is moderate but repeatable timing matters.
Infineon 1EDC20I12MH
- Use when “peak current” needs to be in the 4 A class and packaging/isolation is a primary constraint.
- Works well when Ireq is moderate and layout can keep Lloop low to preserve real current.
onsemi NCD57252 / NCV57252
- Use when two isolated outputs are needed and peak current must stay in the ~6 A class.
- Practical for dual-switch drive where sink capability is not allowed to be the bottleneck.
ADI ADuM4135
- Use when an isolated gate-driver channel is needed and turn-off robustness is prioritized.
- Helpful when the project needs a clean isolation barrier and a stable turn-off path.
TI UCC27714
- Use when a floating high-side is acceptable and peak current around 4 A meets Ireq.
- Selection focus: ensure bootstrap and supply droop do not cap the real peak gate current.
ST L6398
- Use when Ireq is low (small Qg / slower edge target) and a compact 600 V half-bridge driver is desired.
- Good reminder case: “peak current” quickly becomes the limiting knob when scaling to larger Qg.
TI UCC27524A
- Use for LV MOSFET stages when Ipk must be multi-amp and layout can keep Lloop minimal.
- Pairs well with split Rg strategies to keep EMI under control while meeting tr/tf.
Infineon 2EDN7524F
- Use when a dual-channel driver is needed and the project targets “5 A class” peak drive for fast charging/discharging.
- Selection focus: confirm Ipk conditions and ensure supply decoupling preserves peak output.
Microchip TC4420
- Use when a straightforward low-side gate driver is needed and peak current must be in the ~6 A range.
- Selection focus: validate real gate current vs Rg and parasitics (avoid “datasheet Ipk illusion”).
TI LMG1210
- Use when a GaN half-bridge driver is required and peak-current demand is moderate but edge control/matching is critical.
- Selection focus: verify that Ipk meets the intended tr/tf once the loop inductance is minimized.
Pass-fail closure (must exist for any chosen part): after shortlisting by Ipk class, selection is only “done” when the measurement chapter confirms: tr/tf ≤ X ns, Vgs overshoot ≤ Y V, Vgs undershoot ≥ −Z V, and supply droop does not degrade switching after soak.
IC shortlist map (peak-current closure path)
Box diagram that keeps this page inside its scope: sizing → Ipk class → validate → finalize (no cross-topic expansion).
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FAQs (Peak Source/Sink Current)
Each answer follows a fixed 4-line structure for troubleshooting and acceptance alignment: Likely cause / Quick check / Fix / Pass criteria (with placeholders X/Y/Z/N/M).
Datasheet says 10A peak, but Vgs rise is still slow—why?
Likely cause: Real gate current is limited by Rout + Rg + Lloop and/or VDRV droop, not by the headline Ipk.
Quick check: Probe VDD at driver pins during switching and confirm effective Rg at the gate (at the component, not schematic).
Fix: Reduce effective series impedance (Rg and shared return), and add close-in decoupling to prevent VDRV collapse.
Pass criteria: tr(10–90%) ≤ X ns and VDD droop ≤ M V under the intended burst/soak condition.
Increasing driver peak current made EMI worse—first knob to turn?
Likely cause: Higher Ipk reduces tr/tf but increases dv/dt and ringing excitation, pushing emissions up.
Quick check: Step Rg_on upward by one increment and compare EMI delta versus the tr/tf change.
Fix: Add slew control primarily on turn-on (Rg_on or split Rg) while keeping turn-off adequate for safety.
Pass criteria: EMI delta ≤ N dB while maintaining tr ≤ X ns and VGS overshoot ≤ Y V.
Turn-on looks fast, but turn-off is sluggish—source/sink mismatch or Rg_off?
Likely cause: Turn-off is sink-limited (I_SINK too low) and/or Rg_off too large, stretching tf and plateau time.
Quick check: Change only Rg_off (leave Rg_on unchanged) and observe tf and plateau duration shift.
Fix: Strengthen the discharge path (lower Rg_off or choose a sink-strong driver class for Ireq_off).
Pass criteria: tf(90–10%) ≤ X ns and no undershoot below −Z V at the Kelvin VGS point.
Gate waveform rings badly after upgrading driver—loop inductance or probe artifact?
Likely cause: Faster edge excites Lloop/Cg resonance, or the measurement setup creates a false ringing signature.
Quick check: Re-measure VGS with Kelvin reference and a short ground/spring (or differential probe) to remove probe-loop artifacts.
Fix: Reduce loop inductance and add damping (increase Rg slightly on the offending edge) without changing topology.
Pass criteria: Ringing settles within T ns and VGS overshoot ≤ Y V at the defined measurement bandwidth.
Peak current spec is huge, yet VDRV droops—decoupling or bootstrap limit?
Likely cause: Local decoupling impedance and recharge path limit peak delivery; bootstrap bias may be undercharged at duty/frequency.
Quick check: Capture VDD (and bootstrap node if used) at the pins during the fastest switching burst.
Fix: Add close-in ceramic decoupling and lower supply path impedance; ensure bootstrap recharge conditions meet the operating profile.
Pass criteria: VDD droop ≤ M V and tr/tf remain within X ns after a thermal/operational soak.
Two boards same driver, one switches slower—what layout parasitic dominates?
Likely cause: Gate return sharing and loop geometry differences increase effective Lloop/Rshared, reducing real current and slowing edges.
Quick check: Compare Kelvin-source routing, gate-return path, and the physical Rg placement between boards.
Fix: Enforce identical gate-loop geometry (short loop, dedicated return, Kelvin sense) and keep Rg at the gate pin.
Pass criteria: tr/tf difference ≤ ΔX ns between boards under identical test conditions and VDD droop ≤ M V.
Faster switching increased overshoot—how to keep speed but reduce ringing?
Likely cause: The loop is underdamped; higher di/dt drives larger overshoot and sustained ringing.
Quick check: Sweep Rg in small steps and record overshoot versus tr/tf to find the knee point.
Fix: Use split Rg (different effective damping on the critical edge) to preserve speed while reducing peak stress.
Pass criteria: VGS overshoot ≤ Y V while keeping tr ≤ X ns and ringing settle time ≤ T ns.
Measured tr/tf differs wildly between labs—what measurement setup mismatch?
Likely cause: Different bandwidth, reference points (Kelvin vs non-Kelvin), and rise/fall definitions (10–90%, 20–80%) skew results.
Quick check: Align probe bandwidth limit, grounding method, reference nodes, and the exact timing definition window.
Fix: Publish a single measurement note: points, bandwidth, threshold definition, and fixture wiring to standardize results.
Pass criteria: Lab-to-lab tr/tf delta ≤ ΔX ns when using the same definition and Kelvin VGS reference.
Why does gate current not look like “peak current” at all?
Likely cause: Gate current is segmented (pre-plateau / plateau / post-plateau) and shaped by Rout, Rg, and the Miller plateau.
Quick check: Estimate Ig using a small sense resistor in the gate return (or a suitable current probe) with a defined bandwidth.
Fix: Interpret speed using the plateau segment (Qgd-related) rather than expecting a flat “Ipk” waveform.
Pass criteria: Plateau timing and resulting tr/tf meet target ≤ X ns and VGS stress stays within ±Y/−Z V.
How much margin do I need on Ipk vs calculated Ireq?
Likely cause: Ireq is an average over Δt, while real peak is capped by Rout and supply droop across worst-case Qg corners.
Quick check: Recompute using max Qg/Qgd and minimum VDD corner; verify that the sink path also meets Ireq_off.
Fix: Apply a margin factor K for temperature/tolerance and validate at corners instead of relying on a single nominal calculation.
Pass criteria: Meets X/Y/Z/N/M placeholders across worst-case Qg and VDD corners (no performance collapse after soak).
Strong sink fixes false turn-on but increases undershoot—what to check first?
Likely cause: Higher discharge di/dt amplifies Lloop-induced negative swing, and poor probing can exaggerate undershoot.
Quick check: Confirm undershoot at Kelvin VGS with controlled bandwidth and verify the return path is not shared.
Fix: Add damping on turn-off (small Rg_off increase or damping element) while keeping false turn-on margin intact.
Pass criteria: No undershoot below −Z V and false turn-on event rate ≤ N per 1k cycles (placeholders).
Driver runs hot when switching fast—peak vs average current misunderstanding?
Likely cause: Higher switching frequency and repeated charge/discharge increase average output-stage loss even if Ipk is “allowed.”
Quick check: Measure driver supply current versus frequency and compare temperature rise after a steady-state soak.
Fix: Reduce unnecessary edge aggressiveness (target the needed tr/tf only) or move to a driver with lower dynamic loss at the same Ireq.
Pass criteria: Driver case temperature ≤ Y °C and supply current ≤ X mA at the defined operating frequency (placeholders).
