UVLO Thresholds for Gate Driver ICs (ON/OFF Margins)
UVLO thresholds are not just “undervoltage protection”—they define whether the gate is driven hard enough to stay out of the under-drive danger zone. A correct UVLO_ON/UVLO_OFF window, plus ripple/droop margin and deterministic recovery, prevents half-conduction loss, chatter, and reset storms.
What UVLO Thresholds Really Mean (and Why “Half-Conduction” Happens)
UVLO thresholds are not a generic “low supply” warning. In a gate driver, UVLO defines whether the switch is driven inside a fully-enhanced, low-loss region or forced into an under-drive region where conduction loss rises sharply.
DefinitionUVLOON vs UVLOOFF
- UVLOON: the supply level where the driver is allowed to begin driving the gate.
- UVLOOFF: the supply level where the driver must stop driving (to avoid under-drive).
- The gap between them is hysteresis, the minimum immunity against ripple and noise.
Practical rule: always evaluate valley voltage (worst-case droop + ripple), not only the average.
Why it failsHalf-conduction is an under-drive condition
“Half-conduction” does not mean the gate is half-open. It means the gate drive is insufficient to keep the device in the low-loss region:
VDRV ↓ → VG ↓ → RDS(on)/VCE(sat) ↑ → Pcond ↑ → Tj ↑ → reliability risk ↑
A common trap: UVLO may never assert if UVLOOFF is set too low, yet under-drive still occurs. That produces overheating without a clear “UVLO fault”.
System impactChatter amplifies failures
- PWM interruption: switching bursts become fragmented when the driver toggles enable/disable.
- Control wind-up: integrators accumulate error during off periods and overshoot at re-enable.
- Reset/retry storms: repeated threshold crossings cause repeated restarts and secondary faults.
Engineering takeaway: UVLO thresholds must be set to keep the gate drive out of the under-drive zone during worst-case ripple/droop.
Pass criteria template (fill X/Y/N):
Worst-case VG(valley) stays above the device’s recommended minimum by X V across Y load steps and N minutes of operation (no UVLO chatter).
UVLO Inside a Gate Driver (Comparator, Hysteresis, Latch, Output Stage)
UVLO behavior is determined by an internal chain: reference → comparator → hysteresis → logic/latch → output stage. The same datasheet threshold value can behave very differently depending on how these blocks implement noise immunity, timing, and safe output action.
1Reference + Comparator: where the threshold comes from
- The reference and comparator define the nominal trip point, plus tolerance and temperature drift.
- High dv/dt and supply spikes can appear at the pins as fast disturbances; if they reach the comparator input path, false trips become possible.
- Threshold evaluation should use min/typ/max (not a single “typical” number) to build margin.
2Hysteresis: the minimum anti-chatter window
- UVLOON and UVLOOFF are intentionally separated.
- If ΔVpp(ripple) ≥ hysteresis, repeated enable/disable transitions become likely during ripple valleys.
- Hysteresis is a first-order “guardrail”; it does not replace proper supply integrity and decoupling.
3Latch/Logic: what happens after a trip
- Some drivers simply disable outputs until VDRV recovers above UVLOON.
- Others combine UVLO with a fault policy (for example: hold-off, auto-retry, or latch until enable reset).
- Recovery behavior must be defined in an acceptance test to avoid “reset/retry storms”.
4Output stage action: the practical “safe state”
- UVLO can force different gate actions: strong pull-down, high-impedance, or a controlled/soft transition.
- Selection should match the external gate network and the required shutdown predictability.
- For multi-channel drivers, confirm whether each channel has independent UVLO and how close the thresholds match.
What this chapter enables: a consistent interpretation of UVLO numbers, so later chapters can budget ripple/droop and verify behavior with a repeatable bench procedure.
Implementation details for short-circuit protection, Miller clamp, or bootstrap sizing are intentionally excluded to avoid cross-page overlap.
Defining UVLOON / UVLOOFF Budget (Ripple, Droop, Tolerance, Temp)
UVLO thresholds must be evaluated against the worst-case valley at the driver supply pins. The goal is not “average VDRV is OK” but: VDRV(valley) stays safely above UVLOOFF (no under-drive) and VDRV(restore) crosses UVLOON (predictable restart).
Budget objective: ensure Margin_OFF = VDRV(valley) − UVLO_OFF remains positive with headroom under worst ripple, droop, tolerance, and temperature.
All terms must be referenced to measurements at the driver VDD/GND pins, not at a remote regulator node.
Supply floorVDRV,min (droop + distribution)
- Load-step droop: finite regulator bandwidth, current limit foldback, or transformer secondary sag.
- Distribution loss: trace resistance, connector drop, and return-path inductance (local ground lift).
- Corner definition: evaluate at worst load, worst duty/burst mode, and worst temperature.
This term sets the “DC floor” that ripple rides on.
AC disturbanceΔVripple (peak-to-peak)
- Use peak-to-peak ripple measured at the driver pins with proper probing.
- Translate ripple into valley impact: the worst valley typically tracks about ΔVpp/2 below the average (unless waveform is highly asymmetric).
- Ripple must be evaluated during the same switching mode that causes field failures (burst, high duty, hard-switch).
When ripple approaches hysteresis size, chatter risk rises sharply.
Threshold uncertaintyMin/Max + temperature drift
- Use datasheet UVLOON(min/max) and UVLOOFF(min/max), not “typ”.
- Temperature shifts both the supply behavior (droop/ripple) and the comparator/reference behavior (effective trip point).
- Budget must hold across the required operating temperature range: Y °C corner(s).
Decision latencyFilter / delay vs short dips
- Too little filtering: short spikes can cause false UVLO trips.
- Too much filtering: real brownouts may be detected late, leaving time in the under-drive zone.
- Define a practical criterion: “dips shorter than X μs must not trip; dips longer than Y μs must trip.”
This is evaluated by time-aligned VDRV waveforms and output-state transitions.
Reusable UVLO Budget Table (fill X/Y/N)
The table below standardizes how UVLO margin is communicated in design reviews and test reports. All entries refer to the driver supply pins and the worst-case operating mode.
| Budget item | Definition at driver pins | How to obtain | Pass criteria (X/Y/N) |
|---|---|---|---|
| VDRV,nom | Nominal rail at VDD/GND during steady operation | Measure at typical load, typical mode | Reference only (not a pass limit) |
| Droop | DC/low-frequency sag under worst load step | Worst-case load step at mode N | Droop ≤ X V |
| ΔVripple | Peak-to-peak ripple at VDD/GND pins | Scope with correct probe and bandwidth | ΔVpp ≤ X V |
| UVLO_OFF (worst) | Use UVLO_OFF(max) for margin-to-off evaluation | Datasheet max + temperature corner check | Use max in margin calculation |
| UVLO_ON (worst) | Use UVLO_ON(max) for restart guarantee | Datasheet max + temperature corner check | Restart crosses UVLO_ON within Y ms |
| VDRV(valley) | Worst observed supply valley in real switching mode | Worst duty/burst + worst load + worst temp | VDRV(valley) − UVLO_OFF ≥ X V @ Y °C |
| No chatter | No repeated enable/disable toggles around thresholds | Log UVLO/outputs for N minutes | 0 events / N minutes |
Corner pass criteria (fill X/Y): Margin ≥ X V at Y °C, with no UVLO chatter across the defined operating modes.
Matching Device-Recommended Gate Drive Rails to UVLO (Avoiding Under-Drive)
UVLO thresholds must be aligned to the device’s effective drive region. A driver can stay “enabled” while still operating in an under-drive danger zone if UVLOOFF is set too low. The objective is to use UVLO to exclude the region where conduction loss rises rapidly and reliability degrades.
Threshold-setting logic (fill X/Y):
- UVLOOFF ≥ (upper edge of under-drive danger zone) + Margin(X)
- UVLOON ≥ (entry point of full-drive region) + Margin(Y)
“Danger zone edge” and “full-drive entry” must be sourced from the switch vendor’s recommended gate-drive guidance and validated at the intended switching conditions.
IGBTUnder-drive quickly increases loss
If gate drive falls below the recommended region, conduction loss rises steeply. UVLOOFF should be positioned to prevent operation in the high-loss region rather than only reacting to deep brownouts.
Detailed short-circuit behavior and DESAT policies belong to the DESAT page.
SiC MOSFETDrive window and turn-off strength matter
SiC platforms often rely on strong turn-off behavior and tight control of the effective gate voltage. UVLO policies must account for supply valleys that reduce the effective drive margin and can increase susceptibility to dv/dt events.
Negative rail design and clamp details are handled in the SiC driver and Miller-clamp pages.
GaN HEMTNarrow gate window demands strict rail control
GaN gate windows are typically narrower; a “safe full-drive region” should be defined explicitly to avoid both under-drive loss and overvoltage stress. UVLO thresholds should work with rail limits to keep operation inside that region.
Technology-specific gate limits are handled in the GaN driver page.
LV MOSFETChatter is common in burst/skip modes
In synchronous bucks and BLDC stages, burst/skip modes can create large ripple valleys. UVLO hysteresis and restart behavior should be chosen to avoid repeated toggles while still blocking true under-drive.
EMI vs loss tradeoffs for slew control belong to the gate-resistor / slew-control page.
Practical alignment steps (review-ready)
- Step 1: define the device’s “safe full-drive region” and the “under-drive danger region” for the target switching conditions.
- Step 2: apply the H2-3 valley budget to compute worst-case VDRV(valley) at the driver pins.
- Step 3: place UVLOOFF above the danger region edge with margin; verify no operation occurs in the danger region.
- Step 4: place UVLOON so restart only occurs when the rail returns to the full-drive entry with margin.
- Step 5: validate with time-aligned waveforms: VDRV, output state, and thermal/power symptoms under worst mode.
UVLO Behavior During Fast Events (Brownout, Load Step, Burst Mode)
Field UVLO incidents often occur even when the average rail looks adequate. The root cause is typically a valley crossing driven by fast events: short spikes, load-step droop, or burst/skip modes that increase ripple depth. UVLO policy must therefore be specified in two dimensions: dip depth and dip duration.
Policy statement: define (1) a minimum dip duration below which UVLO must not trigger (T_ignore) and (2) a duration above which UVLO must trigger (T_must_trip).
This prevents false trips on very short disturbances while still blocking sustained under-drive conditions.
Class AShort spike (very brief dip)
- Signature: sharp, narrow dip; may repeat with switching edges.
- Desired behavior: should not trigger UVLO when duration is below T_ignore.
- Risk if mis-handled: repeated enable/disable toggles that look like “random resets”.
Class BLoad-step droop (medium duration)
- Signature: dip with recovery; duration depends on regulator bandwidth and local decoupling.
- Key supply-path contributors: distribution resistance, insufficient local capacitance, return-path inductance.
- Policy note: behavior may be application-dependent; define an allowed dip window explicitly.
Class CBrownout (long duration)
- Signature: sustained low rail; often tied to power-source collapse or limit/foldback behavior.
- Desired behavior: must trigger UVLO and force a defined safe output state when duration exceeds T_must_trip.
- Risk if mis-handled: prolonged under-drive with elevated loss and thermal stress.
Event Classification Table (fill X/Y)
The table below standardizes acceptance criteria for “dip depth vs duration” across brownouts, load steps, and burst modes. Values are defined at the driver supply pins.
| Event class | Duration window | Allowed dip definition | Expected UVLO action |
|---|---|---|---|
| Class A Spike | < T_ignore (X μs) | May cross UVLO briefly, but must not cause a state toggle | Ignore (no disable) |
| Class B Droop | X–Y μs/ms | Valley must remain ≥ UVLO_OFF + X V (or follow a defined hold-off rule) | Policy-defined (documented) |
| Class C Brownout | > T_must_trip (Y ms) | Any sustained dip below UVLO_OFF beyond Y ms | Must trip (enter safe state) |
Pass criteria template (fill X/Y/N):
- No chatter: 0 unexpected toggles during N minutes of worst-case burst/load-step operation.
- Required response: Class C events must force safe output state within X μs.
- Recovery: restart occurs only after crossing UVLO_ON and meeting the defined stability window Y ms.
Split Supplies and Negative Rails UVLO (VDD / VEE / Output-State Interaction)
Many gate driver platforms use split rails: a positive drive rail (VDD) and an optional negative rail (VEE). UVLO must be interpreted per-rail: a “rail undervoltage” is not a single condition. The required output behavior must be stated as a rail-to-behavior mapping to avoid ambiguity in reviews and acceptance tests.
Single-railOne UVLO path
- Only VDD is monitored for UVLO behavior.
- Trip/recovery semantics are typically simpler: disable below UVLO_OFF, re-enable above UVLO_ON.
Split-railTwo UVLO paths, multiple meanings
- VDD undervoltage affects drive strength and the ability to hold the device in the full-drive region.
- VEE undervoltage can reduce turn-off robustness and increase susceptibility to dv/dt-induced events (risk statement only).
- Systems must define: which rail triggers which output state (OFF / Clamp / Hi-Z) and how recovery is handled.
Clamp and Miller mechanisms are intentionally not expanded here to avoid cross-page overlap.
Rail-to-Behavior Table (fill X/Y/N)
Use this template to document UVLO meaning when multiple rails exist. Output states are left as placeholders to match the chosen driver policy.
| Condition at rails | UVLO detection | Expected output state | Pass criteria (X/Y/N) |
|---|---|---|---|
| VDD OK, VEE OK | No UVLO asserted | ACTIVE | Stable operation for N minutes |
| VDD LOW, VEE OK | UVLO_VDD asserted (per device min/max) | OFF / Hi-Z (policy) | Disable within X μs; no under-drive operation |
| VDD OK, VEE LOW | UVLO_VEE asserted (if implemented) | OFF / Clamp (policy) | No false turn-on; output state matches policy across N events |
| VDD LOW, VEE LOW | Both UVLO paths asserted | SAFE STATE (policy) | Safe state maintained until recovery criteria met |
| Recovery (rails restored) | Cross UVLO_ON (per rail) + stability window | RE-ENABLE (policy) | Restart only after Y ms stable rails; 0 chatter |
Pass criteria template (fill X/Y/N):
- For each rail undervoltage condition, output state matches the documented policy for N injected events.
- No unintended turn-on behavior during VEE-low conditions.
- Re-enable occurs only after both rails satisfy UVLO_ON and remain stable for Y ms.
Preventing UVLO Chatter (Noise, EMI, Layout, and Filtering)
UVLO chatter is a repeated threshold crossing that causes output-state toggling. It is not a “random reset” problem; it is a measurable interaction among rail ripple, coupled disturbance, and ground reference movement. The objective is to make UVLO behavior deterministic: no false trips and no repeated toggles.
Definition: chatter = more than X UVLO-related enable/disable transitions within Y seconds under a repeatable operating mode.
A compliant design reports 0 unintended toggles during the defined stress window.
Source 1Excess rail ripple at VDD pins
- Mechanism: the VDD valley repeatedly crosses UVLO_OFF (and hysteresis window).
- UVLO-view symptom: toggling correlates with ripple envelope and switching mode (burst/skip/high duty).
- UVLO knobs: local decap layering, short supply loop, rail filtering near VDD pins.
Source 2Common-mode injection into REF/UVLO sense (CMTI-related)
- Mechanism: dv/dt coupling shifts internal reference/sense nodes, creating an “apparent” rail dip.
- UVLO-view symptom: chatter appears in high dv/dt tests and disappears when edge rate is reduced.
- Scope boundary: coupling physics belongs to the CMTI page; this chapter only defines UVLO-facing checks and knobs.
Source 3Ground bounce / return crossing splits
- Mechanism: PGND and local reference ground move relative to each other during di/dt events.
- UVLO-view symptom: VDD-to-GND at the pin looks lower even if the remote rail node is stable.
- UVLO knobs: Kelvin PGND for sensing/control ground, avoid return paths crossing partition boundaries.
UVLO-Specific Mitigation Knobs (actionable, scope-limited)
- RC filtering (policy-defined): set a defined T_ignore window to reject ultra-short dips while still tripping on sustained brownouts.
- Decoupling layering: local high-frequency capacitance at VDD pins plus bulk support, minimizing the loop area of the VDD/PGND path.
- Kelvin PGND reference: keep the UVLO sense reference tied to a quiet local return rather than high-current power return.
- Hysteresis strategy: ensure UVLO_ON–UVLO_OFF separation is sufficient relative to observed ripple at the pins.
Pass criteria (fill X/Y/N):
- 0 unintended UVLO toggles during N minutes in worst switching mode.
- Class-A dips shorter than T_ignore do not toggle the output state.
- When UVLO legitimately trips, the transition is single-shot (no chatter) and recovery follows the documented policy.
Safe State Definition (Outputs at UVLO, and How to Wire /EN /FLT)
UVLO must be treated as a predictable system contract. When UVLO is asserted, the output must enter a clearly defined safe state, external control pins must not “fight” the internal lockout, and fault signaling must remain observable. This chapter defines the UVLO-facing behavior only and avoids mixing other fault sources.
ContractOutput state at UVLO
- Enumerate the safe state: Gate LOW / Hi-Z / Clamp (policy-defined).
- Timing: enter safe state within X μs after UVLO assertion.
- Hold rule: remain in safe state until recovery criteria are satisfied (no oscillation).
Hierarchy/EN vs UVLO vs /FLT
- UVLO: internal lockout layer; rail not valid ⇒ drive not allowed.
- /EN (/DIS): external strategy layer; rail valid ⇒ system may still keep outputs disabled.
- /FLT: observability layer; reports lockout state (commonly open-drain, policy-defined).
RecoveryRestart behavior
- Auto-recover: restart after crossing UVLO_ON and meeting stability window Y ms.
- Latch policy: restart requires explicit /EN transition or reset action (policy-defined).
- No-chatter rule: recovery must not re-enter UVLO repeatedly under the same disturbance.
Fault-Path Checklist (fill X/Y/N)
Use this checklist as an acceptance gate to ensure UVLO behavior, external control, and fault reporting remain consistent across boards, labs, and firmware versions.
Pass criteria (fill X/Y/N):
- UVLO assertion forces the documented safe output state within X μs.
- System remains stable for N minutes with 0 unexpected state toggles.
- Recovery occurs only after rails cross UVLO_ON and remain stable for Y ms.
How to Verify UVLO Thresholds (Bench Procedure + Corner Cases)
UVLO verification must use a consistent trigger definition. Thresholds are not “datasheet numbers” until they are measured at the VDD pin and tied to an observable output-state transition. This section defines a reusable bench procedure and a corner matrix that maps directly to acceptance criteria.
Trigger definitions (policy-aligned):
- UVLO_OFF (falling ramp): VDD(pin) at the moment the output enters the documented safe state (LOW/Hi-Z/Clamp).
- UVLO_ON (rising ramp): VDD(pin) at the moment the output is allowed to resume drive under the documented recovery policy.
/FLT may be captured as an auxiliary indicator, but output-state transition is the primary trigger to avoid false pass/fail from wiring errors.
Baseline Bench Procedure (slow ramp)
-
Instrument the correct nodes
Measure VDD(pin), OUT, and optional /FLT. Avoid remote-supply nodes as the threshold reference.
-
Set a slow, controlled ramp
Use dV/dt = X (rising) and dV/dt = X (falling) so the measurement reflects static thresholds rather than fast-event filtering.
-
Apply the trigger rule
Record the exact VDD(pin) when OUT enters safe state (UVLO_OFF) and when drive resumes per policy (UVLO_ON).
-
Repeat for statistics
Repeat N cycles and report min/typ/max for UVLO_OFF, UVLO_ON, and hysteresis (ON–OFF).
-
Check for unintended toggling
Confirm 0 chatter during steady operation around thresholds (no repeated enable/disable flips).
Corner Matrix (temperature, ripple, fast brownout)
CornerTemperature
- Conditions: T_cold = X°C, T_hot = Y°C.
- Action: run the baseline ramp at each temperature and record drift in UVLO_OFF/UVLO_ON.
- Pass: margins remain ≥ X V and recovery policy remains deterministic.
CornerRipple injection
- Conditions: ripple amplitude X Vpp, frequency Y (sine or switching-like).
- Action: superimpose ripple at VDD and observe threshold crossings and chatter near UVLO_OFF.
- Pass: no unintended toggles; ripple headroom remains within the defined budget envelope.
CornerFast brownout pulse
- Conditions: dip depth X V, duration Y μs/ms.
- Action: inject dip pulses and verify T_ignore vs T_must_trip behavior.
- Pass: short dips do not toggle; long dips force safe state within X μs.
Measurement Record Table (min/typ/max + pass criteria)
Use the table below as an acceptance-ready record. Values are measured at VDD(pin) and referenced to the documented safe state.
| Condition | Ramp dV/dt | UVLO_OFF (min/typ/max) | UVLO_ON (min/typ/max) | Hys (ON–OFF) | Pass criteria (X/Y/N) |
|---|---|---|---|---|---|
| Room | X | min/typ/max | min/typ/max | min/typ/max | Margin ≥ X V; chatter=0 / N min |
| Cold (X°C) | X | min/typ/max | min/typ/max | min/typ/max | Recovery stable for Y ms; deterministic |
| Hot (Y°C) | X | min/typ/max | min/typ/max | min/typ/max | Safe state entry ≤ X μs |
| Ripple (X Vpp) | — | observe | observe | — | 0 unintended toggles |
| Brownout pulse | — | trip / ignore | recover | — | Meets T_ignore/T_must_trip |
Engineering Checklist (Design → Bring-up → Production)
This checklist turns UVLO thresholds into a repeatable engineering gate. Each phase produces artifacts that can be reviewed and accepted: budget and policy definitions in design, measured evidence in bring-up, and screening limits in production.
Design Gate
- Threshold budget completed Margin ≥ X V @ Y°C; includes ripple/droop/tolerance stack.
- UVLO_OFF / UVLO_ON policy documented Defines safe-state entry and recovery rule (auto vs latch).
- Fast-event strategy defined T_ignore / T_must_trip thresholds specified for dips.
- Split-rail behavior mapped (if applicable) Per-rail UVLO conditions → output state (LOW/Hi-Z/Clamp).
- Chatter risk evaluated Mitigation knobs selected (decap, Kelvin PGND, hysteresis, filtering).
Bring-up Gate
- Ramp thresholds measured at VDD(pin) UVLO_OFF/ON min/typ/max recorded; hysteresis computed.
- Ripple injection stays within contract 0 unintended toggles; validated at X Vpp / Y.
- Brownout pulses meet event policy Short dips ignored; long dips trip and enter safe state ≤ X μs.
- Safe state is predictable Output state matches definition; recovery window = Y ms stable rails.
- Observability is consistent /FLT and logs reflect UVLO events (auxiliary indicator, not sole trigger).
Production Gate
- ATE screening window defined Threshold window limits derived from lab min/max.
- Pin-state combinations verified /EN and /FLT behavior consistent with UVLO lockout and recovery policy.
- Recovery policy check included Auto vs latch behavior validated in a shortened production-friendly sequence.
- Traceability enabled Serial ID → measured thresholds → pass/fail stored for audits.
Phase pass criteria (fill X/Y/N):
- Design: margin ≥ X V @ Y°C; policies documented and reviewable.
- Bring-up: measured thresholds within window; 0 chatter / N minutes; safe-state timing ≤ X μs.
- Production: ATE windows and pin-state checks prevent shipment of units that violate UVLO contract.
Applications (Where UVLO Thresholds Make or Break You)
Applications differ in how UVLO is triggered and how recovery must behave. Each playbook below stays strictly on a UVLO axis: trigger shape → system consequence → policy & guardrails.
Application3-Phase Inverter
- Trigger shape: auxiliary bias droop or DC-bus disturbances reduce VDD(pin) below UVLO_OFF.
- Consequence: UVLO chatter breaks PWM determinism, causing repeated enable/disable and restart storms.
- Policy & guardrails: define recovery window = Y ms (stable rails) and require 0 toggles / N min around threshold; prefer deterministic safe-state entry (LOW/Hi-Z/Clamp).
Example BOM part numbers (gate-driver-focused):
Exact UVLO numbers and behavior depend on variant and must be verified in the datasheet.
ApplicationPFC + LLC (Burst / Light-load)
- Trigger shape: burst/skip operation creates a ripple envelope that crosses UVLO_OFF even when average VDD looks sufficient.
- Consequence: repeated UVLO entry re-triggers startup and produces non-deterministic restart timing.
- Policy & guardrails: specify an allowed ripple window such that the VDD valley stays ≥ X V above UVLO_OFF; require hysteresis/filter behavior consistent with T_ignore/T_must_trip.
Example BOM part numbers (gate-driver-focused):
Use these as starting points for UVLO behavior screening; verify UVLO thresholds and recovery mode per datasheet.
ApplicationPOL / VR (Multiphase)
- Trigger shape: one phase experiences larger local droop/ripple and hits UVLO earlier due to decoupling/layout asymmetry.
- Consequence: phase drop-out forces current redistribution and can create hot-spots and phase imbalance.
- Policy & guardrails: enforce threshold consistency (ΔUVLO ≤ X mV, placeholder) and a deterministic “phase-safe” response when a single channel locks out.
Example BOM part numbers (driver & multiphase building blocks):
Driver selection here prioritizes channel consistency and predictable lockout behavior; verify UVLO window and recovery policy per datasheet.
Application-to-Risk Mapping (UVLO axis)
Use the mapping below to keep application discussions UVLO-only. Each line indicates which UVLO failure mode dominates: droop, ripple, chatter, restart.
IC Selection Logic (Choosing UVLO Thresholds and Behaviors)
Selection must stay UVLO-specific: threshold shape, hysteresis, filtering/time behavior, safe-state output, recovery policy, and multi-channel threshold consistency. The decision tree below starts from the rail architecture and ends with an acceptance-ready UVLO contract.
Decision tree entry rules (UVLO axis only):
- Input: rail architecture (single / split ± / isolated bias) and dominant event type (droop / ripple / fast brownout).
- Output: UVLO type (fixed or programmable), behavior (latch or auto), and required margins (X/Y placeholders).
- Verification: every selected behavior must be bench-verifiable with the ramp + corner matrix.
UVLO-Related Spec Checklist (only)
| Selection item | Why it matters (UVLO-only) | Acceptance / pass criteria (X/Y/N) |
|---|---|---|
| UVLO_ON / UVLO_OFF range | Must avoid under-drive region and prevent half-conduction during droop. | Margin ≥ X V at valley; meets device drive window. |
| Independent ON/OFF thresholds | Defines an effective window against ripple without sacrificing protection intent. | Hysteresis window ≥ X V equivalent headroom. |
| Hysteresis size | Primary anti-chatter mechanism when ripple sits near UVLO_OFF. | 0 toggles / N minutes under injected ripple. |
| UVLO filter / delay / response | Defines T_ignore vs T_must_trip for fast events. | Short dips ignored; long dips trip within X μs. |
| UVLO safe-state output | Determines what the gate does at lockout: LOW, Hi-Z, or Clamp. | Safe state matches system contract; no ambiguous mid-level state. |
| Recovery policy | Auto vs latch defines whether the system chatters or recovers deterministically. | Recovery window = Y ms stable; deterministic state transitions. |
| Multi-channel threshold consistency | Prevents “one channel drops first” failures in multiphase and multibridge systems. | ΔUVLO_ON/OFF ≤ X mV across channels (placeholder). |
Concrete Part-Number Shortlist (UVLO-focused)
The parts below are grouped by UVLO needs. Use them as concrete BOM candidates and filter by required UVLO window and policy in the datasheet.
| UVLO need | Example part numbers (BOM candidates) | Typical fit (UVLO axis) |
|---|---|---|
| Isolated driver with strong UVLO contract | TI UCC21750, TI UCC21520, ST STGAP2SICS, ST STGAP2HD, Infineon 1EDC20I12MH, ADI ADuM4121, SiLabs Si827x | Inverters where droop and restart policy dominate |
| Bootstrap half-bridge driver with UVLO | TI UCC27714, TI UCC27211, Infineon IRS21867, Infineon IRS2003, onsemi NCP51530, ST L6398 | PFC/LLC bridges where ripple/chatter must be controlled |
| Low-side driver with defined UVLO behavior | TI UCC27531, TI UCC27614, Microchip TC4420, Microchip TC4427, onsemi NCP81074 (controller-side gating) | POL/VR and low-side stages where local droop causes early lockout |
| SR driver (secondary-side UVLO sensitivity) | TI UCC24612, TI UCC24610, onsemi NCP4306 | LLC secondary where burst behavior can create chatter windows |
| DrMOS integrated driver (phase consistency focus) | Infineon TDA21490, Renesas ISL99390, onsemi NCP302155 | Multiphase VR where per-phase UVLO mismatch is costly |
Note: the shortlist is intentionally UVLO-focused. Exact UVLO thresholds, timing filters, and recovery behavior vary by option code and must be confirmed in the datasheet before freezing the BOM.
Decision Tree Diagram (rails → knobs → recommended UVLO shape)
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FAQs (UVLO Thresholds)
Scope is strictly UVLO: thresholds, ripple, droop/brownout, chatter, and recovery policy. Each answer is fixed to 4 lines: Likely cause / Quick check / Fix / Pass criteria (X/Y/N placeholders).
