Power Mux / Priority Power Path: Policies, Sizing & No-Brownout Handover

Intro & Use Cases

In modern power systems, where multiple power sources are available (e.g., USB-C + Battery, Adapter + PoE, Main + Backup), the key challenge is to determine how to select the primary power source and achieve seamless switching between these sources without causing brownout or back-feed. Additionally, managing inrush current to avoid damaging components is a crucial factor. This page outlines key topology choices, priority policies, and quick sizing formulas (Δt, ΔV, C_hold, R_ds(on) loss), along with validation playbooks and layout/thermal guidelines to ensure a robust design in 48 hours.

Typical Use Cases

Here are some of the most common applications for Power Mux and Priority Power Path solutions:

• USB-C + Battery (Handheld/Industrial Devices)
  Use Case: Power is prioritized from the external adapter when plugged in, and switched seamlessly to battery when unplugged, with no interruption.
  Common challenge: Ensuring that the transition to battery does not cause a drop in power or affect device functionality. Relevant issue: Need for smooth handover with no voltage droop and no back-feed.
• Adapter + PoE (Cameras, Routers, APs)
  Use Case: When PoE power is lost, the system switches to adapter power; conversely, when the adapter is lost, PoE is used.
  Common challenge: Maintaining continuous power during PoE or adapter dropout events.
  Relevant issue: Controlling back-feed to avoid interference between the two power sources.
• Main Power + Backup Power (Servers, Gateways, Security Devices)
  Use Case: Ensuring that VOUT stays stable even during main power failures, keeping logs and system uptime uninterrupted.
  Common challenge: Smooth handover from main to backup power with minimal voltage drop.
  Relevant issue: Ensuring that no logging or critical systems lose power during the switchover.

Key Metrics

When designing for Power Mux and Priority Power Path systems, the following key metrics must be considered:

• VOUT Droop (ΔV): The maximum voltage drop allowed during source switching.
• Switching Time (Δt): The amount of time it takes to switch between power sources without causing power loss or glitching.
• Load Current Range: The range of load currents the system can handle without dropping voltage.
• Reverse Leakage: The amount of reverse current leakage during source switching.
• Thermal Rise: The temperature increase due to FET losses and the total power dissipated in the system.

Architectures & Policies

The architecture selection is crucial in ensuring optimal performance and minimizing losses in power mux systems. Below, we explore three major topologies for power path selection:

1) Diode-OR

– **Pros**: Simple, cost-effective, and low complexity. – **Cons**: High voltage drop (Vf), no priority logic, and limited tolerance for load variations.

2) Ideal-Diode Controller + Back-to-Back FET

– **Pros**: Low voltage drop, reverse blocking, fast switching, automatic ORing. – **Cons**: Doesn’t include priority logic; requires external control for switching logic.

3) True Power Mux (with Priority Logic)

– **Pros**: Built-in priority logic (automatic, fixed, manual), PG/UVLO windows, and supports remote control for switching. – **Cons**: More complex and expensive; requires proper configuration of thresholds and timing.

Priority Strategy

1. **Auto Highest-V**: Selects the highest voltage source. 2. **Fixed Primary with Brownout Override**: Keeps a primary source fixed and switches to the secondary when the primary drops below a defined threshold. 3. **Manual Select (GPIO/I²C)**: Allows the user to manually select the source through GPIO or I²C for testing or maintenance.

Design Rules

In designing Power Mux and Priority Power Path systems, engineers must consider various key design rules to ensure reliability, efficiency, and smooth operation. Below are the essential rules to follow in your designs:

Voltage Drop & Headroom

One of the first steps in designing power paths is calculating the minimum VOUT that will still supply your load effectively. This can be calculated using the formula:

    VOUT,min ≥ min(VIN,pri, VIN,sec) − ILOAD · Rpath
  

This formula ensures that the system will maintain a stable output voltage (VOUT) even under load, by accounting for the voltage drop in the power path resistance (Rpath).

FET Loss & Thermal Design

Power losses from FETs can significantly affect system performance and cause thermal issues. To manage these losses, use the following formula for calculating FET power dissipation:

    Ploss ≈ I² · Rds(on)
  

The total power dissipation (Ploss) is determined by the square of the current (I) multiplied by the FET’s on-resistance (Rds(on)). The junction temperature can then be calculated as:

    Tj = Tamb + Ploss · θJA
  

This helps in determining the thermal rise and ensuring that the system does not overheat during operation. Proper thermal design is essential to prevent failure and ensure longevity.

Switching and Hold-Up

During power path switching, it is crucial to maintain a stable output voltage (VOUT) without interruption. To achieve this, the hold-up capacitor must be properly sized to maintain power during the switching process. The required hold-up capacitor can be calculated using the formula:

    Chold ≥ Iload · Δt / ΔV
  

This formula ensures that the capacitor will maintain the output voltage during the switching period, where Δt is the switching time and ΔV is the voltage drop tolerance.

Inrush Current & dV/dt Limiting

Inrush current is the initial surge of current that occurs when switching power sources, which can cause damage to components. To limit the inrush current, the formula for inrush current is:

    Iinrush = Cload · dV/dt
  

By controlling the rate of change of voltage (dV/dt), you can limit the inrush current, preventing damage to both the power path and load.

Reverse Leakage Detection

Reverse leakage occurs when current flows from the load back into the power source, which can cause system instability or component damage. To prevent this, the controller threshold for reverse voltage and current must be carefully managed.

Design Example Images

Battery/Charger Power-Path

When designing power paths that include both the main power source and battery, it’s essential to ensure smooth operation in scenarios where both power sources are used simultaneously. The power-path must manage the system load and charge the battery while maintaining the system’s stability. This section will focus on system-path and battery-path coordination, emphasizing charging path collaboration, OTG mode, and under-voltage fallback to ensure proper operation.

System Path & Battery Path

The system-path (SYS/VSYS) supplies power to the load and also charges the battery simultaneously. It is important to ensure that this power-path allows for seamless transitions during plug/unplug events and that it does not introduce power dips or instability.

• System-path: External power to the load and battery charging; no interruption when power is plugged/unplugged.
• Battery-path: Discharge/OTG/Ship-mode; prevents simultaneous charging and discharging.

Key Collaboration Points

Ensuring smooth operation involves considering several factors such as PG/STAT signals from the charger, OTG mode decision-making, under-voltage fallback, and system cold startup to avoid instability.

• PG/STAT Signals: Used to detect charger presence and control charging behavior.
• OTG Mode: Ensures the device can act as a host when necessary.
• Under-voltage Fallback: Prevents damage by switching to an alternative power source when voltage drops.
• System Cold Start: Ensures that the system can power up smoothly even from a fully discharged battery.

Protections & Brownout Control

Reverse Blocking / Back-Feed

Use back-to-back (B2B) FETs oriented to block reverse current under all operating modes. Validate the controller’s reverse voltage/current thresholds and consider body-diode conduction as a failure/transition path.

• B2B orientation: sources tied together; diodes opposed to stop reverse flow.
• Thresholds: set reverse comparator limits below system tolerance to prevent back-feed.
• Failure modes: shorted FET or blown gate → body-diode path may appear; detect and isolate.

Cross-Conduction Suppression

Prevent both paths from conducting simultaneously. Gate timing must ensure non-overlap, with blanking/debounce during switchover.

• Gate timing: enforce dead-time; no overlap between primary/secondary FET gates.
• Sense & logic: PG/UVLO qualifiers plus minimum on/off timers to avoid chatter.
• Validation: scope gate nodes for overlap; monitor supply currents for shoot-through spikes.

UVLO/OVP Windows & PG Hysteresis

Define per-input UVLO/OVP windows and a VOUT window. Add hysteresis to PG to avoid oscillatory toggling when sources are close or noisy.

• Per-input UVLO/OVP: block bad sources before muxing; avoid false handovers.
• VOUT window: guarantees downstream rail integrity during transients.
• PG with hysteresis: PG_on > PG_off; plus deglitch time to suppress chatter.

Brownout Handling

Budget VOUT droop and Δt for handover; size hold-up and control ramp-rates. Manage recovery slope and load steps to keep the rail within tolerance.

• Droop budget: allocate ΔV across path losses and switchover; ensure C_hold ≥ I_load·Δt/ΔV.
• Recovery slope: dV/dt limited to keep I_inrush=C_load·dV/dt within stress limits.
• Load steps: verify light→peak transitions during/after handover at Tmin/Tmax.

Layout & Thermal

Minimize Hot Loops & Heavy Copper Paths

• Short, straight, wide: keep high-current paths short and wide; reduce resistive drop and heating.
• Star returns: separate power return from analog/sense return to avoid error injection.

B2B FET Placement & Kelvin Sensing

• Orientation: align B2B FETs with current flow; minimize via count in the power path.
• Kelvin source sense: route dedicated, thin sense lines to the source pins; keep sense loop small.
• Gate routing: avoid parallel high-dv/dt aggressors; add series gate resistors if required for stability.

Thermal Strategy

• Thermal vias under pads: array under FET tabs to move heat into inner/opp layers.
• Copper spreading: use planes to spread heat; avoid bottlenecks near device corners.
• Device spacing: mitigate thermal coupling; keep hot devices from clustering.

Quiet Analog & PG/UVLO Routing

• Keep away from hot loops: route PG/UVLO/STAT and comparators away from switching edges.
• Ground strategy: single-point reference for comparators; avoid large ground currents in sense paths.

Validation Playbook

Scope Setup & Probing

• Oscilloscope ≥100 MHz / ≥1 GSa/s; differential probes for VIN/VOUT; current probe or shunt for reverse current.
• Probe nodes: VIN_PRI, VIN_SEC, VOUT, key FET gates, PG/STAT. Optional IR camera for thermal snapshots.
• Triggers: VIN_PRI drop/remove; PG edge; (for manual switching) I²C/GPIO marker.

Triggers & Measurements (Core Quantities)

• Trigger: Primary VIN brownout/remove, or controller switchover indicator.
• Observe:
  • VOUT droop ΔV (mV): peak-to-valley / steady-to-steady.
  • Switchover delay Δt (µs–ms): trigger to VOUT back within threshold.
  • Gate overlap: any non-zero simultaneous ON window → cross-conduction risk.
  • Reverse leakage I_rev: within the window, confirm within limits.

Worst-Case Matrix

• Environment: T_min / T_max.
• Electrical: minimum headroom (VIN ≈ VOUT + drop), maximum C_load, light/nominal/peak load.
• System: with/without charger attached; sources close in voltage / alternating.
• Record: ΔV, Δt, cross-conduction? reverse leakage? pass/fail per combination.

Fault Injection

• Reverse order plug-in (secondary first, then primary; and vice versa) → watch back-feed and chatter.
• UVLO sweep (ramp primary below UVLO) → verify hysteresis/deglitch.
• OTG mis-detect stress (frequent cable toggling near threshold) → check SYS stability and no charge/discharge conflict.
• Momentary primary interruption (ms-level) → confirm override policy and C_hold sufficiency.

Pass / Fail Criteria

• ΔV ≤ budget; Δt within spec; no cross-conduction; no over-limit reverse leakage; PG/STAT logic matches waveforms.
• On fail: save waveforms & thermal data; log exact scenario; iterate thresholds/policies/timing.

Brand / IC Examples

By Function (Examples)

Quick Selection Hints

• Only need automatic ORing → Ideal-diode controller + back-to-back FETs.
• Need fixed primary / manual / remote policy → Power mux / source selector (I²C variants are most flexible).
• Need charger coordination → System power-path charger and align its PG/UVLO with the mux.

FAQs

Resources & RFQ