Intro & Standards (Qi TX/RX)
Qi wireless charging uses magnetic induction in the sub-MHz band with standardized power profiles. Start with the BPP baseline for wearables and earbuds, scale to EPP for mainstream phones, and adopt Qi2 MPP with magnetic alignment for higher coupling and tighter thermal control. Interoperability depends on coil design (single vs. array), mechanical alignment, and compliance features like FOD and thermal reporting.
For battery charging specifics see Battery Charger PMIC; for inrush/over-current events see eFuse / Hot-Swap Controller.
System Architecture
A Qi system splits into a TX path (control/modulation → bridge driver → TX coil) and an RX path (rectification → DC/DC → system/battery). Power is negotiated through the Qi channel; protection and telemetry (FOD, temperature, OCP/OVP) enforce safe operation. Reverse charging (phone→TWS/watch) is an optional RX feature.
Duty/frequency/phase modulation; FOD & temp inputs.
Sync rectifier + Buck/Buck-Boost; efficiency vs. heat.
System-first vs. direct battery charge; PG/FLT hooks.
Optional back-power to small loads (TWS/watch).
Coils & Magnetics
Design the coil and magnetic path first—geometry drives L, R, and Q; compensation capacitors close the loop at the operating band. Ferrite sheet μr, loss, and thickness set coupling and thermal behavior. Mind the gap and lateral misalignment, and plan shielding for nearby metal to keep k high and FOD events under control.
Specify L at operating band; track RDC and Q with an impedance sweep.
Pick topology (series/parallel), ESR class, and temp stability for tight tuning.
Thicker/higher-μ improves k but watch loss/heat; avoid warpage.
Keep clearance from metal; log FOD events during step-power tests.
Power Path & Protections
The RX path converts AC to DC via a rectifier (diode or synchronous), then regulates through a Buck/Buck-Boost to the system/battery power path. Prevent reverse current with ideal-diode OR-ing, define protection thresholds (OCP/OVP/UVP/OTP), and coordinate with Qi negotiation. Reverse OTG is optional and must be power-limited.
SR for efficiency; verify turn-off timing to avoid reverse conduction.
System-first vs battery-first; expose PG/FLT to host for safe fails.
B2B FET + OR-ing; confirm no reverse flow from USB-C/5V rails.
Derate → retry → latch-off, with thermal and FOD feedback.
Communication & FOD
Qi links use ASK/FSK signaling for RX→TX feedback. A session progresses through Handshake → Power Ramp → Regulated → End. Foreign Object Detection (FOD) monitors inductance/loss/thermal cues and compares against tuned thresholds to derate, retry, or shut down safely.
Identification/Config, Power Request/Control, Temperature/Power, Error/End.
Increase in steps; verify thermal and FOD flags each step.
Start conservative; add temp/position compensation; validate at hot/cold.
Capture time, step, T_coil/T_PMIC, Δx, gap, FOD/fault bits for analysis.
Thermal & Efficiency
Heat sources include coil copper loss and magnetic loss, rectifier/DC-DC conduction and switching loss, and misalignment-induced extra loss. Build clear thermal paths with planes and via arrays, stitched heatsinks, and chassis coupling. Efficiency falls as Δx/gap grow—plan derating and alignment aids accordingly.
Coil copper/magnetic loss, rectifier/DC-DC loss, misalignment overhead.
Stitch planes + dense via arrays; couple to chassis through pads/graphite.
Step power, hold 5–15 min, log T_coil/T_PMIC/T_case at each Δx/gap.
Define safe/derate zones and enforce limits via communication feedback.
Layout & EMI
Keep the high-frequency loop area small, separate power and control domains, and route Kelvin sense pairs cleanly. Place resonance capacitors tight to the coil/matching node, provide solid reference returns, and reserve safe probe access. These practices reduce EMI, improve efficiency, and make bring-up faster.
High-frequency Loop
Bridge → matching → coil path compact and symmetric; mirror bridge halves and keep gate loops short with proper damping.
Domains & Shielding
Physical split of power vs. control; use stitched ground fence; couple shield/cover to ground through a capacitor for RF only.
Kelvin Sense
Sense+/− run directly to the source pads; avoid sharing vias/planes with load current; star-ground PG/FLT/NTC.
Resonance Caps
Low ESR/ESL types, close to the node; add copper pour + via arrays for heat spreading.
Probing & Debug
Reserve pads across shunt/diode; add loop for current probe; spec high-impedance divider at resonant nodes.
EMI First-Aid
Gate resistors, RC snubbers, symmetric routing, ferrite edge clearance, and managed coil-to-metal gaps.
Validation & Certification
Validate with structured tests—power ramp, load steps, alignment matrices, and foreign-object tables—while logging packets, temperatures, and limits. A clear pre-check → fix → lab test → report path accelerates Qi certification and reduces rework.
5–10% steps; 5–15 min holds; record derate/limits and packet trace.
±10/30/50% transients; observe stability, resets, and FOD behavior.
Grid of Δx × gap; map efficiency & temps; define safe/derate zones.
Metal size/material/position; track false-/miss-detection and tune thresholds.
Attach firmware rev, BOM/layout rev, photos/IR images, signatures/time-stamps.
IC Selection (7 Brands)
Compare transmitter (TX) and receiver (RX) families across seven vendors without locking to a single datasheet. Focus on power class, integration level, FOD capabilities, digital I/O, and automotive options.
| Brand | TX / RX | Power Class | DC/DC | Communication | FOD | Automotive | Recommended Uses |
|---|---|---|---|---|---|---|---|
| TI (bq) | TX families | EPP Qi2 MPP | External bridge + matching | I²C, IRQ, NTC | Loss window, temp derate | Selected AEC-Q | Phone pads, in-vehicle mounts |
| TI (bq) | RX families | BPP EPP | Buck / Buck-Boost | I²C, PG/FLT | Threshold + compensation | Consumer / some auto | TWS cases, wearables, phones |
| NXP | TX | EPP Qi2 | Integrated controller + driver | I²C, GPIO | Multi-metric FOD | Options | Phones, multi-coil mats |
| NXP | RX | BPP EPP | Buck | I²C, IRQ | Loss/ΔL + temp | — | Wearables, accessories |
| ST | TX | EPP | Driver + external FETs | I²C | Power gap detect | Automotive variants | In-vehicle, instrument clusters |
| ST | RX | BPP EPP | Buck-Boost options | I²C, status pins | Derate/retry | — | Phones, small devices |
| Renesas | TX | EPP Qi2 | Controller + bridge | I²C, ADC | Adaptive thresholds | Auto-friendly | Car mounts, dashboards |
| Renesas | RX | BPP | Buck | I²C | Loss & temp | — | Wearables/TWS |
| Infineon | TX (controller + drivers) | EPP Qi2 | External MOSFETs | I²C, diagnostics | FOD + thermal headroom | AEC-Q options | Automotive pads, multi-coil |
| Infineon | RX | EPP | Buck-Boost | I²C | Threshold & profiling | — | Phones, rugged devices |
| onsemi | TX | BPP EPP | Controller + gate drivers | I²C, INT | Loss/ΔL + temp | Industrial/auto lines | Budget multi-coil, mats |
| onsemi | RX | BPP | Buck | GPIO/I²C | Basic FOD | — | Low-cost wearables |
| Microchip | TX (MCU-centric) | BPP EPP | External drivers | I²C/UART (MCU) | Firmware-tuned | Long-life/industrial | Custom pads, maker/industrial |
| Microchip | RX | BPP | Buck | I²C | Configurable | — | Accessories, small loads |
Wearables / TWS (<10 W)
Favor compact RX with integrated Buck, basic FOD, and simple I²C. Coils are small—prioritize thermal limits.
Phones / General (≈15 W)
RX Buck-Boost, robust FOD and temperature feedback, PG/FLT to host. TX supports precise ramp and multi-coil or magnetic alignment.
Automotive / Rugged
Pick AEC-Q variants with diagnostics, wide temp, and conservative derating. Validate Δx/gap and FOD across hot-soak cycles.
FAQs
Answers to frequent engineering questions on FOD, misalignment, metal backs, thermal behavior, derating, and interoperability. Each item links to the most relevant chapter for deeper context.
How do I diagnose frequent FOD false positives?
Log Pin/Prx, effective inductance/loss, and temperatures while stepping power in 5–10% increments. Sweep a grid of Δx/gap and compensate thresholds for alignment and ambient. Validate at cold/room/hot.
What does a metal back cover or ring do to efficiency and heat?
It reduces coupling k and increases eddy-current loss. Add ferrite thickness, keep a clearance to metal, and derate power at higher temps. Map the safe region via Δx/gap sweeps.
Misalignment causes “no charge”—where to start?
Check Δx/gap against your design window, re-tune compensation caps around the operating band, and verify ramp policy and FOD thresholds aren’t prematurely limiting power.
See Coils, FOD thresholds.
Thick cases reduce efficiency—how much and what to adjust?
Extra gap lowers k and raises loss. Expect a step down in efficiency beyond a few millimeters; favor Qi2 magnetic alignment, and plan a derate curve tied to temperature and Δx/gap.
See Efficiency vs Offset.
When is synchronous rectification not better?
At very light loads or during transitions, SR can reverse conduct if turn-off timing is late. Verify gate timing and add ideal-diode OR-ing to block backfeed.
See Power Path.
How should I set derating for hot automotive cabins?
Define temperature guard bands with hysteresis and limit power under poor alignment. Validate hot-soak with Δx/gap sweeps and thermal steady-state holds (5–15 min).
Cross-brand interoperability fails to reach target power—what to tune?
Adjust ramp slope/steps, broaden FOD windows with temperature/position compensation, and ensure packet timing and error handling follow the common state machine.
See Communication.
How to cap Reverse OTG safely?
Impose a low power limit with timeouts, monitor PMIC and coil temperatures, and block backfeed via ideal-diode OR-ing to wired rails.
See Power Path.
What are the backfeed checks with USB-C present?
Confirm no reverse current from 5 V rails into the RX path; use back-to-back FETs, sense voltage with Kelvin routing, and verify transitions between wired/wireless sources.
See Power Path, Layout.
EMI spikes—what’s the first-aid list?
Reduce loop area, balance bridge routing, increase gate resistors, add RC snubbers, and ensure shielding gaps and ferrite edges are clear of coil currents.
See Layout & EMI.
What’s the minimum calibration/log set to keep?
Timestamp, power step, Tcoil/TPMIC/Tcase, Δx, gap, FOD/fault bits, firmware rev, and layout/BOM revision.
See Validation.
Common reasons a Qi submission gets bounced?
Incomplete FOD characterization, missing hot-soak data, inconsistent packet logs, or labeling/mark compliance gaps. Provide pre-check reports and traceability.
See Certification flow.
Handling coil/ferrite batch variance?
Profile efficiency and temperature across batches and introduce dynamic offsets in FOD thresholds; re-tune compensation if the resonant point drifts.
Priorities when both wired and wireless are present?
Prefer the more efficient source with clean switchover; avoid tug-of-war by OR-ing and policy that drops wireless when wired exceeds a current/voltage threshold.
See Power Path.
Resources & RFQ
Access downloadable templates for FOD tuning, power ramp logging, and coil parameter calculations. Submit your BOM to receive tailored recommendations within 48 hours.
FOD Tuning Sheet (XLSX)
Grid-based for Δx/gap adjustments, threshold tuning, and false/miss detection.
Download FOD SheetPower Ramp Log (PDF)
Track power step, duration, and thermal data for each stage of the ramp-up.
Download Ramp LogCoil Parameter Calculator (XLSX)
Calculate coil parameters such as inductance, resistance, and resonance frequency.
Download Coil CalculatorSibling Pages
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