Audio/Voice PMIC — Low-Noise Rails & Pop-Free

Q: Why does in-band PSRR matter for AVDD?

In-band PSRR (20 Hz–20 kHz) attenuates ripple where hearing is most sensitive, keeping codec analog paths quiet. PSRR depends on EA gain-bandwidth and the output capacitor’s ESR/ESL. If hiss persists, add a post-LDO and tune RC/LC after the pre-regulator. See Working Principle and Design Rules.

Q: How do I eliminate pop/click at startup or shutdown?

Use a slew-controlled ramp (≈5–20 ms) and coordinate EN/MUTE: mute first, then ramp; reverse the order on power-down. Gate amplifier enables with power-good so rails settle before release. If clicks persist, lengthen the ramp or add a brief mute hold. See Working Principle and Design Rules.

Q: What noise level is acceptable for MIC bias in arrays?

Target ±1–2% bias accuracy and noise density below ~100 nV/√Hz to avoid hiss and inter-element coupling. Use star routing with end-point decoupling near each microphone tail. If ripple rises under load, check returns and increase local caps. See Working Principle and Applications.

Q: Should AVDD, DVDD and PVDD power up in a fixed order?

Yes—bias/reference first, then AVDD → DVDD → PVDD, with power-good gating each release. This prevents pop and undefined logic states. For shutdown, reverse the order to avoid output jumps. Verify edge timing at PG, EN/MUTE and each rail. See Design Rules and Validation & Debug.

Q: How do I probe rails and PG without loading the circuit?

Use ×10 probes, short grounds and measure at device pins. Capture ramp slope, steady-state ripple (p-p or rms) and PG threshold/delay. For noisy captures, reduce loop area or use coax with proper termination. Document acceptance bands per rail. See Validation & Debug.

Q: PVDD load steps pull AVDD down—how do I fix it?

Physically separate PVDD, limit inrush and tighten loop areas. Increase AVDD decoupling at codec pins and verify post-LDO stability. Measure ΔV and recovery; if PG chatters, raise thresholds or add delay. A short mute window around step events also helps. See Design Rules and Validation & Debug.

Q: Hot-start causes inconsistent sequencing—what’s wrong?

Residual charge can reorder rails and cause PG chatter. Discharge sensitive nodes or add hold-off before re-enable. Ensure POR, ramp and PG thresholds are deterministic across temperature. Validate with repeated hot-plug tests and matched loads. See Validation & Debug.

Q: Will brownout corrupt voice-wake or cause false triggers?

Use a UV comparator plus a hold timer to assert mute and drop PG during dips, then restore the normal sequence after recovery. Verify by injecting controlled sags and logging thresholds/durations. Consider longer de-glitch for automotive profiles. See Working Principle and Validation & Debug.

Q: How do I reduce crosstalk in PDM microphone arrays?

Star-route MIC bias from a single node, add end-point decoupling at each element and keep returns short and separated. If channels couple under bursts, increase local caps and inspect shared vias/planes near array tails. See Applications.

Q: Do I need RC/LC after a low-noise LDO?

Add RC/LC only if residual ripple or switching harmonics remain in the audio band. Place the filter near the load, then confirm stability and PSRR improvement at codec pins. If ringing appears, adjust R/C values or output capacitor ESR. See Design Rules.

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Intro — Problems to Applications

Audio/Voice PMICs deliver quiet rails, pop-free ramps and deterministic sequencing for codecs/DSPs, microphone arrays and class-D/H amplifiers. This page focuses exclusively on audio power rails (AVDD/DVDD/PVDD), MIC bias and de-pop timing—no battery protection, eFuse or general DC/DC topics.

Typical applications include headphones/TWS, smart speakers/soundbars, voice-wake modules and optional in-vehicle audio & voice. Design goals are consistent: low in-band ripple/PSRR for analog paths, controlled enable/mute ramps to eliminate pop/click, stable and low-noise MIC bias for PDM/analog microphones, and predictable power-good-gated sequencing across rails.

Still unsure which audio PMIC fits your codec or mic array? Submit your BOM for a cross-brand suggestion within 48 hours. ← Back to PMIC Hub

High-level blocks only; details follow in the Architecture section.

Architecture — Audio Power Rails

Rails & Roles

Audio rails split into AVDD (analog codec/ADC/DAC), DVDD (logic/DSP), PVDD (class-D/H) and MIC bias/VREF. AVDD typically uses a post-LDO with RC/LC filtering to improve in-band PSRR for the audio path; MIC bias requires tight tolerance and low noise to avoid hiss and array crosstalk.

Isolation & Decoupling

Keep AGND/DGND domains separated with a single-point tie, route PVDD as a power path with small loop area, and place decoupling close to pins. AVDD often benefits from a low-noise LDO after a pre-regulator plus RC/LC where ripple persists in the 20 Hz–20 kHz band.

Sequencing & De-Pop

Use power-good to gate enables and coordinate AMP EN/MUTE. A controlled ramp (≈5–20 ms) eliminates pop/click during power-up; apply reverse order on power-down. A sample order is: reference/bias → AVDD → DVDD → PVDD.

Protection & Brownout Immunity

Implement UVLO/OVP, short-circuit/thermal foldback and brownout handling so audio paths remain stable under dips and surges—especially for voice-wake scenarios where unintended triggers must be avoided.

Rails & roles, isolation/decoupling, sequencing/de-pop, and protection; focused on audio power only.

Working Principle — Audio/Voice PMIC Internals

Reference & Error-Amplifier Chain

A band-gap reference feeds the error-amplifier (EA), which drives the pass element (LDO or switch) through a feedback network. In-band PSRR (20 Hz–20 kHz) depends on EA gain-bandwidth and the output capacitor’s ESR/ESL. Proper compensation keeps the audio path quiet and stable.

Reference→EA→Pass→Feedback chain; in-band PSRR shaped by EA GBW and output capacitor ESR/ESL.

Low-Noise Post-LDO (“Last-mile” Noise Reduction)

A pre-regulator (buck or upstream LDO) feeds a low-noise post-LDO for AVDD. Output noise density combines reference and EA noise; keep the decoupling point close to codec/MIC pins with short return paths.

Pop/Click Suppression

A soft-start current charges C_SS (or an internal cap) to create a slew-rate-controlled ramp. Sequence EN/MUTE: mute first then ramp; reverse on power-down. Keep input and output bias in sync to avoid fast jumps.

Mute → ramp → enable; reverse on power-down to avoid audible transients.

MIC Bias Regulation

MIC bias uses a linear reference with a low-drift amplifier and current limiting. Typical design targets: tolerance ±1–2% and noise density <100 nV/√Hz. Use star routing with end-point decoupling to minimize array crosstalk.

Star routing with local decoupling reduces crosstalk among microphone elements.

PVDD Power Path & Inrush Control

Keep PVDD physically separate from AVDD. Use inrush control (slew or current limit) to avoid AVDD droop during power-up. Gate amplifier enables with PG/Fault signals and apply de-pop mute before PVDD rises.

Sequencing FSM

Typical power-up sequence: POR → Ramp → PG → AMP_EN. Power-down reverses it: AMP_MUTE → Ramp-down → PG-low. For brownout, an undervoltage comparator plus a hold timer prevents unintended voice-wake triggers.

Separate PVDD/AVDD domains; inrush limiter on PVDD; PG/Fault drives a simple enable FSM.

Probes & Expected Waveforms

Check AVDD/DVDD/PVDD ramp slopes, steady-state ripple, PG thresholds, and MIC bias ripple. Inspect the pop/click window within tens of milliseconds around EN/MUTE edges. Under load steps, record ΔV and recovery time against your acceptance bands.

Design Rules — Actionable for Audio Power

Optimize In-Band PSRR (20 Hz–20 kHz)

Rule: Use a low-noise post-LDO and add RC/LC when residual ripple persists in the audio band; choose output capacitors to place helpful zeros versus EA poles.

When: Audible hiss or ripple shows up on AVDD lines.
Targets/Quick check: In-band ripple < defined limit; PSRR notch within 20 Hz–20 kHz.
Validate: Scope at codec pins; sweep with audio-band stimulus if available.
Common failure: ESR/ESL mismatch → move to different cap series or add small RC.
IC signals: TI TLV758xx; ST LDLN/LDLN0xx; onsemi NCP167.

Schedule De-Pop Ramp & Mute

Rule: Apply a 5–20 ms ramp and gate AMP enables with PG; mute before ramp, reverse on power-down.

When: Startup/shutdown clicks or pops are heard.
Targets/Quick check: No audible transient; ramp within 5–20 ms.
Validate: Four-track timing capture: MUTE/EN/RAMP/AMP_OUT.
Common failure: EN and MUTE unsynchronized → add delay or invert logic as needed.
IC signals: TI TAS58xx family (enable/mute control); NXP TFA98xx (amp control context).

Stabilize MIC Bias & Star-Route Arrays

Rule: Aim for ±1–2% bias accuracy and <100 nV/√Hz noise; use star routing with end-point decoupling to reduce crosstalk.

When: Arrays show hiss or inter-element coupling.
Targets/Quick check: Bias drift within ±1–2%; ripple below your mic spec.
Validate: Measure at array tails; compare with single-element baseline.
Common failure: Shared returns → re-route to star topology, add local caps.
IC signals: Microchip MCP1799 (LDO context); Renesas ISL9001A; ST LDLN025.

Sequence Rails for Clean Audio Startup

Rule: Power reference/bias first, then AVDD → DVDD → PVDD; use PG thresholds and delays to coordinate releases.

When: Startup is inconsistent or sensitive to load states.
Targets/Quick check: Deterministic order with verified PG gating.
Validate: Trigger on PG rising; verify EN edges relative to each rail.
Common failure: PG too early → add delay/threshold margin.
IC signals: TI TLV/TPS LDOs (PG variants); NXP PF series (sequencing context).

Control PVDD Transients & Ground Bounce

Rule: Limit inrush and separate PVDD loops from AVDD; keep switch currents away from analog ground and verify recovery under load steps.

When: Class-D bursts pull down other rails or inject noise.
Targets/Quick check: ΔV and recovery time within acceptance bands.
Validate: Step PVDD load; watch AVDD ripple and PG stability.
Common failure: Shared return loops → re-route and tighten loop area.
IC signals: onsemi NCP2820 (amp supply context); TI TAS58xx (enable control).

Validation & Debug — Oscilloscope Probes, Scenarios and Root-Cause Fix

Probing Points (4–6 Channels Recommended)

AVDD / DVDD / PVDD: ramp slope (ms), steady-state ripple (mV p-p/rms)
PG (power-good): threshold, jitter and delay vs rail stability
EN / MUTE: edge order and gating relationship
MIC Bias: DC level, ripple and short-term drift at the array tails

Mute → ramp → enable; PG after rail settles; no audible transient on AMP_OUT.

Test Scenarios (Cold/Hot Start, Steps, Bursts, Brownout)

Cold start: 0 V power-up follows reference → AVDD → DVDD → PVDD; verify no pop/click.
Hot start: residual charge must not reorder sequencing; PG should not chatter.
Load step: class-D or wake pulses; record ΔV and recovery time vs acceptance bands.
Burst toggling: rapid AMP enable/mute; ensure controlled output and no spikes.
Brownout: dips trigger PG-low and AMP_MUTE; voice-wake should not false-trigger.

Under PVDD steps, confirm AVDD ΔV and recovery; during brownout, PG drops and mute is asserted to prevent false voice-wake.

Troubleshooting — Pop/Noise/Sequencing

Pop/Click: EN/MUTE wrong order or ramp too steep → delay EN, lengthen ramp (5–20 ms), mute first then ramp; reverse power-down.
Noise/Howl: in-band PSRR insufficient or PVDD noise coupling → add post-LDO + RC/LC; separate PVDD domain; star-route MIC bias with end-caps.
Bad sequencing: PG threshold too early or delay too short → raise threshold and add hold; discharge before hot start.
Step droop: inrush or burst currents → limit inrush, increase AVDD decoupling, tighten loop areas.

Applications — Rails, Key Parameters and Validation

Codec + DSP

Rails: AVDD (low-noise), DVDD (logic), VREF (reference). Key parameters: in-band PSRR for AVDD, post-LDO after pre-reg, PG-gated DSP enable. Validation: codec-pin ripple/PSRR, PG stability, cold/hot start consistency.

IC signals: TI TLV758xx; ST LDLN025/LDLN0xx; Renesas ISL9001A.

Microphone Array (PDM / Analog)

Rails: MIC bias (±1–2% target) and possible 1.8/3.3 V front-end. Key parameters: noise density <100 nV/√Hz, star routing and end-point decoupling. Validation: ripple at array tails and inter-element crosstalk.

IC signals: Microchip MCP1799; ST LDLN025; onsemi NCP167.

Class-D/H Amplifier

Rails: PVDD (power path) with physical separation from AVDD. Key parameters: inrush limiting, synchronized ramp and AMP EN/MUTE gating. Validation: AVDD ΔV and recovery under PVDD steps; no audible pop.

IC signals: TI TAS58xx family; NXP TFA98xx; onsemi NCP2820.

Voice Wake-Up

Rails: low-noise standby supply with repeatable fast wake. Key parameters: brownout handling, PG de-glitch and bias stability. Validation: no false triggers during dips; matched cold/hot starts.

IC signals: TI TLV/TPS (PG variants); NXP PF series; Renesas low-noise LDO.

Each module lists rails, key parameters and validation points with non-comparative IC examples.

IC Selection Examples — Non-Comparative, Application-Oriented

The following examples point to application fit for audio power rails (AVDD/DVDD/PVDD), MIC bias and sequencing. They are not a comparison matrix; each line is a directional cue to help engineers pick a starting point.

Tag icons indicate the application context of each example; no cross-brand comparisons are implied.

Texas Instruments (TI)

TLV758xx — low-noise LDO used as a post-regulator for codec analog rails. #AVDD #PSRR
TAS58xx family — enable/mute control context for amplifier power path and de-pop coordination. #PVDD #DePop #Sequencing

STMicroelectronics (ST)

LDLN025 / LDLN0xx — ultra-low-noise LDO for analog audio rails or microphone front-ends. #AVDD #MICBias
STA350BW (context) — class-D related control path for synchronized mute/enable. #PVDD #Mute

NXP

PF series (context) — multi-rail sequencing and power-good gating on audio boards. #Sequencing #PG
TFA98xx family — amplifier control and supply gating coordination in audio paths. #PVDD #DePop

Renesas

ISL9001A / ISL9021A — low-noise LDO for AV rails and precision references. #AVDD #VREF
RAA/ISL (context) — support for amplifier gating and power-path coordination. #PVDD #Mute

onsemi

NCP167 — low-noise LDO for MIC bias or analog front-end rails. #MICBias #AVDD
NCP2820 (context) — companion device for amplifier supply routing. #PVDD

Microchip

MCP1799 / MCP17xx — small-current low-noise LDO for microphone or front-end rails. #MICBias #FrontEnd
MCPx (PG variants) — enable/PG options to enforce clean startup order. #Sequencing #PG

Melexis

MLX81xxx (automotive domain) — used where voice subsystems sit in body domain supplies. #Automotive #Domain
Automotive LDO context — low-noise sub-rails supporting in-vehicle voice paths. #AVDD #Brownout

Out of stock or EOL? Submit your BOM for a 48 hour cross-brand replacement suggestion.

FAQs — Real Questions from Search, Engineer Communities and Social Threads

Concise, actionable answers (45–60 words) that link back to the relevant sections. No cross-brand comparisons; focused solely on audio/voice power management ICs.

Why does in-band PSRR matter for AVDD?

In-band PSRR (20 Hz–20 kHz) keeps codec analog paths quiet by attenuating ripple where human hearing is most sensitive. PSRR is shaped by EA gain-bandwidth and the output capacitor’s ESR/ESL. If hiss persists, add a post-LDO and tune RC/LC after the pre-regulator. Jump to: Working Principle · Design Rules.

How do I eliminate pop/click at startup or shutdown?

Use a slew-controlled ramp (≈5–20 ms) and coordinate EN/MUTE: mute first, then ramp; on power-down, reverse the order. Gate amplifier enables with power-good to ensure rails are quiet before release. If clicks persist, lengthen the ramp or add a brief mute hold. Jump to: Working Principle · Design Rules.

What noise level is acceptable for MIC bias in arrays?

Target ±1–2% bias accuracy and noise density below ~100 nV/√Hz to avoid hiss and inter-element coupling. Use star routing with end-point decoupling near each microphone tail. If ripple rises under load, check return paths and increase local caps. Jump to: Working Principle · Applications.

Should AVDD, DVDD and PVDD power up in a fixed order?

Yes—bias/reference first, then AVDD → DVDD → PVDD, with PG gating each release. This avoids pop and undefined logic states. For shutdown, reverse the order to prevent output jumps. Verify edge timing at PG, EN/MUTE and each rail. Jump to: Design Rules · Validation & Debug.

How do I probe rails and PG without loading the circuit?

Use ×10 probes, short grounds and measure at the device pins. Capture ramp slope, steady-state ripple (p-p or rms), and PG threshold/delay. For noisy captures, reduce loop area or use coax with proper termination. Document acceptance bands per rail. Jump to: Validation & Debug.

PVDD load steps pull AVDD down—how do I fix it?

Separate PVDD physically, limit inrush, and tighten loop areas. Increase AVDD decoupling at codec pins and verify the post-LDO stability. Measure ΔV and recovery; if PG chatters, raise thresholds or add delay. Consider a brief mute during step events. Jump to: Design Rules · Validation & Debug.

Hot-start causes inconsistent sequencing—what’s wrong?

Residual charge can reorder rails and make PG chatter. Discharge sensitive nodes or add hold-off before re-enable. Ensure POR, ramp and PG thresholds are deterministic across temperature. Validate with repeated hot-plug tests and matched loads. Jump to: Validation & Debug.

Will brownout corrupt voice-wake or cause false triggers?

A UV comparator plus a hold timer should assert mute and drop PG during dips, then restore the normal sequence after recovery. Verify no false triggers by injecting controlled sags and logging thresholds/durations. Consider longer de-glitch for automotive profiles. Jump to: Working Principle · Validation & Debug.

How do I reduce crosstalk in PDM microphone arrays?

Use star routing from a single MIC bias node, add end-point decoupling at each element, and keep returns short and separated. If channels couple under speech bursts, increase local caps and inspect shared vias/planes near the array tails. Jump to: Applications.

Do I need RC/LC after a low-noise LDO?

Add RC/LC only when residual ripple or switching harmonics remain in the audio band. Place the filter near the load, then confirm stability and PSRR improvement at the codec pins. If ringing appears, adjust R/C values or output capacitor ESR. Jump to: Design Rules.

Any guidance for class-D/H amplifier enable/mute timing?

Keep PVDD separate, assert mute, then raise rails; release the amplifier only after PG is stable. For shutdown, mute first, then ramp down PVDD. A short mute window around load steps also prevents clicks. Validate with four-track timing captures. Jump to: Working Principle · Applications.

My recommended PMIC is out of stock—can I request a cross-brand alternative?

Yes. Share your codec/amp type, rail voltages, ramp targets, PG logic, and footprint constraints. We’ll return a 48-hour cross-brand suggestion aligned to your validation plan—no comparison tables, just an application-fit shortlist. Jump to: IC Selection Examples.

Still unsure which audio PMIC fits your codec or microphone array? Submit your BOM for a 48h cross-brand recommendation.

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Audio/Voice PMIC ICs for Codecs, Microphones & Class-D Amps

Intro — Problems to Applications

Architecture — Audio Power Rails

Rails & Roles

Isolation & Decoupling

Sequencing & De-Pop

Protection & Brownout Immunity

Working Principle — Audio/Voice PMIC Internals

Reference & Error-Amplifier Chain

Low-Noise Post-LDO (“Last-mile” Noise Reduction)

Pop/Click Suppression

MIC Bias Regulation

PVDD Power Path & Inrush Control

Sequencing FSM

Probes & Expected Waveforms

Design Rules — Actionable for Audio Power

Optimize In-Band PSRR (20 Hz–20 kHz)

Schedule De-Pop Ramp & Mute

Stabilize MIC Bias & Star-Route Arrays

Sequence Rails for Clean Audio Startup

Control PVDD Transients & Ground Bounce

Validation & Debug — Oscilloscope Probes, Scenarios and Root-Cause Fix

Probing Points (4–6 Channels Recommended)

Test Scenarios (Cold/Hot Start, Steps, Bursts, Brownout)

Troubleshooting — Pop/Noise/Sequencing

Applications — Rails, Key Parameters and Validation

Codec + DSP

Microphone Array (PDM / Analog)

Class-D/H Amplifier

Voice Wake-Up

IC Selection Examples — Non-Comparative, Application-Oriented

Texas Instruments (TI)

STMicroelectronics (ST)

NXP

Renesas

onsemi

Microchip

Melexis

FAQs — Real Questions from Search, Engineer Communities and Social Threads

Request a Quote

Accepted Formats

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