USB-C PD / PPS Controller — What This Page Covers
A USB-C PD/PPS controller negotiates safe power over CC/PD, reads cable E-Marker data, and coordinates protections (OVP/OCP/OTP) to safeguard your system. Practical success depends on PDO planning, PPS loop stability, cable derating, and clear fault/retry behaviors.
Applies To
Laptop/tablet/phone fast-charge sinks; camera & industrial handhelds; controller-level source/DRP in hubs or automotive modules.
Out of Scope
Battery charger power-path specifics; eFuse/Hot-Swap/Load Switch deep dives; USB data/ALT-mode PHY topics.
Back to PMIC Hub: Power Management ICs (PMIC)
Still unsure which USB-C PD/PPS controller fits your design? Submit your BOM for a 48h cross-brand recommendation.
Architecture — Where the Controller Sits in Your System
Blocks: Type-C Port, CC/PD PHY, PD Policy Engine (PDO/PPS), MCU/Firmware (optional), Cable E-Marker, Protections (OVP/OCP/OTP), Power Path (hint only).
Working Principle — CC/PD Negotiation & Strategy
From attach to power-ready, a USB-C PD/PPS controller determines roles on CC, evaluates Source capabilities, requests a suitable PDO/PPS profile, then maintains power with AVS updates while enforcing safe derating and clear fallback paths.
CC Attach & Role
Detect CC1/CC2 and Rp/Rd to settle UFP/DFP/DRP. Only raise or draw VBUS after a valid attach and role lock.
PDO Table & Request
Parse Source_Capabilities; choose the lowest stable voltage that meets current demand, then scale up as thermal and efficiency allow.
PPS AVS Loop
Use bounded V-step/I-step with a minimum dwell time; align AVS update cadence with the supply loop to avoid ripple-induced faults.
Cable E-Marker & Derating
Read SOP′ E-Marker for current/voltage capability and ID. If absent/invalid, derate or fall back to 5 V PDO.
Exceptional Paths
Handle Wait/Reject (capability changes or conflicts) and Hard Reset; gracefully drop from PPS to a fixed PDO when required.
Healthy Trace Pattern
Typical sniffer log: Source_Cap → Sink_Request → Accept → PS_RDY, then periodic PPS AVS with bounded steps.
Tip: Log Source_Cap, Sink_Request, Accept, PS_RDY, and AVS commands with timestamps. If E-Marker is absent or invalid, derate and fall back to a safe PDO.
Design Rules — Checklists You Can Apply
Copy-ready rules for PDO planning, PPS steps & sampling, cable authentication, protection thresholds, and thermal/fault policy.
PDO Planning Checklist
- Cover 5/9/15/20 V common rails; add margin for cable loss and temperature.
- For multi-port sources, reserve a fallback PDO for re-allocation events.
- Choose the lowest stable voltage meeting current demand; revisit for efficiency/thermals.
Document a “must-run” PDO and a “preferred” PDO per product SKU.
PPS Step & Sampling
- Bound V-step/I-step within the supply loop bandwidth to avoid oscillation.
- Enforce a minimum dwell time per step; rate-limit AVS commands.
- Set ripple/max transient per AVS cycle (ΔV/ΔI) and verify under load steps.
Align telemetry sampling with AVS cadence to prevent false trips.
Cable Auth + Source Cap Composition
- If E-Marker read fails or is out of spec, disable high-V/high-I and revert to 5 V PDO.
- Derate current for long/active cables per resistance and temperature rise.
- Compose limits with Source_Capabilities; use the intersection as the safe envelope.
Record cable ID in logs to correlate field failures with specific lots.
Protections: Thresholds & Delays
- OVP: target rail + loop/ADC/ripple error budget; avoid nuisance trips on AVS edges.
- OCP: include peak load, cable drop, and temperature derating.
- OTP: compute from junction-to-case/ambient; bind to auto-retry or latch policy.
Use digital filtering or delay so short spikes don’t trigger faults; only sustained violations do.
Thermal Design & Fault Policy
- Map power hotspots (controller, external FETs, connectors) and provide copper/airflow paths.
- Define user-visible messages: “PPS not supported”, “Cable limited”, “Derated to 9 V”, etc.
- Specify orderly fallback: PPS → best fixed PDO → 5 V safe mode.
Keep a one-page “fault → action” matrix for service teams.
Validation & Debug — Ticket-Style Checklist
Validate negotiation and power integrity with a repeatable capture flow, a boundary-condition matrix, and a symptom->cause decision tree. Archive artifacts (PDO/PPS, cable policy, thresholds) for future builds.
PD Sniffer Setup & Capture Script
Connect to CC1/CC2, probe VBUS, and log temperature near the connector. Export structured logs.
- Include charger ID / port index / firmware build / cable E-Marker VID:PID / current class / ambient & case temperature.
- Only enable load after PS_RDY; timestamp every AVS update and any protection event.
Boundary Condition Matrix
Sweep voltage, current, cable class, temperature, and source type. Capture ripple (mVpp), overshoot, settling time, negotiated profile.
- Voltage: 5/9/15/20 V + PPS window
- Current: idle / nominal / peak step
- Cable: passive 3 A, E-Marked 5 A, long/active
- Source: single-port vs multi-port (re-allocation)
- Thermal: 0 °C / 25 °C / 45 °C / 60 °C
- Firmware: baseline vs AVS rate-limited vs adjusted delays
Failure Signatures → Next Probe
- PPS falls back to fixed PDO: PPS unsupported / AVS too fast / cable limit → verify E-Marker, slow AVS cadence, re-request.
- No PS_RDY: malformed Request / power conflict → re-request lower PDO, check multi-port re-allocation.
- Hard Reset loop: OVP/OCP trip or dwell too short → relax delays, widen error budget, verify load step.
- VBUS droop: cable drop / source current cap → derate current or reduce AVS step size.
- Ripple trips: loop crossover vs AVS rate → sync sampling with AVS, add digital filtering.
Artifacts to Archive
- Final PDO/PPS table (target & fallback), cable whitelist/blacklist with E-Marker classes.
- Protection thresholds & delays, AVS cadence (∆V/∆I, dwell), derating policy card.
- “Fault → Action” matrix and sanitized sniffer logs for regression.
Need a review of your validation matrix or AVS cadence? Submit your BOM for a 48h cross-brand recommendation.
Applications — Minimal Working Recipes
Four reference recipes with controller-level presets: PDO/PPS, cable policy, protections, and validation focus.
Laptop / Tablet (Sink)
High-power sink with optional PPS during dynamic workloads.
- Minimal Stack: Type-C receptacle → CC/PD PHY → PD policy → (MCU logging) → Protections → Power-path.
- Negotiation: prefer 20 V PDO; fallback 15 V; PPS for ramp-up only.
- Presets: V-step 20–60 mV; I-step 50–100 mA; dwell ≥ 60–100 ms.
- Cable Policy: require 5 A E-Marked for 20 V; auto-derate otherwise.
- Validation Focus: multi-port re-allocation; sleep/wake transients; connector temperature.
Phone Fast-Charge (Sink)
Thermally constrained sink with aggressive AVS cadence.
- Negotiation: start 9 V PDO; use PPS to match SoC thermal window.
- Presets: dwell ≥ 40–80 ms; ripple target ≤ 50–80 mVpp at battery rail.
- Cable Policy: allow 3 A passive for mid-power; block unknown E-Markers above 9 V PPS.
- Validation Focus: screen-on steps; camera/video bursts; user-visible fallback messages.
Camera / Industrial Handheld (Sink)
Rugged sink with wider environmental range.
- Negotiation: prioritize 9/15 V PDO; PPS for transient-heavy features (RF Tx, flash).
- Presets: V-step 20–40 mV; I-step 50 mA; conservative delays for cold starts.
- Cable Policy: whitelist short, low-R cables; apply strong derating at 0 °C / 60 °C.
- Validation Focus: attach time in cold; plug/unplug bounce; EMI on CC lines.
Automotive Input Module (Nav/DVR) — Source/DRP
Source-side controller with tight thermal/power budget.
- Minimal Stack: PD policy (source table) + pre-reg from 12 V; protections tuned for crank/brown-out.
- Negotiation: advertise 5/9 V PDO; avoid high-V unless thermals allow.
- Presets: cap current to fit enclosure thermals; PPS optional/limited.
- Cable Policy: enforce E-Marker for >3 A; reject questionable cables.
- Validation Focus: cold crank/brown-out; EMI; ignition cycle behavior; persistent logs.
IC Selection — Standalone PD/PPS Controllers vs Chargers with PD Policy
Choose between a standalone PD/PPS controller (maximum firmware flexibility, re-usable policy across platforms) and a charger/PMIC with built-in PD policy (shorter power-path integration and smaller BOM). Below are representative parts from seven major vendors, with roles, PPS notes, and quick selection hints.
Bucket A — Standalone USB-C PD/PPS Controllers
Texas Instruments (TI) — TPS65987D / TPS65988, TPS25750
DRP/Source/Sink controllers widely used in docks and notebooks; PPS support depends on config; I²C/Flash policy with external MCU optional.
- Why pick: mature ecosystem, multi-port use, robust policy manager.
STMicroelectronics (ST) — STUSB4500, STUSB1602, STUSB4710/4711
STUSB4500 simplifies Sink PDO requests; STUSB1602 covers Type-C/PD at the sink; STUSB4710/4711 target source-side.
- Why pick: quick bring-up for sinks; clear application notes and NVM presets.
Microchip — UPD301A
Standalone PD3.0/PPS controller with integrated policy engine; good docs and reference designs for rapid adoption.
- Why pick: minimal external firmware burden; portable across product lines.
NXP — PTN5110
Type-C/PD PHY partnered with your MCU running the PD stack; ideal if you want full control of policy and state machine.
- Why pick: best for teams owning firmware and needing custom behaviors.
onsemi — FUSB302B, NCP81239
FUSB302B offers low-cost Type-C/PD PHY (external stack required); NCP81239 targets source-side PD control.
- Why pick: cost-efficient building blocks for custom PD stacks.
Infineon (Cypress EZ-PD) — CCG3PA / CYPD3175, CCG6/CCG7D
Proven USB-PD controllers used in adapters and accessories; configuration-friendly with EZ-PD toolchains.
- Why pick: solid app notes and ecosystem for both source and sink designs.
Analog Devices / Maxim — MAX77958
USB-C CC/PD controller used in mobile and accessory designs; integrates well with MAX charger families.
- Why pick: clean integration with ADI/Maxim power path and charger ICs.
Bucket B — Chargers / PMICs with Built-in PD Policy
Renesas (Intersil) — ISL9238, RAA489800
Buck-boost battery chargers with USB-C PD support for notebooks/tablets; strong efficiency and system telemetry.
- Why pick: proven notebook platforms and reference designs.
Texas Instruments (TI) — TPS25762
Integrated buck-boost power path with PD policy; suited for mobile/handhelds and compact industrial devices.
- Why pick: reduces external FETs and shortens bring-up.
NXP — PCA9460 / PCA9461
High-efficiency switch-mode chargers used in PD/PPS phone fast-charge designs; compact, thermally aware.
- Why pick: mobile-grade performance and ecosystem support.
onsemi — NCP81231 / NCP81234
Source-side solutions for adapters/hubs; PD policy integrated at the power-stage controller level.
- Why pick: practical path for source-only or multi-port adapters.
Infineon (Cypress EZ-PD) — CCG3PA / CYPD3175-based adapters
Adapter-class solutions where PD policy integrates with the primary power controller for PPS fast charging.
- Why pick: mature tooling and extensive application notes for adapters.
Analog Devices / Maxim — MAX77818 / MAX77860 (family context)
Charger families commonly paired with ADI/Maxim PD controllers to realize PD/PPS sinks in mobile devices.
- Why pick: cohesive integration with MAX77958 and related parts.
STMicroelectronics (ST) — STUSB4710/4711-based source path with ST charger stage
Source-side PD policy using STUSB47xx combined with ST power-stage controllers for adapter/hub designs.
- Why pick: clear partition between PD policy and high-voltage stage, easing compliance.
Integration Notes
- Cable policy: enforce 5 A E-Marker for high-power rails; on failure, derate or drop to 9 V/5 V.
- Protections: align OVP/OCP/OTP thresholds and delays with PPS AVS steps and dwell to avoid nuisance trips.
- Logging: record charger/port ID, cable E-Marker class, AVS cadence, and temperatures for field triage.
Always verify final capabilities in the latest datasheet and compliance guides for PD3.0/PPS.
Still unsure which USB-C PD/PPS controller fits your codec or microphone array? Submit your BOM for a 48h cross-brand recommendation.
FAQs — Practical Answers for PD/PPS Integration
Tightly scoped, engineer-first guidance. Each answer links to deeper sections for architecture, negotiation strategy, design rules, validation workflow, and IC selection.
Why does PPS negotiation sometimes fall back to a fixed PDO?
How should I choose the initial PDO versus starting directly with PPS?
What are sensible V-step, I-step, and dwell values for stable PPS AVS?
What is the safe policy when the cable’s E-Marker is missing or invalid?
Why do I see Accept but never PS_RDY in the trace?
How do I set OVP/OCP/OTP thresholds and delays without nuisance trips?
Multi-port chargers keep re-allocating power. How can I stay stable?
How should I measure PPS ripple and transient response correctly?
When should I trigger a Hard Reset versus a soft recovery?
Standalone PD/PPS controller or charger with built-in PD policy—which fits better?
How much current derating is prudent for long or active cables?
How do I plan firmware hooks for updating the PDO table in the field?
What does a “healthy” PD/PPS sniffer trace look like?
Resources & CTA
Wrap up your design with a cross-brand recommendation, or continue into related power-path topics for a complete solution.
Submit Your BOM (48h)
We map your PDO/PPS plan, cable policy, and protections, then return cross-brand options aligned to your constraints.
Submit BOMRelated Topics
Jump back to: Architecture • Working Principle • Design Rules • Validation • IC Selection
