Single-Inductor Buck-Boost (SEPIC/Zeta)
Single-Inductor Buck-Boost (SEPIC/Zeta) — Intro
Single-inductor SEPIC/Zeta is a non-inverting buck-boost architecture that uses a single magnetic core (coupled inductor, typically 1:1 with k ≈ 0.95–0.99) plus a series coupling capacitor (Cc). It naturally supports CV/CC, enables gentle start-up current limiting, and can be made pre-bias friendly across wide VIN. Tradeoffs include a right-half-plane zero (RHPZ) that constrains bandwidth, strict Cc RMS/ESR sizing, and damping for leakage inductance.
Definition
“Single-inductor” here means a single magnetic component with two windings on one core (a coupled inductor). Together with a series coupling capacitor Cc, it forms a non-inverting buck-boost converter: SEPIC or Zeta. Both deliver a positive output from a positive input while stepping voltage up or down.
- SEPIC/Zeta share similar power stages; they differ in the energy transfer path and ripple distribution.
- Using one magnetic core reduces volume and loop area; Cc sets RMS stress and start-up surge.
- Well-suited to CV/CC loads (LEDs, auxiliary rails, sensor/measurement fronts) with soft-start limiting.
- Limits: RHPZ caps control bandwidth; verify Cc RMS/ESR; damp Llk with RC/RCD.
Next we compare SEPIC vs Zeta power paths, ripple placement, and high-dv/dt hot loops to guide compensation, layout, and validation.
Principle — Conversion, Ripple, and Limits
In continuous conduction and ideal form, the single-inductor SEPIC/Zeta buck-boost follows a boost-like conversion law while its control bandwidth is constrained by a right-half-plane zero (RHPZ). Coupling alters ripple sharing across windings, and the series coupling capacitor Cc must keep low impedance at fSW to avoid excess ripple and start-up surge.
Conversion Ratio (CCM, Ideal)
For SEPIC/Zeta in CCM and ideal components:
VOUT/VIN ≈ D/(1−D).
Near D≈0.5 the input RMS current rises and stresses increase; at high D, efficiency and
transient behavior degrade, so margining is required in practical designs.
Inductor Ripple & Coupling Effects
Ripple current per winding follows
ΔIL ≈ (VL/L)·(D·Ts).
With a coupled inductor, winding ripples are correlated (set by coupling factor k and dot orientation),
which redistributes copper/core loss and thermal hotspots. The effective inductance Leq
depends on k and the energy path in SEPIC vs Zeta.
RHPZ & ESR Zero
The buck-boost-like right-half-plane zero limits voltage-loop bandwidth:
fRHPZ ≈ RLOAD(1−D)² / (2π·Leq).
Output capacitor ESR introduces a zero:
fZESR ≈ 1/(2π·COUT·ESR).
The coupling capacitor impedance must be small around the switching frequency:
|XCc| ≈ 1/(2π f Cc) « channel impedance.
Dual-Loop Control for CV/CC
A current inner loop (peak or valley with proper slope compensation) plus a voltage outer loop (Type-II commonly, Type-III for higher BW within RHPZ limits) implements CV/CC. ILIM and SS (soft-start capacitor or digital ramp) coordinate gentle start-up and pre-bias behavior.
These principles set the guardrails for component selection and compensation. Next we turn them into copy-able design rules.
Design Rules — Copy-able Process
Use this step-by-step flow to size the coupled inductor, coupling/output capacitors, rectification, limits, and compensation while respecting RHPZ, EMI, and thermal targets.
Set min/nom/max VIN, target VOUT, load range. Reserve
10–20% efficiency/thermal margin and include cold/hot corners.
ΔIL ≈ 20–40% · IL,avg; choose k≥0.95, often 1:1.- Isat ≥ IPK with temp derating; shielded core preferred.
- Compute copper/core loss vs
fSW, material (ferrite/iron powder),Bmax.
- Check RMS current (often a sizable fraction of switch/input current).
|XCc(fSW)|must be small; verify ESR and bias/temperature drift.- Prefer film + MLCC in parallel; X7R arrays to overcome DC bias loss.
Split ripple target into charge and ESR parts. Add small series-R for damping/ESR-zero shaping when needed.
- Diode: rate
Iavg, Irms, VF, reverse recovery. - Synchronous FET: dead-time, reverse conduction, gate damping, driver slew trade-offs.
Choose peak vs valley limit (mode-boundary behavior near D≈0.5). Set SS cap/digital ramp and
ILIM threshold; ensure pre-bias safe start without reverse discharge.
- Rule:
BW ≤ fRHPZ/5–10. - Voltage loop Type-II (typical) or Type-III (higher BW cases within limits).
- Slope compensation for peak mode; avoid jitter at mode boundary in valley mode.
- Minimize hot-loop area; input π / dual-T filters; RC/snubber for leakage spikes.
- Spread-spectrum: beware probe ground-lead artifacts and analyzer RBW misreads.
Compute RθJA for FET/diode/inductor. Use copper spreading and via arrays; validate with
steady-state hot-spot maps (≥10-min soak).
ΔIL = 20–40% · IL,avg|XCc(fSW)|« channel impedanceBW ≤ fRHPZ/5–10
- Pre-bias safe soft-start
- Snubbers for leakage spikes
- Via arrays for hot devices
With these rules in place, proceed to Layout & EMI and Validation to lock stability and compliance.
Layout & EMI — Hot Loops and No-Shake Rules
To keep a single-inductor SEPIC/Zeta stable and quiet, minimize hot-loop area, route proper return paths, and place the coupling capacitor Cc next to the switching nodes. Use Kelvin sensing for current sense, partition PGND/AGND, and add damping (RC/RCD and gate resistors) to tame leakage-induced ringing.
- Shortest path from VIN decoupling to FET to ground return.
- Keep high-dv/dt node compact; avoid crossing ground splits.
- Place snubber near FET; short, wide traces.
- Diode/SR FET close to inductor and output caps.
- Return straight to output ground, not via signal ground.
- Gate damping (SR) to prevent reverse conduction chatter.
- Bulk + high-freq MLCC right at VIN/FET pins.
- Dual-path: HF to power ground, bulk to quiet ground star.
- Use via arrays to anchor to ground plane.
- Cc adjacent to the two coupled-inductor nodes.
- Symmetric entry/exit and mirrored return to reduce parasitics.
- Film + MLCC in parallel; shortest loop area wins.
Dots & Winding Orientation
Match dot polarity to the controller’s reference. A reversed dot pair shifts ripple sharing and can inject unexpected common-mode noise. Verify after assembly with a quick scope check across windings at light load.
- Do: keep winding start/finish consistent with schematic dots.
- Don’t: route the dot node across plane splits.
Kelvin Sense & Grounding
Kelvin route the sense resistor; isolate AGND from power currents and join at a single star near the IC AGND pin.
- Do: dedicated sense pair to Rsense pads.
- Don’t: tie AGND into switch loop returns.
Damping & Gate Control
Place RC/RCD snubbers at the culprit node (FET or rectifier). Set gate resistors to balance loss vs ringing and meet EMI margins; validate dead-time for synchronous rectification.
Layer Stack & Return Paths
Top: power routing; inner: continuous ground plane; bottom: signals. Avoid signal lines crossing plane gaps; guide return directly under the forward path to cancel fields.
- Place Cc tight to the switching nodes.
- Keep continuous ground plane under power routes.
- Kelvin sense Rsense; single AGND-PGND star point.
- Cross plane splits with fast nodes.
- Loop snubbers through long vias.
- Share AGND with power returns.
With loop areas minimized and grounds disciplined, you can confidently validate start-up, mode boundaries, loop gain, EMI, and thermal behavior.
Validation — Scripted Tests & Reusable Logs
Validate across start-up conditions, VIN/VOUT crossings, loop gain, EMI, and thermal steady state. Pay special attention near D≈0.5 (VIN ≈ VOUT), where mode boundaries and current-limit transitions are most sensitive.
Start-Up Suite
- Cold/hot start; pre-bias present; sweep soft-start slope vs inrush and output dip.
- Record: rise time, Vdip, input current peak, switch-node spikes, PG/EN timing.
- Confirm ILIM behavior (fold-back vs clamp) does not latch or chatter.
Across VIN & Mode Boundary
- Sweep VIN through VIN ≈ VOUT (around D≈0.5); watch for subharmonics and peak↔valley limit handover.
- Apply load steps (25%↔75%), linear sweeps of VIN/IOUT; log overshoot/undershoot and settling.
Loop Gain — CV & CC
- Target BW ≤ fRHPZ/5–10; phase margin 45–60° with load/temperature corners.
- Injection point at the error amp or current sense; keep injected amplitude small to avoid nonlinearity.
- With spread-spectrum, average/qp detectors may read differently—note analyzer RBW/VBW.
EMI — Conducted & Radiated
- Conducted (LISN, 150 kHz–30 MHz) and radiated (1 m/3 m). Keep probe ground leads short to avoid false peaks.
- Correlate bench scans to chamber results; verify snubber and filter damping remain stable across VIN.
Thermal Imaging
- Full-load soak ≥10 min; capture max device temps and ΔT to ambient.
- Compare to RθJA estimates and loss models; check for via starvation under hot parts.
| Condition | Key Measurements | Pass Criteria | Notes |
|---|---|---|---|
| Cold start, min VIN, max load | Inrush peak, Vout dip, PG timing, Vsw spike | No latch; dip < spec; spike < abs max | SS ramp tuned; ILIM verified |
| VIN sweep through VIN≈VOUT | Subharmonics, limit mode handover | No oscillation; seamless handover | Observe near D≈0.5 |
| Load step 25%↔75% | Overshoot/undershoot, settling time | BW target met; PM within spec | Loop injection correlates |
| Conducted EMI (LISN) | QP/Avg limits vs mask | Below limit with margin | Filter damping stable |
| Thermal soak ≥10 min @ full load | Max device temp, ΔT, IR map | Tj < rating; hotspots acceptable | Via arrays present under hot parts |
Thresholds Sheet
| Parameter | Target | Measured |
|---|---|---|
| ILIM | — | — |
| UVLO/OVP | — | — |
| SS slope | — | — |
Inrush/Sag Sheet
| Test | Peak/Dip | Settling |
|---|---|---|
| Cold start | — | — |
| VIN dip | — | — |
| Load step | — | — |
Loop Parameters Sheet
| Item | Value | Notes |
|---|---|---|
| fRHPZ | — | BW ≤ fRHPZ/5–10 |
| ESR zero | — | — |
| PM / GM | — | PM ≥ 45–60° |
ICs & Selection Matrix — Single-Inductor SEPIC/Zeta
Real, SEPIC-capable parts only. “Controller” rows drive external MOSFETs; output current is set by the power stage. Values are typical summaries for quick screening—verify against the datasheets for final sizing.
| Brand | Type | PN | VIN Range | IOUT (max) | fSW | Sync | Gate Driver | SS / ILIM | Spread-Spectrum | LED / General | AEC-Q100 | Notes |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| TI | Controller | LM3478 | 2.97–40 V | Ext MOSFET | 100 kHz–1 MHz (adj.) | Optional (external SR) | Low-side driver | Soft-start, cycle-by-cycle | No (sync pin only) | General / LED | LM3478Q-Q1 available | Boost/SEPIC/flyback capable; current-mode. |
| TI | Controller | TPS40210 / TPS40211 | 4.5–52 V | Ext MOSFET | Adj. (typ. 200–600 kHz) | Optional (external SR) | Low-side driver | Programmable SS, cycle-by-cycle | No | General / LED | Q-1 options | Boost/SEPIC/flyback; 0.7 V / 0.26 V ref (40210/40211). |
| ST | Controller | HVLED001A | Offline; 85–305 Vac (HPF) | Up to ~150 W systems | QR / variable | No (diode) | Integrated | Peak current mode; programmable | No | LED | No (std. industrial) | Flyback / buck-boost PFC; SEPIC also supported. |
| NXP | Integrated SBC | FS27 (with SEPIC front-end) | Automotive 12/24 V systems | Front-end supply (configurable) | Internal controller | No (SEPIC controller) | Integrated | Programmable limits | — | General (SBC power) | Yes; ASIL-capable | SBC includes SEPIC controller for 24 V withstand. |
| Renesas | LED Controller | ISL1904 | Offline (PFC LED) | By power stage | CrCM control | No | Integrated | Primary-side regulation; OCP | — | LED | No | Supports boost, Ćuk, SEPIC, buck-boost topologies. |
| onsemi | LED Driver | NCP3066 / NCV3066 | Up to 40 V | LED CC; by sense & MOSFET | ~150 kHz (adj.) | No (diode) | Integrated switch / driver | Current-regulated LED CC | No | LED | NCV grade available | Buck/boost/SEPIC LED driver controller. |
| Microchip | Controller | MCP1631HV | +5.5–16 V (HV) | Ext MOSFET | High-speed PWM (ext. clock) | Optional (external SR) | External MOSFET driver | Peak current-mode; programmable | No | LED / General | Automotive-friendly variants | Frequently used for SEPIC LED/charger designs. |
| Melexis | LED Driver | MLX10803 | Automotive supply (wide) | By power stage | Controller-set | No | Integrated | Programmable LED current | — | LED | Automotive oriented | General-purpose high-power LED driver; SEPIC usable. |
Tip: shortlist by VIN domain first (low-voltage DC vs. offline mains), then decide “controller vs integrated”, and finally check SS/ILIM and RHPZ-limited bandwidth targets.
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FAQs — Single-Inductor SEPIC/Zeta
Practical answers for sizing the coupling capacitor, handling RHPZ limits, soft-start, mode boundaries around D≈0.5, EMI and measurement hygiene. Each entry includes a takeaway threshold or formula to copy into your design notes.
How do I size the coupling capacitor to avoid overheating yet limit inrush?
Make |XCc(fSW)| = 1/(2πfSWCc) much lower than the series path impedance while checking the RMS current from worst-case duty and ripple. Use multiple X7R MLCCs in parallel with a small film cap to tame ESR shift. Verify temperature rise at max VIN and load; add soft-start pre-charge if needed.
Peak-current limit vs valley-current limit near D≈0.5 — which is safer?
At the mode boundary (VIN≈VOUT), peak limiting resists subharmonics but aggravates overshoot; valley limiting gives smoother recovery yet risks chatter with shallow slope compensation. Rule of thumb: ensure effective slope ≥ 0.5× inductor down-slope and confirm no period-doubling in a VIN sweep through D≈0.5.
How can I tune dead-time without increasing diode conduction loss?
Start with short dead-time, add gate damping to control dv/dt, then extend only until cross-conduction vanishes on scope. Check body-diode current plateau; target <50–100 ns for mid-power designs. Validate over temperature and at highest VIN—dead-time usually grows with slower gates and snubber loading.
How do I support pre-bias start-up without reverse discharge?
Keep the synchronous rectifier disabled until VOUT ramp exceeds pre-bias; use diode rectification or SR with strong reverse blanking. Coordinate SS, ILIM, and PG so the current loop limits first. Confirm no negative current through the inductor during soft-start by probing VSW and inductor current.
Why does input RMS current spike around certain duty cycles?
SEPIC/boost move higher energy through the input at intermediate duty, raising RMS stress. For ideal CCM, VOUT/VIN≈D/(1−D); near D≈0.5 the product of inductor ripple and average current often peaks. Choose bulk electrolytics with ripple margin and test at VIN that makes VOUT≈VIN.
Does spread-spectrum break loop measurements or compensation?
It does not change small-signal poles/zeros but smears the injected tone. For Bode work, disable spread-spectrum or measure in average/peak-hold with adequate RBW/VBW. Keep compensation values fixed; only re-validate margins. Re-enable dithering for EMI after confirming bandwidth and phase margin.
How do I choose magnetic core material for wide-VIN SEPIC/Zeta?
Use ferrite for high fSW and low core loss; use iron-powder where ripple is large and saturation headroom matters. Shielded parts cut EMI. Size for ΔIL=20–40%·IL,avg, verify Isat at hot corner, and check copper/core loss at min and max VIN.
How should I chain PG with a downstream LDO/VRM?
Gate the next rail with SEPIC/Zeta PG plus a short delay (1–5 ms) to avoid double correction during ramp-up. Keep return grounds separate and meet the VRM’s UVLO/soft-start requirements. If the downstream regulator sinks current, ensure your pre-bias policy prevents reverse discharge.
Soft-start slope vs inrush: what relationship matters most?
Make the SS ramp such that the inner current loop is always in control. Empirically, set SS time ≥ 5–10× output LC time-constant and confirm input inrush does not exceed bulk capacitor ripple rating. For large Cc, consider pre-charge or a current clamp during the first milliseconds.
What RC filter can I place on the current-sense signal without destabilizing?
Keep the filter pole above one-tenth of fSW and below the switching noise corner. Typical: fp ≈ 0.1–0.2·fSW with a small zero at the slope-comp point if needed. Verify the injected-signal phase in the Bode plot does not erode phase margin <45°.
When should I switch to a 2-switch inverting converter for a −V rail?
Prefer 2-switch inverting when negative output current is high, isolation of return currents is critical, or SEPIC/Zeta efficiency falls from diode loss and RHPZ-limited bandwidth. It offers cleaner return paths and easier compensation at high gains, at the expense of extra FET and driver complexity.
USB-PD: how do I keep regulation during PDO transitions?
Reduce bandwidth near the transition and cap slew on the commanded setpoint. Coordinate EN/SS with PD events so the current loop remains dominant. Validate worst cases: stepping VIN upward across D≈0.5 and large load changes; ensure no overshoot violates the sink’s OVP window.
Crank and falling-VIN ride-through: any duty limits or protections?
Set a maximum duty clamp to keep the switch within SOA and maintain margin from RHPZ. Add UVLO with hysteresis and current limit fold-back during deep dips. Test cold-crank profiles and log recovery time; avoid prolonged operation where D→1 and the loop loses control authority.
How low should I cap bandwidth under the RHPZ constraint?
Use BW ≤ fRHPZ/5–10. This gives space for load variation and ESR-zero placement. For LED CC, pick the lower side of that range to reduce flicker from line ripple; for tightly regulated rails, approach the upper side after confirming ≥60° phase margin across temperature.
Synchronous rectification vs Schottky — where is the crossover?
SR wins when I·VF loss dominates and thermal headroom is tight. Use a Schottky below a few hundred milliamps or when pre-bias start-up simplicity matters. Account for dead-time, reverse conduction, and gate losses; confirm EMI does not worsen from faster edges with SR.
Need a verified SEPIC/Zeta short-list?
Send your VIN range, VOUT, IOUT and constraints. We’ll return a cross-brand matrix, first-pass risks, and compensation targets—ready to validate within 48 hours.
- Coverage: low-voltage DC and offline front-ends, LED and general CV/CC rails.
- Deliverables: selection matrix, design limits (RHPZ-aware), and validation checklist.
- Your inputs: VIN(min/nom/max), VOUT, IOUT, startup constraints, size/thermal limits.
