What is EMI in Switching Regulators?
Electromagnetic interference (EMI) in buck/boost/buck-boost supplies is unwanted energy created by fast dv/dt and di/dt at the switching node and high-di/dt loops. It couples via stray C/L into cables, planes, and nearby circuits and is measured as conducted (150 kHz–108 MHz) and radiated (30–300 MHz).
- Hot loop — smallest high-di/dt loop (VIN MLCC → switch → inductor → ground)
- SW node — switching copper; main dv/dt source
- Conducted EMI — noise on power leads; checked with a LISN (150 kHz–108 MHz)
- Radiated EMI — noise through space; cables/loops act as antennas (30–300 MHz)
- DM / CM — differential-mode (through loop) / common-mode (to chassis/cables)
How it works
EMI follows a simple chain. Fix items in this order for best results.
- Source — SW node edges, gate/diode reverse recovery, current spikes
- Path — loop area and return currents (planes, parasitic C/L, cabling)
- Victim — sensors, clocks, ADC refs, I/O lines, enclosure
- Minimize loops — place smallest VIN MLCC within 2–3 mm of pins
- Tame SW geometry — small polygon, via-fence to ground, signal keep-out
- Partition grounds — PGND vs AGND with a single tie near sense/IC pad
- Only then add parts — RC snubber / boot-R / CM choke as needed
- Verify — near-field probe → LISN pre-scan → A/B with identical setup
Layout first. Parts second. Validate every change.
- Shrink high-di/dt loops
- Compact, shielded SW node
- Partition PGND vs AGND (single tie)
- RC snubber / boot-R after layout
- Verify: near-field → LISN → A/B
Identify the Hot Loops
- VIN MLCC pad-to-pin ≤ 2–3 mm; keep ESL path ≲ 1 nH
- Compact SW polygon; no signal traces through it
- Stitch 6–10 GND vias around SW (2–3 mm pitch)
- Place the smallest VIN MLCC first (≤2–3 mm to pins)
- No signal vias through the SW polygon
- 6–10 stitching vias to GND around SW (2–3 mm pitch)
- Route FB/ADC on an inner layer with ground shielding
Copper & Ground Partitioning
Keep noisy power currents away from sensitive returns; rejoin once at a controlled point near the IC.
- Separate PGND and AGND; join once near the IC ground reference
- Place VIN/BOOT MLCCs within 2–3 mm (pad-to-pin)
- Keep gate-drive loops short; no plane slots under them
- Route FB/REF on an inner layer with AGND shielding
- Via-fence around SW polygon; stitch AGND around sense corridor
Snubbers & Boot-R: When and How
Fix geometry first. If ringing (10–200 MHz) remains: fit RC snubber from measurements, then adjust boot-R for dv/dt.
- Measure SW ringing; note fring and decay (ground spring on probe)
- Start: Csnub ≈ 1.5–3× Cpar; Rsnub ≈ √(L / Csnub)
- Thermal check of snubber R (ΔT < ~25 °C at worst case)
- Boot-R start 5–22 Ω; balance dv/dt vs loss
- Use gate-R split when you need fast turn-off but slower turn-on
Input/Output Filtering & Ferrites
Treat the regulator + filter as one system. Place DM/CM filters where the noise travels and always add damping when needed.
- Place DM filter at VIN pins; CM choke at the cable/connector
- Bead: check |Z|@100 MHz, DC-bias derating, SRF, and IDC margin
- Input LC: re-check inrush and source impedance vs control loop
- Output filter: add damping (series-R or Zobel) and re-run Bode/load-step
Sense, Feedback, and Gate Drive Hygiene
Protect the reference. Kelvin returns to AGND, FB far from SW, and a tight gate loop to suppress recovery spikes and dv/dt issues.
- Kelvin sense → AGND; single-point tie to PGND at IC
- Place Cff and anti-alias RC at the pins (tiny loops)
- FB/ADC lanes on an inner layer with AGND corridor; avoid SW crossings
- Minimize gate loop; manage recovery and dv/dt (boot-R / split-R / clamp)
Layout Checklist (Copy-Paste)
Place capacitors first, keep SW geometry tight, partition grounds, stitch wisely, and pre-place tuning pads.
- Place VIN/BOOT/HS-clamp MLCCs first (≤2–3 mm pad-to-pin)
- Keep SW polygon small; no signal vias crossing the polygon
- Separate PGND/AGND; single tie near IC ground reference
- Stitch GND vias every 2–3 mm around the power island
- Route FB/sense on an inner layer with ground shielding
- Pre-place pads: RC snubber, boot-R, split gate-R
- Add a quiet-zone keep-out around ADC/refs/clk
Validation Playbook
Repeatable A/B protocol: near-field sweep → LISN pre-scan → timestamp-aligned captures with identical cabling.
- Near-field sweep map (E/H), pre/post overlays
- LISN scan: QP/AV/PK, L1 & L2, fixed cable photo
- A/B scope: dv/dt, overshoot, fring; snubber-R thermal
- Artifacts: CSV logs, screenshots, instrument settings, test ID & timestamp
- Naming:
<topic>-<before|after>-<load>-<date>-<run>.png(+ same for CSV)
Trade-offs & Escalation Path
Geometry → edge shaping → filtering/shielding. Document efficiency, temperature, and measurement side-effects.
- Shrink loops; fix SW polygon & grounds → re-measure
- Tune boot-R / split gate-R; add RC snubber → check ΔT / efficiency
- Add DM/CM filtering (VIN pins / cable entry) → LISN re-scan
- If cable/enclosure coupling remains → shield can / enclosure grounding
- Log trade-offs: loss, temperature, cost, space; attach artifacts
Mini IC-Selection Pointers (pads you’ll want)
Fast picks that simplify EMI/layout: controllable edges, blanking/OCP filters, spread-spectrum options, and EPAD packages for clean PGND rings. Note: the full matrix lives in the “IC Selection Guide” page.
- Gate-driver strength/slew tuning; sync & spread-spectrum options
- 2.2 MHz / 440 kHz choices for AM-band planning
- QFN/HTSSOP with EPAD → easy PGND ring + via-fence
- Wide-VIN boost; adjustable soft-start & slope-comp
- Good pre-boost/hold-up with EMI-friendly tuning space
- EPAD footprint enables short SW loop + PGND ring
- Sync buck with optional spread-spectrum (200 kHz–2.3 MHz)
- QFN16 EP → compact PGND ring; short BOOT/VIN loops
- Good for AM-band and cable-noise mitigation
- Up to 61 V async buck; soft-start pin for ramp control
- HTSSOP-EP package for solid ground stitching
- Robust choice for industrial front-ends
- Sync buck controller; programmable SS & PGOOD
- QFN/HTSSOP with EPAD → clean PGND ring layout
- Good controller when you need tuning headroom
- 40 V 4-switch buck-boost; peak/avg sensing both ends
- Helpful OCP filters & blanking; bidirectional option
- EPAD package supports tight SW copper & short returns
- Automotive pre-boost; slope-comp & low-IQ modes
- Strong for crank/stop-start EMI scenarios
- Layout room for snubber/boot-R easing AM band
- 2 MHz sync buck; AM-band friendly when routed tight
- Soft-start/PG; EPAD package helps PGND stitching
- Good for low-noise in compact auto rails
- 75 V/5 A sync buck; external soft-start; robust controller
- QFN EP variants → strong PGND ring & short loops
- Industrial rails where thermal/EMI both matter
- 30 V buck in tiny SOT-23; internal soft-start
- Good helper rail; short VIN/BOOT loops possible
- Simple pad set still benefits from snubber footprint
- Multi-buck PMIC with spread-spectrum & sync options
- Centralized rails → minimal hot-loop perimeter
- Watchdog/PGOOD for clean sequencing & logging
- Quad-buck + LDOs PMIC; tight integration shrinks hot loops
- Flexible sequencing and fault reporting
- EPAD package to anchor PGND stitching
- Hall current sensors with internal conductor (SOIC)
- DC–300 kHz bandwidth; dual over-current diagnostics
- Lets you avoid noisy shunt near SW polygon
- ~250 kHz bandwidth; AEC-Q100; programmable filters
- Clean analog output routing; good for AGND corridors
- Reduces dv/dt pickup relative to discrete shunts
Tip: reserve footprints early — RC snubber at SW, boot-R, split gate-R, Zobel on output, CM choke at cable entry — to keep EMI tuning on-board.
FAQs
How small must the input hot loop be to shift a CISPR fail to pass?
Aim for pad-to-pin MLCC distance ≤2–3 mm and total loop ESL ≤~1 nH. That typically yields a 3–8 dB reduction in near-field peaks which often translates to a margin win in conducted scans. Confirm with a probe map first, then re-run the LISN pre-scan using the exact same cabling and load conditions.
Snubber vs gate-R: which to try first and how to size each quickly?
Try gate-R (or split gate-R) first to reduce dv/dt at the source. If ringing persists, fit an RC snubber: estimate C ≈ 1.5–3× the parasitic C from ring decay, then start R ≈ √(L/C). Verify by temperature: the snubber resistor should warm but stay comfortably below its rated rise under worst load.
What |Z|@100 MHz is “good enough” for a ferrite bead at 2 A bias?
As a fast rule for DM hash, target ≥80–120 Ω at 100 MHz under 2 A DC bias with SRF above the noisy band. Always read derating curves—many beads lose 30–60% impedance at bias. Ensure IDC rating >= 1.5× rail RMS and confirm thermal rise at maximum duty.
Does spread-spectrum really fix cable-borne peaks on 30–300 MHz scans?
It lowers narrow spectral peaks by smearing energy, improving quasi-peak margins. It does not fix poor geometry or bad return paths. Use it after minimizing hot loops and routing the SW polygon correctly. Disable spread-spectrum during loop/Bode measurement to avoid false margins, then re-enable for compliance pre-scans.
Where should the star-point live if the controller has analog ground pins?
Create an AGND island for FB/COMP/REF and tie it to PGND at a single star-point located at the controller’s ground reference or sense-shunt return. Keep high current returns out of AGND. Flank FB lanes with a ground corridor and via stitching; do not cross the SW polygon with any AGND traces.
Can I route SW on an inner layer to “hide” it? Thermal risks?
Burying SW can reduce radiated coupling, but adds via inductance and complicates heat removal. If you must, contain it between continuous planes, minimize via count and length, and keep copper area small. Ensure adequate thermal vias near FETs/diodes and verify temperature with a heat camera under worst-case load.
How many stitching vias are meaningful before diminishing returns?
Around power islands, 2–3 mm pitch along edges is a strong baseline. Extra vias help until the local return impedance is dominated by plane spreading rather than via inductance. Add clusters near SW edges and between noisy/quiet partitions, then check near-field maps; stop when adding vias no longer reduces peaks.
RC filter on FB: values that won’t destabilize current-mode control?
Keep the FB RC’s pole well above the crossover of the inner current loop and below the switching residue you want to attenuate. Typical starts: R = 50–200 Ω, C = 100–680 pF at the pin. Place parts tight to the IC, reference to AGND, and re-check phase margin after fitting.
Boot-R harms start-up with pre-bias—how to tune around it?
A large boot-R slows turn-on dv/dt but can stall or back-discharge pre-biased outputs. Use split gate-R (larger turn-on, smaller turn-off), extend soft-start, and add blanking to ignore transient OCP/UVP. Verify pre-bias behavior with load connected and log dv/dt, overshoot, and PGOOD timing during ramp.
CM choke vs shield can: which first for a quick audit pass?
Start with a CM choke at the cable entry if the pre-scan suggests cable-borne common-mode peaks. It is cheaper, fast to retrofit, and keeps harness currents in check. Add a shield can when near-field maps show strong local fields after loop and edge control. Re-scan with identical cable routing.
Why does a long sense trace cause min/max latch “spam” at load steps?
Long sense runs pick up dv/dt and diode-recovery spikes, creating false excursions that trip min/max latches. Cure with Kelvin routing, an AGND corridor, and a small anti-alias RC at the pin. Avoid running sense under SW copper, and keep return paths adjacent and continuous back to the star-point.
How to photograph/record probe setups so future runs are comparable?
Capture a wide frame including the DUT, cable paths, LISN, and probe orientation. Place a ruler or grid for scale. Record scope settings (timebase, bandwidth limit, coupling, attenuation) and probe model in a text overlay or caption. Use consistent filenames with topic, before/after, load, date, and run index.
USB-PD rails: preventing cable-injected noise during PDO transitions.
Keep the PD controller and power-path FETs close, minimize sense/gate loops, and place a small HF MLCC array at the receptacle. Sequence the buck/boost to ride through PDO steps and log dv/dt at the SW node. If peaks persist, add a CM choke at the connector and a damped output bead.
Automotive CISPR 25 Class 5: what’s realistically achievable on 2-layer?
It is challenging but possible for modest power if you keep loops extremely compact, dedicate the back to a near-solid ground, and fence with dense stitching vias. Select controllers with soft drive and spread-spectrum, use a CM choke at the harness, and verify with near-field mapping before chamber time.
Bead-LC on output oscillates—how to damp without burning ripple spec?
Insert a small series resistor (0.1–0.5 Ω) with the bead or add a Zobel (e.g., 0.47–1 µF with 0.5–2 Ω) to ground tuned near the LC resonance. Re-measure load-step and ripple; target a flatter peak without exceeding ripple limits. Re-check loop stability after any damping change.
