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General-Purpose LDO (50–500 mA, OTP/OCP)

Introduction & Scope

General-purpose LDOs target 50–500 mA loads with solid line/load regulation, basic protections (OTP/OCP), and practical cost/availability. Typical inputs are 2.5–6 V (USB 5 V, single-cell Li-ion), with VOUT in the 1.2–5 V range. This page excludes ultralow-IQ, high-PSRR/low-noise, DDR VTT/Vref, automotive AEC-Q topics, and >1 A LDOs.

  • Quick selection loop: dropout & thermal check → stability window (COUT/ESR) → protections & reverse current.
  • Power loss: Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN; Tj = Ta + θJA·Ploss.
  • Stability cues: fp,out ≈ 1/(2π·Rout·COUT), fz,ESR ≈ 1/(2π·ESR·COUT).
General-Purpose LDO — Scope Solid regulation · 50–500 mA · OTP/OCP Current VIN/VOUT 50–500 mA (target band) VIN 2.5–6 V VOUT 1.2–5 V VOUT Ultralow-IQ (see dedicated page) High-PSRR/Low-Noise (audio/RF) DDR VTT / Vref (bidirectional) Automotive AEC-Q (separate) >1 A LDO (separate)
Scope map: focus on 50–500 mA, typical VIN/VOUT windows, and route excluded topics to sibling pages.

Topologies (PMOS / NMOS / BJT)

Three common pass-device choices balance dropout, Iq/noise, stability window (COUT/ESR), reverse current risk, and cost/availability. Use PMOS for simplicity, NMOS for lower dropout (with pump), and BJT for smooth small-signal behavior when VIN headroom is adequate.

PMOS Dropout ≈ Iload × RDS(on) Simple, no pump Check reverse current ESR window sensitivity Good for simplicity/low Iq Dropout rises with Iload Verify COUT/ESR bounds NMOS Pump/boosted gate Lower RDS(on) → lower dropout Watch pump ripple/noise Tighter stability margin Best thermal at same size Requires pump circuitry Check high-freq coupling BJT Dropout ≈ VCE(sat) Smooth small-signal behavior Base current overhead Cost-friendly, widely available Needs headroom for VCE(sat) Re-validate ESR zero position
PMOS vs NMOS vs BJT — minimal text, visual cues: dropout model, stability window sensitivity, noise/Iq, reverse current, and thermal trade-offs.
  • PMOS: simple, no pump; dropout ∝ RDS(on); verify reverse current & ESR window.
  • NMOS: lowest dropout (needs pump); watch pump ripple; tighter stability margin.
  • BJT: smooth behavior, low noise; needs VCE(sat) headroom; mind base-current overhead.

Key Parameters

Focused metrics for 50–500 mA general-purpose LDOs: Vdrop, Iq, PSRR @ 100 Hz / 100 kHz, output noise, line/load regulation, and OCP with foldback. Keep a consistent recording method (Vin/Vout/Iload/Temp/COUT/ESR).

Key Parameters — quick visual Few words · clear labels · 3:2 responsive SVG Vdrop PMOS/NMOS: Vdrop ≈ Iload·RDS(on) BJT: Vdrop ≈ VCE(sat) Iq Standby / enable states tens–hundreds of µA (typ.) Iq·VIN contributes to heat PSRR @ 100 Hz Low-frequency ripple 50–60 dB target PSRR @ 100 kHz Switching-coupled noise 20–30 dB target Noise µVrms over BW specify bandwidth (e.g., 1 Hz–100 kHz) few tens–hundreds µV Line / Load Reg ≤0.1–0.3%/V · ≤0.5–1% OCP with foldback record Ilimit & recovery mode
Six quick cues with minimal text: Vdrop, Iq, PSRR at two anchors (100 Hz / 100 kHz), output noise, line/load regulation, and OCP/foldback.
  • Record format: Vin/Vout/Iload/Temp/COUT/ESR + test bandwidth.
  • Compare apples-to-apples: same points for PSRR, noise, line/load reg.
  • Thermal math: Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN; Tj = Ta + θJA·Ploss.

Design Rules (General Use)

A practical loop: dropout & thermal → stability window → reverse events → start-up dynamics → EMI/layout. Each rule states the decision, the first actions, and the verification.

Design Rules — decision → action → verify A) Dropout & Thermal Decide: Tj near limit? Action: lower Vdrop / NMOS / 2-stage Verify: steady temp, no OTP B) Stability Window Decide: ESR & COUT fit? Action: MLCC + ESR aid Verify: no oscillation C) Reverse Events Decide: back-power risk? Action: RCP diode / blocker Verify: zero reverse flow D) Start-up Dynamics Decide: ramp vs load? Action: SS slope / damping Verify: dip/overshoot OK E) EMI / Layout Decide: coupling present? Action: partition, near decoupling Verify: PSRR at fSW
Five-rule flow with minimal words: decide → first actions → verify, covering thermal, stability window, reverse events, start-up, and EMI/layout.
  • Thermal math: Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN; Tj = Ta + θJA·Ploss.
  • Stability window: follow COUT/ESR limits; keep loop small; re-validate at light/heavy load.
  • Reverse events: prefer built-in blocker; else add diode/block; delay PG/RESET.
  • Start-up: match SS slope to load; add small damping at load if needed.
  • EMI/layout: partition from switchers; near input decoupling; verify at 100 kHz neighborhood.

Design Rules (General Use)

Four practical blocks for 50–500 mA general-purpose LDOs: Vdrop & thermal budget, VIN tolerance & inrush, COUT/ESR stability window, and reverse-current protection. Each card shows decide → first action → verify.

Design rules — decide · act · verify A) Vdrop & Thermal Decide: Tj near limit? Action: lower Vdrop / NMOS / 2-stage Verify: steady temp, no OTP Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN B) VIN Tolerance & Inrush Decide: adapter/battery drift Action: near CIN; SS or limiter Verify: plug-in overshoot, VOUT dip USB ±5–10%; Li-ion 2.7–4.35 V C) COUT / ESR Window fz,ESR = 1/(2π·ESR·C) fp,out = 1/(2π·Rout·C) Decide: in-window at corners? Action: MLCC + ESR aid / RC Verify: no oscillation at light/heavy D) Reverse Current & Protection Decide: back-power risk? Action: blocker diode/device Verify: zero reverse flow; PG stable
Four minimal cards show what to check and how to verify: Vdrop & thermal, VIN tolerance & inrush, COUT/ESR window, and reverse-current protection.
  • Thermal math: Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN; Tj = Ta + θJA·Ploss.
  • VIN: place CIN near; limit inrush (soft-start or series limiter); test plug-in overshoot.
  • Stability: follow COUT/ESR window; consider MLCC + ESR aid or RC if allowed; validate at light/heavy loads.
  • Reverse: prefer built-in blocker; else add diode/device; add delay/hysteresis for PG/RESET.

Stability & Compensation in Practice

Practical checks for ESR window, bidirectional load steps, and parasitics (ESL, trace inductance). Keep loops small, validate at corners, and log dip/overshoot and tsettle.

ESR window & load-step response ESR zero & output pole fz,ESR fp,out Increase ESR → fz,ESR ↓ Increase C → fp,out ↓ Bidirectional load step dip/overshoot t_settle (2% band)
Left: how ESR and C shift the ESR zero and output pole. Right: load-step response with dip/overshoot and settle time markers.
  • ESR window: confirm both corners (COUT ± tolerance, ESR ± tolerance). Consider RC or Cff if allowed.
  • Load steps: test 10→90% and 90→10% at three temps; record ΔV(%), tsettle(µs), ring frequency.
  • Parasitics: keep loops small; place CIN/COUT near; isolate FB/REF; add small damping at load if needed.

Validation Playbook

Minimal, repeatable plan for 50–500 mA general-purpose LDOs. Cover bidirectional load steps, cold/hot starts, VIN sweep, boundary load near Ilimit, and short-circuit foldback. Use a consistent log format.

Validation swimlane — quick path Load steps (10→90% and 90→10%); log ΔV(%), tsettle(2%), ring(kHz), 3 temps Cold/Hot start; soft-start slope, pre-bias tolerance, PG/RESET timing VIN sweep; find dropout; PSRR at 100 Hz / 100 kHz across VIN Boundary load near Ilimit; check OTP onset & recovery behavior Short-circuit foldback I–V; recovery mode (auto/latched) Record context each run: VIN, VOUT, Iload, Temp, COUT/ESR, layout note Targets: ΔV ≤ 3–5% · tsettle ≤ 100–200 μs · PSRR ≥ 50/20 dB (100 Hz / 100 kHz) Record 1 — ΔV and tsettle dip/overshoot tsettle within ±2% Record 2 — PSRR anchors 100 Hz ≥ 50–60 dB 100 kHz ≥ 20–30 dB Record 3 — Short-circuit foldback (I–V) V I Foldback shape & recovery
Swimlane shows test order; cards highlight what to log: ΔV/tsettle, PSRR at 100 Hz/100 kHz, and I–V foldback.
  • Matrix: VIN(min/nom/max) × Iload(0–100%) × Temp(−20/25/85 °C) × COUT/ESR(corners).
  • Record: VIN | VOUT | Iload(up/down) | Ta | COUT/ESR | ΔV(%) | tsettle(µs) | ring(kHz) | PSRR(100 Hz/100 kHz) | Ilimit/Foldback | OTP/PG.
  • Targets: ΔV ≤ 3–5% · tsettle ≤ 100–200 µs · PSRR ≥ 50 / 20–30 dB · stable recovery.

Common Pitfalls & Fixes

Five engineer-facing cards: oscillation at start, noise coupling / PSRR drop, thermal stacking, reverse discharge, and PG/RESET false triggers. Each shows cause → quick fix → verify.

Common pitfalls — cause · fix · verify Start-up oscillation Cause: COUT/ESR out of window Fix: MLCC + ESR aid / RC Verify: bidirectional load steps Noise coupling / PSRR Cause: switcher node coupling / ground bounce Fix: partition; near decoupling; π if needed Verify: sweep around fSW; A/B layout 100 Hz 100 kHz Thermal stacking Cause: (VIN−VOUT)·Iload + Iq·VIN too high Fix: lower Vdrop/NMOS; DCDC→LDO Verify: steady temp; no OTP chatter Reverse discharge Cause: no back-power blocking path Fix: device with blocker; else diode Verify: reverse current = 0; PG stable PG/RESET false triggers Cause: narrow window; noise + dips Fix: delay/hysteresis/filter Verify: 0 false events on cycles
Five common issues distilled into cause → fix → verify cards: start-up oscillation, coupling/PSRR, thermal, reverse discharge, and PG/RESET false triggers.
  • Oscillation: return to COUT/ESR window; consider RC/Cff if allowed; confirm at light/heavy loads and three temps.
  • Coupling: partition from switchers; near decoupling; verify PSRR around fSW with A/B layout.
  • Thermal: lower Vdrop/NMOS or two-stage; confirm no OTP chatter at worst corners.
  • Reverse: prefer built-in blocker; else add diode/device; add PG/RESET delay/hysteresis.
  • PG/RESET: tune thresholds & delay; aim for zero false events across plug-in and load steps.

Mini IC-Selection Pointers

Small, scenario-based hints for 50–500 mA general-purpose LDOs. Each card: when to use, quick thresholds, one common pitfall, and real part numbers.

General-Purpose LDO — mini scenarios Few words · clear thresholds · remember Vdrop / Iq / PSRR / thermal / PG MCU Core / IO 100–300 mA · Vdrop ≤ 200–300 mV Watch line/load regulation Analog Front-End ≤200 mA · low noise PSRR@100 Hz ≥ 60 dB Post-DCDC Clean-Up 200–500 mA · low Vdrop Validate COUT/ESR window Peripherals / IO Banks 100–300 mA · fast settle PG/RESET robustness Always-On / Standby ≤150–250 mA · low Iq EN/leakage check 5 V → 3.3 V Legacy 200–500 mA · thermal Cable drop + Vdrop Battery-Powered ±VIN drift · inrush place CIN near Sensor Rail 2.8 V ≤200 mA · noise PSRR at fSW Quick PG / RESET stable thresholds delay · hysteresis
Nine quick scenario tiles: use them to anchor thresholds and pick a few proven part numbers per brand.

MCU Core / IO (3.3 V / 1.8 V)

When: 100–300 mA, decent line/load reg.
Quick gates: Vdrop ≤ 200–300 mV@full; Iq 50–200 µA.
Pitfall: cable drop + low VIN margin.

  • TI: TLV700xx, TLV757P, TPS736xx
  • ST: LDS3985, LD39050, LDL1117
  • Renesas: ISL9001A, ISL80101A
  • onsemi: NCP718, NCP4681
  • Microchip: MCP1700 / 1703, MIC5504
  • NXP: Use platform PMIC rails (e.g., PCA9450A)
  • Melexis: Pair with external LDO above

Analog Front-End / Sensor Rail

When: ≤200 mA, low noise & ripple.
Quick gates: Noise ≤ tens–hundreds µVrms; PSRR@100 Hz ≥ 60 dB; @100 kHz ≥ 20–30 dB.
Pitfall: coupling from switcher.

  • TI: TPS799xx, TPS7A20
  • ST: LDLN025, LD39150
  • Renesas: ISL9001A
  • onsemi: NCP167
  • Microchip: MIC5219, MIC5225
  • NXP: PMIC LDO rails (e.g., PF1550)
  • Melexis: external LDO recommended

Post-DCDC Clean-Up

When: 200–500 mA after a buck.
Quick gates: favor low Vdrop; validate COUT/ESR window.
Pitfall: light-load ringing.

  • TI: TLV757P, TPS7A02
  • ST: LD39050, LDL1117
  • Renesas: ISL80101A
  • onsemi: NCP718
  • Microchip: MCP1825S, MIC5504
  • NXP: use PMIC rail (PCA9450A)
  • Melexis: external LDO per load

Peripherals / IO Banks

When: USB / Wi-Fi / BT / storage 100–300 mA.
Quick gates: settle ≤ 100–200 µs; PG/RESET clean.
Pitfall: PG false events at plug-in.

  • TI: TPS736xx, TLV700xx
  • ST: LDS3985, LD39050
  • Renesas: ISL9021A, ISL9001A
  • onsemi: NCP4681, NCP718
  • Microchip: MIC5504, MCP1703
  • NXP: PMIC rail as needed
  • Melexis: external LDO pairing

Always-On / Standby

When: ≤150–250 mA with strict battery life.
Quick gates: Iq ≲ 1–50 µA; check EN/leakage.
Pitfall: divider leakage after EN low.

  • TI: TPS7A02, TLV700
  • ST: LD39015, LDLN025
  • Renesas: ISL9001A
  • onsemi: NCP167
  • Microchip: MCP1700 / 1702
  • NXP: use PMIC low-Iq rail
  • Melexis: choose external low-Iq LDO

5 V → 3.3 V Legacy

When: adapters/USB sources, 200–500 mA.
Quick gates: account VIN tolerance + cable drop; θJA &thermal.
Pitfall: drop-out at peak current.

  • TI: TLV757P, TPS736xx
  • ST: LDL1117, LD39050
  • Renesas: ISL80101A
  • onsemi: NCP1117, NCP718
  • Microchip: MCP1825S, MIC5504
  • NXP: PMIC rail (PCA9450A)
  • Melexis: external LDO per load

Keep apples-to-apples when comparing: record VIN/VOUT/Iload/Temp/COUT/ESR and bandwidth for PSRR/noise; re-check PG/RESET behavior.

Frequently Asked Questions

PAA-style answers (45–60 words) plus a short social hook. Where useful, see related sections on this page.

What is a safe dropout margin for general-purpose LDOs?

For 50–500 mA LDOs, reserve at least 1.25× the specified dropout at your worst corner (highest load, temperature, and lowest VIN). This preserves regulation during transients and cable losses. If thermal headroom is tight, consider a lower-dropout family, NMOS-pass options, or a buck→LDO two-stage approach. See Design Rules.

Social hook: Keep 25% headroom over stated dropout to survive real-world corners.

How do I size COUT/ESR to stay inside the stability window?

Start with the datasheet’s COUT and ESR window, then verify both extreme corners (capacitance and ESR tolerance, temperature, and aging). If MLCC ESR is too low, add a small series R or a parallel electrolytic per vendor guidance. Validate with bidirectional load steps and ensure no oscillation. See Stability & Compensation.

Social hook: Design to the corners, not the typ point.

Why does PSRR degrade around the switcher’s switching frequency?

PSRR often dips near the upstream converter’s fSW and its harmonics because LDO loop gain and output pole/zero placement provide less attenuation there. Layout coupling makes it worse. Partition physically, keep loops small, and validate PSRR at fSW±. Consider a small RC filter if allowed. See Stability.

Social hook: Test PSRR where the switcher lives, not just at 100 Hz.

How can I validate load-step performance quickly?

Use 10→90% and 90→10% steps at three temperatures. Log dip/overshoot (percent), settle time to ±2%, and ring frequency. Repeat at COUT/ESR window corners. Targets for general LDOs: ≤3–5% deviation, 100–200 µs settle. Align measurements to PG/RESET timing if used. See Validation Playbook.

Social hook: Two steps, three temps, window corners—done.

What VIN sweep is enough to locate dropout and guard bands?

Sweep from slightly below VIN(min) to slightly above VIN(max) at full load while logging VOUT and PG. Identify dropout onset and add 10–20% VIN margin for cables and transients. Repeat at hot. If headroom is thin or power loss is high, move to a lower-dropout or two-stage solution. See Validation.

Social hook: Find dropout hot and loaded—then add margin.

When do I need reverse-current blocking on an LDO rail?

Add reverse blocking when downstream rails can be back-powered (multiple sources, hot-plug, or batteries). Prefer devices with built-in reverse protection; otherwise, use a diode or dedicated blocker and consider a discharge path for safe power-down. Verify zero reverse current and stable PG during unplug. See Design Rules.

Social hook: If outputs can power inputs, block it.

How do I avoid PG/RESET false triggers at plug-in?

Use proper delay or hysteresis per datasheet, filter fast spikes, and ensure your PG threshold aligns to actual regulation limits. Validate across cable-in and load-step events. Keep sense nodes quiet in layout, and avoid coupling from switcher nodes. Count false events; the target is zero. See Pitfalls & Fixes.

Social hook: Delay, hysteresis, and quiet routing beat PG chatter.

Can I place an LDO after a buck to “clean up” noise?

Yes—post-regulation reduces ripple and harmonics, but mind efficiency and thermal loss: (VIN−VOUT)·Iload. Choose a low-dropout family and validate PSRR near the buck’s fSW. Keep loops small, decouple locally, and confirm stability across the COUT/ESR window. See Mini IC-Selection Pointers.

Social hook: Buck→LDO works—watch heat and fSW.

How can I estimate thermal headroom without a chamber?

Use Ploss ≈ (VIN−VOUT)·Iload + Iq·VIN and Tj ≈ Ta + θJA·Ploss. Measure steady-state case temperature and apply a conservative junction-to-case estimate. If Tj approaches 80–85% of rating, redesign for lower Vdrop, better layout copper, or two-stage regulation. See Design Rules.

Social hook: Quick math + case temp = safe headroom.

What compensation tricks are typically allowed by datasheets?

Many LDOs permit a small feed-forward capacitor (Cff) or RC to place a zero and improve phase margin. Only apply values within vendor guidance and re-validate across load and temperature. If compensation is fixed, tune COUT/ESR and layout first. See Stability & Compensation.

Social hook: If RC/Cff is allowed, verify at corners.

Light-load ringing: fix with more C or with ESR?

First confirm you are within the COUT/ESR window. If MLCC ESR is too low, add a small series resistor or mixed capacitor type to introduce a stabilizing zero. Increasing capacitance alone can move poles but may not add damping. Re-test with 10↔90% steps. See Stability.

Social hook: Damping needs ESR—not just more C.

Do I need soft-start or is input decoupling enough?

Strong local decoupling at VIN handles most plug-in events. If inrush or PG timing is critical, use devices with controlled soft-start or enable ramp. Validate VOUT dip and PG behavior during hot-plug and load steps, and ensure upstream sources tolerate the transient. See Design Rules.

Social hook: Decouple first; add soft-start when timing matters.

Short-circuit foldback: what curve shape is acceptable?

An L-shaped or curved foldback that reduces current as VOUT collapses is typical; it limits power and helps thermal recovery. Verify repeatable behavior, absence of chatter near Ilimit, and correct auto/latched recovery per datasheet. Log I–V points from normal load down to near 0 Ω. See Validation.

Social hook: Foldback should cool, not chatter.

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