LDO with Bypass / Standby Pass
LDO with Bypass / Standby Pass
Center idea: two paths, one goal—standby pass for ultra-low loss when idle, and a regulated LDO path for high-PSRR, low-noise peaks. A brownout hook decides when to switch, with hysteresis to prevent chattering.
Scope & Boundaries
- In-scope: LDOs featuring bypass/standby-pass, fast switchover control, brownout hooks, reverse-current safety, layout/validation notes.
- Not covered in depth: full eFuse/ideal-diode controllers, generic load switches, DDR VTT/Vref special, ultra-low-Iq LDO grand tour, wideband high-PSRR deep dive (see sibling pages).
Architectures
Two parallel paths merge at a controlled node: standby pass (low loss) and regulated LDO (high PSRR). Directionality and anti-backfeed are mandatory when rails collapse or during rapid mode toggling.
A) LDO in series + parallel bypass (split paths)
Standby sends current through the bypass FET (low RDS(on)), while peak/noise-critical windows switch to the LDO path for high PSRR. Guard against backfeed during collapse and ensure debounced thresholds to avoid chattering. Size output capacitors and add clamps if needed to tame switchover spikes.
B) LDO pre/post vs ideal-diode controllers (boundary only)
Placing the LDO before OR-ing prioritizes directionality; placing it after OR-ing maximizes PSRR at the load but impacts dropout and thermals. Full ideal-diode/eFuse strategy is covered in the sibling page; here we only mark the interface boundary.
C) Reverse-current safety & OR-ing relationship
Regardless of the path, reverse-current blocking is mandatory. For multiple sources or paralleled rails, define priority + hysteresis. Validate with forced VOUT > VIN tests to measure Irev.
| Dimension | Standby pass (bypass) | Regulated LDO | Notes |
|---|---|---|---|
| Loss / Thermals | Low; P≈I²·RDS(on) | Dropout × I | Derate with temp; check RθJA |
| Noise / PSRR | Weak PSRR | High PSRR / low noise | Choose by load sensitivity |
| Control / Timing | Simple path | Switchover tsw, PG/RESET | Add hysteresis; debounce |
| Reverse current | Guard needed | Guard needed | Test VOUT>VIN; measure Irev |
Modes & Fast Toggling
Standby (pass-through, low loss) ↔ Peak (LDO regulate, high PSRR) switching with dual thresholds + hysteresis, debounce, and minimum dwell to avoid chattering and PG glitches.
- Enter Peak below V_BO_LOW; return Standby above V_BO_HIGH (ΔHyst ≥ ripple × 1.5–3).
- Add debounce and minimum dwell on both directions to suppress chattering.
- Size output caps/clamps to keep ΔV and PG within limits during switchover.
Brownout Protection
Set V_BO_LOW / V_BO_HIGH, apply hysteresis, and coordinate with PG/RESET. Consider simple RC filtering or digital averaging to avoid single-cycle false trips.
| Parameter | Typical | Note |
|---|---|---|
| ΔHyst (voltage) | ≥ ripple × 1.5–3 | Avoid chattering near VIN≈Vout+margin |
| t_assert / t_release | 1–10 ms (start point) | Tune vs. load step & ripple |
| PG mask | cover t_sw window | Prevent false PG dips |
| RESET release lag | > t_sw + t_hold | Release after stable settle |
Design Rules (calculation & selection)
Balance pass-through loss vs. regulated loss, budget Iq/Istandby, control tsw & spikes, guarantee reverse-current safety, and trade PSRR/noise vs. transients.
| Dimension | Rule of thumb | Notes |
|---|---|---|
| Pass loss | P_pass ≈ I_out²·R_DS(on) | Account R_DS(on)(T) and ΔV_pass |
| LDO loss | (V_in−V_out)·I_out + Iq·V_in | Check dropout margin vs PSRR |
| Iq / standby | Minimize Iq_standby; average by D_peak | P_avg ≈ D·P_LDO + (1−D)·P_pass |
| Reverse-current | Block required | Test VOUT>VIN, measure I_rev |
Sequencing & System Hooks
Align power-up/down order with downstream LDO/VRM/MCU. Mask PG during switchover, release RESET after a stable hold, and log key status for diagnostics.
- Power-up: start in Standby → mask PG during switchover → release RESET after t_sw + t_hold.
- Power-down: Peak → Standby → safe shutdown; prevent backfeed on collapsing rails.
- Hooks: expose state bits, log chatter/PG glitches/t_sw; align enable levels with MCU/VRM domains.
Layout Checklist
Minimize the bypass FET loop, tie AGND–PGND at a single point, use Kelvin sense from the load-side VOUT, and place PG/brownout dividers close to the comparator pin.
- Bypass loop: shortest VIN→FET→merge→VOUT; wide copper + via array.
- AGND/PGND: single-point tie near the LDO reference; guard cut between zones.
- Kelvin sense: VOUT_S+/GND_S− as a tight pair from the load-side.
- Dividers: at pin + small RC; keep-out near hot parts; add bleed and test pads.
- Reverse-current guard near merge node; clamp with shortest return.
Validation Playbook
Sweep a condition matrix, measure tsw and ΔV, count chatter, confirm reverse-current safety, and export logs for A/B comparison.
| Axis | Levels | Notes |
|---|---|---|
| I_OUT | I_min · I_typ · I_max · I_step | Cover worst-case transients at I_step |
| Temperature | −40 · 25 · 85 °C (up to 105/125 °C) | Validate thresholds drift vs. T |
| VIN | High · Mid · Low · Brownout ramp | Down–hold–up profile |
| KPIs | t_sw, ΔV, chatter/1000, PG glitches, I_rev | Export CSV + timestamps for A/B |
Mini IC-Selection Pointers (Seven Brands, real P/Ns)
Pattern: use a low-loss bypass/ORing path (ideal-diode/eFuse/load-switch) for Standby, and a high-PSRR LDO for Peak. Reverse-current protection is required at the merge node. PG/RESET timing must mask the switchover window.
| Brand | Bypass / ORing device | Regulated LDO (Peak path) | Why this pair | Notes |
|---|---|---|---|---|
| Texas Instruments |
LM74700-Q1 / LM74703-Q1 (ideal-diode controller) LM74800-Q1 (ideal-diode + reverse battery) |
TPS7A94 (ultra-low-noise, high-PSRR) TPS7A85A (high-current, low-noise) |
Robust reverse blocking and fast turn-on in Standby; excellent PSRR in Peak. | Automotive options (-Q1). Coordinate PG mask with tsw. |
| STMicroelectronics |
STEF12 (eFuse, 12 V class, reverse-current limiting) STEF01 (programmable eFuse) |
LD39200 (2 A, high-PSRR) LDLN015 (ultra-low-noise, 150 mA) |
eFuse provides low-loss pass with protections; LDO covers noise-sensitive windows. | Keep dividers at the pin; validate reverse blocking in drop-out. |
| NXP |
NX20P3483 (ideal-diode USB-PD power switch) PF5020 (PMIC: LDO channel configurable as load-switch) |
PCA9420 (PMIC with LDOs for low-noise rails) | Use integrated load-switch for Standby; dedicate LDO for Peak sampling windows. | Confirm inrush profile and PG latency vs. MCU reset tree. |
| Renesas |
ISL6146 (ORing / ideal-diode FET controller) RAA489000 (ideal-diode controller, wide input) |
ISL80505 (low-noise LDO) ISL80101A (1 A low-noise LDO) |
Efficient Standby path with back-to-back FETs; quiet LDO for analog/RF loads. | Log reverse-current test (VOUT>VIN) and thermal drift. |
| onsemi |
NIS5021 / NIS6350 (eFuse with reverse blocking) NCP45520 (load switch with reverse blocking) |
NCV8161 (auto LDO, high PSRR) NCP717 (low-Iq LDO) |
Low-loss pass and fault protection; stable LDO supply during Peak. | Automotive grades available; check Grade and PPAP. |
| Microchip |
MIC94161 (reverse-blocking load switch) MIC2545 (high-side power switch) |
MIC5504 (ultra-low-noise LDO) MCP1799 (150 mA, wide VIN) |
Clean Standby pass plus quiet Peak rail; simple BOM and small packages. | Verify dropout vs. PSRR at 10 k/100 k/1 MHz points. |
| Melexis |
MLX80030/31/50 (LIN SBC with LDO + reset) MLX81340/44 (LIN pre-driver module power) |
On-chip LDO (SBC), for local logic/IO rails | Use SBC LDO for local regulation; add TI/Renesas/onsemi ideal-diode on the main Standby pass. | System-level integration; confirm wake/sleep currents and reset timing. |
Submit your BOM (48h turnaround)
Cross-brand alternates, small-lot friendly fulfillment.
- Pin-to-Pin or same-footprint alternates across TI / ST / NXP / Renesas / onsemi / Microchip / Melexis
- Small-lot ready: cut-tape / partial reel / mix-brand shipping
- Automotive docs: AEC-Q100 / PPAP on request
- Anti-counterfeit & traceable sourcing
- 48-hour selection feedback + ETA window
Your file will be kept confidential and used for BOM selection & fulfillment evaluation only. NDA available upon request.
Back to the LDO hub for architectures, sizing rules, and brand matrices.
Back to LDO Main PageFAQs (Engineer Tone)
How do I measure and accept switchover time tsw?
Trigger on the control event and measure until VOUT re-enters the ±band around its target and stays there for the hold window. Cross-probe VIN, VOUT, and PG. Accept if PG is masked over t_sw, RESET is released after t_sw + t_hold, and no brownout flag is latched.
What hysteresis prevents chatter around brownout?
Set total hysteresis to roughly 2–3× the worst-case ripple plus the measured transient sag at the hand-off. Implement with a feedback resistor and de-bounce time. Validate by sweeping VIN slowly and stepping load; require zero PG oscillation and no more than one retry within 10 ms near the threshold.
Does bypass mode hurt PSRR and noise?
Yes. In bypass, the load sees source ripple minus only the FET path impedance, so PSRR is weak above a few kHz. Keep RF/ADC windows in Peak (regulated) mode or add a post-filter. Confirm noise with a defined bandwidth and list PSRR at 10 kHz, 100 kHz, and 1 MHz.
How fast should the hand-off be to avoid MCU brownouts?
Target 10–100 µs end-to-end under worst-case load and temperature. Synchronize the ideal-diode gate ramp with the LDO soft-start so current doesn’t dip. Add local bulk at the load. Require no RESET assertion and no clock stretch events during the transition window.
How do I budget Iq for Standby vs Peak?
Compute P_avg = D_peak·P_LDO + (1–D_peak)·P_pass. In Standby, include controller quiescent current, sense leakage, and downstream idle load. In Peak, add the LDO’s Iq and gate-drive losses. Verify over temperature and production corners; track with a daily duty cycle log if the rail is dynamic.
Where should RC slew and clamps go to tame spikes?
Place the RC slew network and the clamp next to the merge node with the shortest ground return. A small series resistor can damp ringing with the local MLCC. Verify ΔV and di/dt using a short ground-spring probe; accept only if the worst-case sag never trips PG/RESET thresholds.
How do I verify reverse-current safety?
Force VOUT > VIN and measure reverse current vs. temperature. Confirm the controller drives back-to-back FETs off quickly. During power-down, pre-bias the output with a capacitor and watch the clamp path. Pass only if I_rev < data-sheet limit and device temperature stays within SOA.
What PG/RESET timing avoids false trips?
Mask PG for the entire switchover window, then release RESET after t_sw + t_hold. Add explicit de-bounce and a minimum dwell time in both Standby and Peak. On multi-rail systems, apply enable delays so downstream VRMs see a stable upstream supply before ramping.
How should AGND–PGND and Kelvin sense be routed?
Keep a single-point AGND–PGND tie near the LDO reference. Run a tight Kelvin pair from the load-side VOUT back to the comparator/dividers. Do not share these with high-current returns. Place test pads on VIN, merge node, VOUT, PG, RESET, and the control input.
Which KPIs should I log for A/B comparisons?
Record t_sw, ΔV (sag/overshoot), chatter per 1000 cycles, PG glitch count, and reverse current. Export CSV with timestamps, VIN, VOUT, I_out, PG, RESET, mode, and temperature. Compare distributions, not just means, and inspect worst-case corners for each configuration.
What changes under automotive crank and load-dump?
Thresholds must be validated across cold-crank dips and load-dump surges. Ensure the ideal-diode stays in control, the LDO survives dropout without latch-up, and PG remains masked through the event. Require AEC-Q100 grade where applicable and perform hot/cold testing at the extremes.
How does package and RθJA impact pass-mode losses?
Pass loss scales with I_out²·R_DS(on) and with the copper path resistance. Choose packages with good thermal pads and plan via arrays to spread heat. Use the vendor’s θJA and your board stack-up to predict steady-state temperature, then verify with an IR camera and on-board thermistors.
What should I double-check when doing pin-compatible swaps?
Confirm gate-drive polarity, sense architecture (single vs back-to-back FETs), PG polarity and thresholds, and any built-in clamp or timing features. Even if footprints match, timing or logic differences can cause chatter, false PG, or reverse-current spikes during hand-off.
