Charge-Pump Fast-Charge (2:1 / 4:1)

Topic & Intent: Why 2:1 / 4:1 Charge-Pump

A charge-pump fast-charger is a fixed-ratio DC step-down stage (typically 2:1 or 4:1) that takes a high-voltage input and feeds the battery directly, then runs a normal charging state machine. It exists for one reason: fast charge without hot boards.

In many BMS-oriented products the upstream source is already high (12–20 V from adapter or USB-C/PD). A large-current buck here will heat up and need big magnetics. A charge-pump, by contrast, divides the voltage first, spreads the losses, and keeps the board cooler.

Target queries to capture: charge-pump fast charge, low heat charging, direct-to-battery, USB-C/PD ready charger, 4:1 charger IC.

Operating Scenarios & Boundaries

Charge-pump fast-charge is best used when the source is already negotiated DC (USB-C/PD or a fixed adapter) and the target is a single cell or a pack-front battery node that must run cooler than a large buck stage would allow.

Typical deployments:

• USB-C / PD source fixed at 15 V or 20 V → direct-to-battery via CP.
• 12–18 V adapter in a cramped board where big inductors don’t fit.
• Handheld / tablet / medical portable / in-vehicle accessory that needs low-heat fast charge.

Rule of thumb: if VIN is just moderately higher than the battery (e.g. 12 V → 6 V), use 2:1 for better efficiency. If VIN is much higher (e.g. 20 V → 5 V), use 4:1 to cut thermal stress.

Architecture / Topology (Core of 2:1 / 4:1 CP)

A charge-pump fast-charger is not “a buck without an inductor”. It is a switching matrix that moves charge between nodes with the help of flying capacitors, under a ratio-aware CP controller. The whole point is to take a high-voltage DC source and present the battery with a lower, cooler, direct-to-battery charging node.

We go vertical here: first the blocks, then the 2:1 vs 4:1 difference, then flying-cap discipline, then why this is cooler than buck.

Core block sequence

A practical CP fast-charge path for single-pack charging can be read from left to right:

1. HV IN front-end — fixed / negotiated DC source (12–20 V) with OVP/UVLO.
2. CP switch matrix — MOSFET array that alternately connects the flying caps to the input and to the output according to the selected ratio.
3. Flying capacitors (C_fly) — energy shuttle; their value, voltage rating and ESR decide whether the CP is stable.
4. Battery / VBAT node — direct-to-battery point, usually protected by battery OVP, NTC/JEITA gating and a state machine.

Most CP faults (cap-not-present, cap-undervoltage, CP-not-ready) can be traced back to one of these four blocks.

2:1 vs 4:1 — what really changes

In a 2:1 CP stage, the flying capacitor is charged from the HV input in one phase and then stacked/connected to the output in another phase. Control is simpler.

In a 4:1 CP stage, the controller must run more complex switch combinations to present a much lower effective output. That means:

• More switching events per cycle.
• Stricter requirements on flying-cap value and placement.
• Higher chance to raise a CP fault if the layout is long or the caps are down-binned.

So the difference is not “change one resistor and it becomes 4:1”. It is a different internal switching sequence.

Why flying capacitors trip the charger most often

For CP fast-charge devices, flying-cap quality = system reliability. Keep these three rules:

• Voltage rating: must meet or exceed the CP ratio requirement.
• ESR: cannot be casually downgraded by purchasing; high ESR looks like a fault.
• Placement: caps must sit tight to the CP pins; long traces add parasitic R/L and trigger CP errors.

Compared to a high-current buck, a CP charger can be smaller (no big inductor), cooler (voltage divided first), and quieter (less magnetic coupling). That is the architectural reason to pick this topology.

Charge State Machine for CP Fast-Charge

Even though the power stage is a charge-pump, the charging logic is still a state machine. CP does not mean “always on”; it means “fast when conditions are met”. Because the battery is charged directly, every stage must check temperature and pack condition before engaging the CP at full ratio.

Four basic stages

A CP fast-charger for single-pack use normally walks through:

1. Pre-charge — pack is low / cold / unknown, so current is limited.
2. Fast-charge (CP active) — 2:1 or 4:1 stage enabled, main current delivered, thermal headroom monitored.
3. CV / Taper — current decays because the battery is nearly full.
4. Re-charge — pack fell below a re-entry threshold.

CP is only fully useful in the fast-charge stage. If JEITA/NTC says “no”, the device will stay in pre-charge and users will think “CP not working”.

How CP fast-charge differs from a normal switching charger

A normal switching charger may try to run even under marginal conditions. A CP fast-charger is stricter:

• Battery state sensitivity: if VBAT is too low or the NTC is out of window, the CP stage may not engage.
• Input / cap sensitivity: if a flying cap is wrong or the input current limit is hit immediately, the controller can exit fast-charge and raise a fault.

JEITA / NTC gating point

Safe strategy for battery-direct charging:

• Check NTC / JEITA before entering full-rate fast-charge.
• If temperature is cold/hot, stay in pre-charge or limit current.
• Log this condition so the host knows why the CP didn’t go fast.

Battery-Direct Safety Strategies

This sub-page exists because a charge-pump fast-charger feeds the battery directly. That means any mistake in input voltage, flying-cap health, or temperature window must be able to stop, limit, or report immediately. We build safety in three vertical layers: what is inside the CP IC, what the engineer must add, and what is reported to the host.

Why battery-direct is stricter

A buck charger has an inductor and an intermediate regulated node that can absorb short disturbances. A 2:1 / 4:1 CP stage does not: it divides a high DC level and presents it straight to VBAT. If the adapter overshoots, if the flying cap is missing, or if the NTC is out of range, the CP must not keep charging the cell.

Safety functions that must be built into the IC

These should come from the CP device itself, not as an afterthought:

• Input OVP / UVLO: blocks CP start if the source is above the programmed range, or shuts it down when the adapter collapses.
• Battery OVP: because the battery is direct-fed, the CP must stop or clamp when VBAT crosses the limit.
• OCP / short-to-battery detection: high current or a pack that looks like a short must trigger current limit or CP disable.
• NTC window + JEITA derating: temperature out of window → no fast-charge, or only reduced current.
• Timer-based safety: prevents staying in pre-charge / fast-charge forever when the pack cannot progress.
• Fault latch / auto-retry: hard faults can latch; softer layout/flying-cap faults can retry after a cool-off.

What the engineer still needs to add

Not every protection can or should be inside the CP IC. For field and automotive builds, add:

• External eFuse / second-level FET: stops abnormal or malicious adapters that overshoot above the negotiated level.
• PACK-level MOSFETs: to align with the rest of the battery-protection tree.
• Additional thermal / NTC sensor: when the internal JEITA is not enough or must be made more conservative.

This is how we keep it non-overlapping with the Protection page: we stay on “single-pack, battery-direct, CP-specific reactions”.

Fault Reporting & Telemetry (I²C / SMBus Style)

Serious charge-pump fast-charge parts don’t just stop when something goes wrong — they tell the host what went wrong. This is how you prove it is a real CP solution and not just a repurposed charger with a hardwired ratio.

Minimal telemetry set

A practical CP device should be able to raise at least these bits/flags:

• CP not ready: ratio not locked, missing cap, or conditions not met.
• Flying cap fault / out of range: wrong value, wrong ESR, or layout too long.
• Input overvoltage: adapter delivered more than negotiated.
• NTC / JEITA fault: pack temperature outside window, fast-charge not allowed.
• Charge timeout: stuck in a stage for too long.
• Battery OVP: VBAT reached limit while CP was active.

This is enough for an MCU or master BMS to decide whether to retry, to log, or to switch to a safer source.

Why reporting matters

With reporting, you can tell whether the issue is environmental (temperature, adapter), assembly-related (flying cap), or pack-related (VBAT already high). Without reporting, everything looks like “charger does not start”.

This also helps purchasing and validation: a part that exposes the CP-specific faults indicates it was designed for this topology, similar to TI bq2597x style devices, even if we don’t list the full register map here.

I²C / SMBus style layout

Most CP fast-charge ICs use a simple map:

• STATUS: current operating state.
• FAULT: latched or latest fault.
• MASK / ENABLE: to silence non-critical events.
• ADC / telemetry: voltage, current, temperature snapshots.

An optional ALERT# or INT# pin can be used so the MCU does not have to poll all the time.

System / VSYS Power-Path Coordination

Charge-pump fast-charge is chosen to run cool, but real products must also run while charging. That means the CP path that is feeding the battery may need to feed the system (VSYS) at the same time. If this coordination is not explicit, a sudden system current step can look like a CP fault and the charger will back off — defeating the whole “low heat” point.

We therefore describe three vertical points only: (1) how CP and VSYS share power, (2) what happens when system current jumps, (3) what to do when the IC does not have a built-in power-path.

When CP is charging, who serves the system?

In the best case, the CP charger exposes a system-priority / VSYS rail that is internally tied to the CP output. The rule is simple: keep the system alive first, then continue charging the battery. This avoids brown-outs on the application processor or radio.

If the IC does not expose such a node, you must add an external power-path controller (ideal diode / OR-ing / load switch) that guarantees VSYS can draw from either VBUS/HV-IN or the battery without confusing the CP.

Conflict: system load steps vs CP fault logic

A CP fast-charger typically watches input current, capacitor health and VBAT rise. If the system suddenly pulls, for example, +1.5 A on VSYS while the CP is in 4:1 mode, the CP can see an unexpected voltage dip or current spike and misinterpret it as “cap not good” or “input not stable”.

The mitigation is to isolate fast system steps (with a local VSYS cap bank or power-path limiter) so that CP sees a reasonably slow load. That keeps the CP cool and stops it from bouncing in and out of fast-charge.

“You chose CP to run cool, don’t add heat back”

One recurring field issue is: hardware chose a CP charger to remove the inductor and spread heat, but then the system rail was hung directly on the battery node with no current shaping. The result was extra I·R and extra FET losses right on the board — exactly what CP was meant to avoid. So the layout must treat VSYS as a managed consumer, not as “just connect it”.

Brand / IC Mapping (Seven Vendors)

True 2:1 / 4:1 charge-pump fast-charge parts are most mature at Texas Instruments. Other vendors usually enter this topology from the front-end / USB-C / PD / safety / sensing side, or via a PMIC that can be paired with an external CP stage. Below is a vertical, non-overlapping mapping.

Validation & Test Playbook (Engineering)

This is the part that most generic charger pages don’t have. A charge-pump fast-charge path must be validated under high input, max current, temperature corners, and component variation, otherwise purchasing can silently replace flying capacitors or NTCs and the board will only fail in the field.

Run these as must-pass items, record the measured values, and write them into the BOM remark. That is how you lock the CP-specific parts.

High-VIN + I_CHG,max + High-T → check thermal / power foldback

Force the negotiated / front-end voltage to the high end (15–20 V), run the CP in its 2:1 or 4:1 mode, and pull the charger to its rated fast-charge current. Heat the board (hot air / chamber) to the upper spec. The CP should fold back smoothly or pause charging instead of dropping out unpredictably.

Log: VIN, I_CHG, T_board, state before/after foldback.

Flying capacitor variation → CP fault reaction

Replace the recommended C_fly with: (1) same capacitance but lower voltage rating, (2) similar value but higher ESR, (3) same value but intentionally placed farther from the CP pins. A real CP device must raise a Cfly / CP-not-ready fault or at least lower the charge power. If it happily keeps charging, it is not strict enough for battery-direct use.

Log: fly-cap PN, voltage rating, ESR, layout distance.

Battery removed / NTC forced low → block fast-charge

Unplug the battery or emulate a low-temperature NTC (below the JEITA window). The CP must stop fast-charge entry and remain in pre-charge or idle. This proves the NTC window is actually enforced.

Add system load while CP is active → robustness test

While the CP is already in fast-charge, add a system load pulse (for example +1 A on VSYS). The charger should not immediately fall back to pre-charge or throw a spurious fault. If it does, the system power-path is not well isolated and must be fixed.

Fault register walk-through → screenshots to purchasing / QA

Trigger, one by one, the CP-specific faults: Input OVP, NTC / JEITA, Cfly fault, charge timeout, battery OVP. Capture the I²C / SMBus status and save it. This is what you show to procurement so they understand the device does monitor CP components.

Write into BOM remark: “CP validation done at HV + I_max + high-T. Flying capacitors must meet IC-recommended voltage and ESR. Do not down-bin. NTC value must match JEITA table.”

Procurement & Small-Batch Notes

Small-batch CP projects fail for three very boring reasons: (1) flying capacitors get replaced with cheaper, lower-voltage MLCCs, (2) NTC values get “standardized” by purchasing, so the pack never enters fast-charge, (3) the CP main device has long lead time and nobody prepared a cross-brand / cross-layer alternative.

Say it clearly in English in your RFQ / BOM: “Do not down-bin flying capacitors; CP stages are sensitive to ESR and voltage rating.” and “Submit BOM (48h) for cross-brand CP / front-end / safety recommendations.”

Frequently Asked Questions

All questions below are specific to charge-pump fast-charge (2:1 / 4:1). We do not cover USB-C/PD negotiation, multi-cell balancing, or generic buck-boost charging here.