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USB Port eFuse – 5V VBUS Protection and Cross-Brand Paths

← Back to: eFuse / Hot-Swap / OR-ing Protection

Targeting 5 V USB VBUS, this page shows how an eFuse implements OCP/OVP, controlled VBUS discharge, reverse-backfeed blocking, BC ID pin protection, and IEC 61000-4-2 ESD as an integrated port-level safeguard. It provides A→A / A→B substitution paths with unified PG/FAULT semantics and a telemetry field set for small-batch purchasing and fast validation.

Cross-brand suggestion in 48h
PG/FAULT semantics aligned
Clean re-enumeration (to Vsafe)
USB Port eFuse cover OCP/OVP, controlled VBUS discharge, reverse-backfeed block, BC ID protection, and IEC 61000-4-2 ESD. USB Port eFuse OCP/OVP · VBUS discharge · Reverse backfeed · BC ID · IEC 61000-4-2 VBUS OCP / OVP Limit & fast-trip VBUS Discharge to Vsafe Discharge Backfeed Block Reverse current IEC 61000-4-2 ESD BC ID Pin Protect 5V VBUS · Small-batch ready
Figure — USB Port eFuse cover: OCP/OVP, controlled discharge, reverse-backfeed, BC ID & ESD.

Problems and What Each Hook Fixes

Five real issues on 5 V VBUS: hot-plug inrush trips, residual VBUS causing bad resets or enumeration, dual-source backfeed, post-ESD “latch-up” or false FAULT, and BC ID damage or mis-detection. Each maps cleanly to an eFuse capability: OCP/OVP & dV/dt, controlled discharge, reverse-block, IEC ESD with robust FAULT policy, and ID pin protection.

Symptom Likely Cause Probe Priority eFuse Hook Quick Test Pass/Fail Gate
Hot-plug trips Inrush over limit VIN ramp + load step H I_lim / I_trip_fast / dV/dt 10–100 µs short pulse I_trip_fast = 1.5–2.0 × I_load
Bad re-enumeration VBUS residual Decay to Vsafe H Controlled discharge Detach then time-to-0.3 V t_discharge ≤ budget
Backfeed/dual source Reverse path open Inject 5 V at port H Reverse-block Record I_rev_peak V_rev_thresh ≤ 20–30 mV eq
Post-ESD “dead” Latch/false FAULT IEC 61000-4-2 contact M ESD + FAULT policy Clear & retry count Recoverable & logged
BC ID failure ESD or mis-sense Probe ID pin M Series-R + clamp ESD at ID node No mis-detect after ESD
USB-VBUS problems mapped to eFuse hooks Hot-plug trips, residual VBUS, backfeed, post-ESD latch, and BC ID issues mapped to OCP/OVP, discharge, reverse-block, ESD policy, and ID clamp. Hot-plug tripsTune I_lim / I_trip_fast / dV/dt Residual VBUSDischarge to Vsafe Backfeed / dual sourceReverse-block threshold Post-ESD “dead”ESD + FAULT policy BC ID failureSeries-R + clamp eFuse Hooks • OCP/OVP & dV/dt • Controlled discharge (to Vsafe) • Reverse-backfeed block • ESD policy (IEC 61000-4-2) • BC ID protection PG = good · FAULT = protected
Figure — Typical USB-VBUS problems mapped to eFuse functions; PG/FAULT semantics unified.

Mechanism and Signal Path

The port-level flow features I_lim/I_trip_fast, V_OVP, soft-start (dV/dt), the discharge branch to Vsafe, reverse-block towards the source, and PG/FAULT/ALERT to the MCU. Priority of actions is: Fast-short > OVP > Thermal > Discharge (discharge only after source detach).

  • I_lim ≥ 1.2 × I_load_max；I_trip_fast = (1.5–2.0) × I_load_max
  • t_discharge ≤ t_system_reset_budget（e.g., 100–300 ms to Vsafe）
  • Reverse/dual source: V_rev_thresh ≤ 20–30 mV eq（near ideal-diode behavior）
Functional path of a USB eFuse Current limit, OVP, soft-start, discharge to Vsafe, reverse-blocking, and PG/FAULT/ALERT with BC ID clamp. VBUS OCP / OVP / Soft-Start I_lim · I_trip_fast · dV/dt V_OVP action priority Discharge Branch to Vsafe within budget Reverse-Block V_rev_thresh target PG FAULT ALERT / Telemetry (I²C/PMBus) BC ID Series-R + clamp
Figure — Functional path: OCP/OVP/Soft-Start, discharge to Vsafe, reverse-block, PG/FAULT/ALERT, BC ID clamp.

Selection Dimensions and Threshold Windows

Define a comparable header for cross-brand decisions and enforce windows for A→A and A→B substitution. Hard gates protect re-enumeration, reverse-blocking, and ESD survivability; soft gates allow fine tuning without changing behavior seen by the system stack.

V_OVP

5.8–6.2 V (fixed or programmable). Higher than 6.2 V risks hot-plug / enumeration timing.

t_discharge → Vsafe

100–300 ms to ≤ 0.3 V, derived from system reset/reconnect budget.

V_rev_thresh / I_rev_peak

≤ 30 mV eq target (dual-source/backfeed). Log I_rev_peak and block delay.

ESD (IEC 61000-4-2)

≥ ±8 kV contact / ±15 kV air at VBUS and BC ID pin; recoverable and diagnosable.

PG / FAULT / ALERT

PG debounce > 2–5 ms; FAULT behavior must match latch / hiccup / auto-retry policy.

I_lim I_trip_fast V_OVP t_discharge (to 0.3V) V_rev_thresh / I_rev_peak ESD (IEC 61000-4-2) PG / FAULT / ALERT Interface (I²C/PMBus) AEC-Q100 Pkg θJA / RθJA Notes
≥ 1.2 × I_load_max 1.5–2.0 × I_load_max 5.8–6.2 V ≤ 100–300 ms ≤ 20–30 mV / log peak ±8/±15 kV (port/air) PG 2–5 ms; FAULT policy Optional If required as datasheet Re-enumeration safe

0.5 A peripherals

  • I_lim ≈ 0.6–0.7 A；I_trip_fast ≈ 0.8–1.0 A
  • Require controlled discharge：Yes（frequent re-enumeration）
  • Alert bus：Optional；AEC-Q100：App-dependent
  • V_rev_thresh ≤ 30 mV

1.5 A hubs / docks

  • I_lim ≈ 1.8 A；I_trip_fast ≈ 2.5–3.0 A
  • Require controlled discharge：Yes（multi-port timing）
  • Alert bus：Recommended（health / retry logs）
  • V_rev_thresh ≤ 20–30 mV（dual-source common）

3 A fast USB loads

  • I_lim ≈ 3.6 A；I_trip_fast ≈ 5.0–6.0 A
  • Require controlled discharge：Yes（clean reset mandatory）
  • Alert bus：Recommended；AEC-Q100：If automotive
  • V_rev_thresh ≤ 20 mV（near ideal-diode behavior）
Selection matrix for USB eFuse I_lim, OVP, discharge time, reverse threshold, ESD level, and interface mapped to 0.5A/1.5A/3A scenarios. I_lim target ≥ 1.2 × load V_OVP 5.8–6.2 V t_discharge → Vsafe 100–300 ms to ≤ 0.3 V V_rev_thresh ≤ 20–30 mV eq ESD level ±8/±15 kV Interface PG/FAULT mandatory; I²C optional 0.5 A I_lim 0.6–0.7 A; fast 0.8–1.0 A Discharge: Yes Alert: Optional V_rev ≤ 30 mV 1.5 A I_lim ≈ 1.8 A; fast 2.5–3.0 A Discharge: Yes Alert: Recommended V_rev ≤ 20–30 mV 3 A I_lim ≈ 3.6 A; fast 5.0–6.0 A Discharge: Yes Alert: Recommended V_rev ≤ 20 mV
Figure — Selection matrix across I_lim, OVP, discharge, reverse threshold, ESD, and interface with three current scenarios.

Tuning and Validation Flow

Use the following executable script to complete a 48-hour bring-up. Each step states stimulus → measurements → pass gate. Keep logs for ilim_set, ilim_fast, t_discharge, i_rev_peak, fault_code, and recovery timing.

  1. Power-up current limiting — VIN trapezoid + load step.
    Measure: I_inrush, PG bounce, FAULT. Pass: no false trip; PG debounce ≥ 2–5 ms.
  2. Fast short (10 µs / 100 µs / 1 ms) — pulse to ground.
    Measure: I_trip_fast, action policy (latch/hiccup/auto-retry), t_recover. Pass: matches configuration; no abnormal reset.
  3. VBUS controlled discharge — detach source and time to 0.3 V.
    Measure: t_discharge, re-enumeration success. Pass: t_discharge ≤ budget; stable reconnect.
  4. Reverse backfeed block — inject 5 V at the port or parallel source.
    Measure: I_rev_peak, block delay, V_rev. Pass: V_rev_thresh ≤ 20–30 mV eq; no sustained backfeed.
  5. ESD (IEC 61000-4-2, port & BC ID) — contact/air levels per target.
    Measure: recoverability, fault_code_after_esd, clear steps. Pass: Recoverable & logged; no “dead” state.
  6. Thermal cycling + repeated hot-plug — high/low temp with cycles.
    Measure: PG/FAULT repeatability, T_junction, drift. Pass: consistent behavior; no abnormal rise.
PG stability
≥ 2–5 ms debounce; no chatter.
Discharge gate
t_discharge ≤ reset budget; Vsafe ≤ 0.3 V.
Reverse gate
V_rev_thresh ≤ 20–30 mV eq; I_rev_peak within limit.
ESD gate
±8 kV contact / ±15 kV air; recoverable & logged.
Test sequence for USB eFuse validation Timeline: inrush, fast short, discharge to Vsafe, reverse block, ESD, thermal cycling; with what to measure and pass ticks. Inrush I_inrush, PG Pass: no false trip Fast-Short 10µs/100µs/1ms Pass: policy matches Discharge t → 0.3 V Pass: ≤ budget Reverse-Block I_rev_peak Pass: V_rev ≤ 30 mV ESD ±8/±15 kV Pass: recoverable Thermal cycle & plug Pass: consistent Measure: I/V, PG, FAULT Log: fault_code, t_recover Log: t_discharge, re-enum Log: i_rev_peak, V_rev Log: esd_level, clear
Figure — 6-step validation timeline with key measurements and pass gates.

Seven-Brand Mapping and Substitution Paths

Use the matrix below to map 0.5 A / 1.5 A / 3 A USB VBUS ports to brand series and representative part numbers. Hard gates are enforced for V_OVP, t_discharge to Vsafe, V_rev_thresh, ESD, and PG/FAULT policy. For A→B moves, align telemetry fields (fault_code, t_discharge, i_rev) before build release. Values should be verified against the latest datasheets for the exact suffix/grade.

V_OVP
5.8–6.2 V (USB timing safe)
t_discharge → Vsafe
100–300 ms to ≤ 0.3 V
Reverse
V_rev_thresh ≤ 20–30 mV eq
ESD
±8 kV contact / ±15 kV air
Policy
PG debounce 2–5 ms; FAULT policy fixed

A→A (Pin-to-Pin, same series)

  • Allow: I_lim fine tune within ±10%.
  • Disallow: degradation on V_OVP, t_discharge, V_rev_thresh, ESD, FAULT policy.
  • PG debounce must remain within gate.

A→B (Cross-brand)

  • Map telemetry: fault_code, t_discharge, i_rev.
  • No downgrade in t_discharge or V_rev_thresh, ESD, AEC-Q100, or thermal.
  • PG/FAULT semantics must be aligned before release.
Brand Series (USB eFuse / Power Switch) 0.5 A PN 1.5 A PN 3 A PN Discharge I²C/PMBus AEC-Q100 Notes
TI TPS25xx USB power switch / TPS2595x eFuse TPS2553 TPS2561 TPS2595 Yes (family-dep.) Some variants Options USB 5 V oriented; verify exact suffix.
ST STEF / STUSB power switch STEF05 STEF12-5V class STEF33-5V class Yes/series-dep. Limited Options Pick 5 V-focused variants; confirm V_OVP window.
NXP NX5P / NX3P USB load/OVP switch NX5P2553 NX5P3090 NX3P2901 class Yes (typ.) No/Some — Known for OVP + reverse blocking on USB.
Renesas ISL6185/86 USB switch; RAA/ISL eFuse ISL6186 ISL6187 class RAA489xxx eFuse class Series-dep. Some Options Classic USB distribution controllers.
onsemi NCP380 / FPF21xx / NCP361 OVP NCP380-0.5A class FPF2123 NCP380-3A class Series-dep. No Options Check reverse-block spec per device.
Microchip MIC2005/2026/2545A USB switches MIC2005 MIC2026-1 MIC2545A Basic (ext. RC) No — Widely used per-port power limiting.
Melexis N/A for USB eFuse / USB power switch — — — — — — No native USB eFuse series (do not substitute).
Cross-brand acceptance gates Seven-brand list feeding threshold grid; right side shows pass/reject; bottom shows PG/FAULT alignment legend. Brands TI ST NXP Renesas onsemi Microchip Melexis (N/A) Threshold Grid V_OVP: 5.8–6.2 V t_discharge → Vsafe ≤ 0.3 V V_rev_thresh ≤ 20–30 mV ESD ≥ ±8/±15 kV PG debounce ≥ 2–5 ms FAULT: latch / hiccup / auto-retry Decision PASS (all gates met) REJECT (any gate fails) Legend PG = Good FAULT = Protected Align PG/FAULT semantics and telemetry fields before A→B substitution.
Figure — Cross-brand acceptance gates with unified PG/FAULT semantics and threshold windows.

BOM Remark Template (Procurement Gate)

Add the following copy-ready lines to your BOM to prevent unsafe substitutions. Each line corresponds to a validation step and encodes the non-degradable windows from this page.

Controlled discharge: USB eFuse must implement VBUS discharge with t_discharge ≤ ____ ms to Vsafe ≤ 0.3 V.

Current limit & fast short: I_lim = ____ A; I_trip_fast = ____ A; FAULT policy = latch | hiccup | auto-retry.

Reverse backfeed: V_rev_thresh ≤ ____ mV; parts lacking reverse-block are forbidden in dual-source/backfeed scenarios.

PG/FAULT semantics: PG debounce ≥ 2–5 ms. If I²C/PMBus is present, update cloud mapping (fault_code / t_discharge / i_rev) before release.

OVP window: V_OVP ∈ [5.8, 6.2] V; higher thresholds are not accepted due to USB hot-plug and enumeration timing.

ESD robustness: IEC 61000-4-2 at VBUS & BC-ID ≥ ±8 kV (contact) / ±15 kV (air); non-conforming parts are not acceptable.

Automotive & thermal: AEC-Q100 grade must not downgrade; θJA / RθJA must not worsen vs the original fit.

BOM hooks and evidence links Five BOM constraints linked to evidence: report, waveform, threshold table, logs, and automotive/thermal. Discharge t → 0.3 V I_lim / Fast-short policy fixed Reverse-block V_rev ≤ 30 mV PG/FAULT debounce & policy OVP & ESD USB safe windows Report/PDF Waveforms Threshold table Logs/telemetry Auto/thermal Each BOM constraint must link to evidence before procurement approves a substitute.
Figure — BOM hooks connected to test evidence: report, waveforms, thresholds, logs, and automotive/thermal checks.

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Fault Injection & Diagnostics

This section provides reproducible fault scripts for 5 V USB VBUS eFuse: short-circuit (SC), over-voltage (OVP), ESD, reverse backfeed, and thermal rise. For each, capture PG/FAULT/ALERT codes, telemetry fields, and recovery behavior. The goal is diagnosable & recoverable outcomes without repetitive “soft-dead” states.

Telemetry & Event Fields

Event
fault_code (SC_FAST/OVP/THERM/ESD/BACKFEED), fault_time, recover_action (LATCH/HICCUP/AUTO_RETRY/MANUAL_CLEAR)
Electrical
ilim_set, itrip_fast, t_discharge_to_0p3V, i_rev_peak, v_rev_th, esd_level_kV
Timing
t_block_delay, t_recover, pg_debounce_ms, re-enum_pass (bool)
Counters
cold_boot_cnt, brownout_cnt, consecutive_fail_cnt

Cold-boot Clear & Retry Backoff

  • On power-up, clear FAULT if consecutive_fail_cnt < N.
  • Hiccup retry: t_retry = min(t0 × 2^k, Tmax).

Thermal Gate

  • Block retries if Tj > T_hot; allow when Tj < T_cool.
  • Record THERM transitions in logs.

Recovery Priority

  • SOFT_CLEAR → PARTIAL_POWER_CYCLE → FULL_POWER_CYCLE.
  • Only escalate if the prior step fails.

Re-enumeration Gate

  • t_discharge_to_0p3V ≤ reset_budget (100–300 ms).
  • Block retries if discharge is too slow.

Short-Circuit (SC_FAST)

Pulse widths: 10 µs → 100 µs → 1 ms (×5 each).

  • Record itrip_fast, t_block_delay, recover_action, t_recover.
  • Pass: t_block_delay ≤ 2–5 µs, no hang states.

Over-Voltage (OVP)

Raise source to V_OVP + 0.2–0.4 V, hold 50–200 ms ×10.

  • Capture V_OVP_trip, t_discharge_to_0p3V, re-enum_pass.
  • Pass: discharge ≤ budget; re-enumeration ≥ 99%.

ESD (IEC 61000-4-2)

VBUS & BC-ID: ±8 kV contact / ±15 kV air, 10 shots each polarity.

  • Log fault_code=ESD, recover_action; try SOFT_CLEAR first.
  • Pass: recoverable & diagnosable, no “black-out”.

Reverse Backfeed

Inject 5 V at port or dual-source, step 0 → Iload_max.

  • Record i_rev_peak, v_rev_th, t_block_delay, fault_code=BACKFEED.
  • Pass: v_rev_th ≤ 20–30 mV, bounded i_rev_peak.

Thermal Cycling

High/low chamber + rapid plug cycles.

  • Track THERM events, PG/FAULT repeatability.
  • Pass: no thermal “soft-dead” or runaway retries.
PG Debounce
≥ 2–5 ms, no chatter
Discharge Budget
t_to_0p3V ≤ 100–300 ms
Reverse Threshold
v_rev_th ≤ 20–30 mV
ESD Recovery
Recoverable & logged
USB eFuse fault injection map Four quadrants (SC/OVP/ESD/Backfeed) funnel to PG/FAULT/ALERT outcome stream and recovery priority bar. Short-Circuit (SC_FAST) 10µs → 100µs → 1ms; record itrip_fast, t_block Over-Voltage (OVP) V_OVP + 0.2–0.4V; discharge to 0.3V ESD (IEC 61000-4-2) ±8/±15kV; prefer SOFT_CLEAR Reverse Backfeed v_rev_th ≤ 20–30mV; bound i_rev_peak Outcome Stream: PG / FAULT / ALERT + Recovery SOFT_CLEAR → PARTIAL_POWER_CYCLE → FULL_POWER_CYCLE
Figure — Fault injection map with correlated PG/FAULT/ALERT outcomes and recovery priorities.

FAQ

Answers focus strictly on this page’s scope: 5 V USB VBUS eFuse (OCP/OVP, discharge, backfeed block, BC-ID protection, IEC ESD). Each answer is 40–70 words to fit FAQPage JSON-LD.

Frequently Asked Questions

How do I size I_lim and I_trip_fast to avoid nuisance trips?

Start with I_lim ≈ 1.2× the maximum steady load, then set I_trip_fast ≈ 1.5–2.0× to catch hard shorts without tripping on inrush. Verify with staged load steps and scope the upstream profile. If the upstream has a large bulk cap, add soft-start (dV/dt) to keep the startup spectrum inside the fast-trip window.

What V_OVP is safe for 5 V without breaking hot-plug timing?

For USB 5 V ports, a practical 5.8–6.2 V OVP window preserves hot-plug behavior while protecting against overshoot. Below 5.8 V you risk false trips during cable bounce; above 6.2 V you increase stress on downstream devices. Pair OVP with PG debounce and modest RC filtering to reject brief ringing.

How fast should VBUS discharge be for clean re-enumeration?

Size the discharge path so Vsafe ≤ 0.3 V within the system’s reset budget, typically 100–300 ms. Too slow causes brown-field states and failed re-enumeration; too aggressive can stress upstream switches. Validate by cutting the source, timing to 0.3 V, and measuring restart success over 100+ cycles.

How do I prevent backfeed when two USB sources are present?

Use an eFuse or ideal-diode stage with V_rev_thresh ≤ 20–30 mV and verify the reverse current peak during switchover. Avoid simple FET-OR unless the controller enforces tight reverse thresholds. Test with dual sources and a stepped load; record i_rev_peak and recovery time to ensure no persistent back-powering.

When should I choose latch, hiccup, or auto-retry?

Latch suits safety-critical or debug-friendly products—no surprise restarts. Hiccup limits thermal stress via duty-cycled retries—great for field resilience. Auto-retry gives quick recovery but can oscillate if faults persist. Pick based on service model, thermal headroom, and your logging/telemetry capability.

What if soft-start (dV/dt) is too slow or too fast?

If ramping is too slow, upstream rails may brown out or firmware may time out. If too fast, inrush spikes can trip the fast-short comparator. Tune dV/dt so the measured inrush crest fits under I_trip_fast with margin, then confirm enumeration completes within your timing budget.

How do I protect the BC-ID pin properly?

Use a small series resistor to limit surge and a clamp device to keep the ID node within safe limits. Include the BC-ID node in your ESD test plan and probe it during strikes. Avoid long, unshielded runs; route with a clear return and ensure the clamp’s trigger pairs well with the eFuse thresholds.

How should TVS diodes and the eFuse work together?

Select a TVS with a clamping level that stays below device abs-max but high enough to avoid constant conduction. Place it close to the connector with a short return to chassis or quiet ground. Ensure the eFuse’s OVP threshold and the TVS clamp do not “double-trigger” under normal transients.

Why does PG chatter during plug/unplug and how to fix it?

Cable bounce and connector arcing can create brief dips and overshoots. Apply a 2–5 ms PG debounce and consider a small RC filter in firmware or hardware. Improve grounding at the connector, reduce loop inductance, and validate with repeated hot-plug tests while logging PG transitions.

How do I avoid false latches in IEC 61000-4-2 tests?

Control discharge paths and reference ground, and probe VBUS and PG/FAULT during strikes. Try SOFT_CLEAR first, then partial power cycle, reserving full power-down for persistent errors. Keep TVS returns short and avoid shared noisy returns with logic references to reduce unintended latch conditions.

How should I write the BOM to block “no-discharge” parts?

State explicitly: “VBUS controlled discharge required: t_discharge ≤ ____ ms to Vsafe ≤ 0.3 V.” Reference the validation step and forbid substitutes lacking reverse blocking in dual-source cases. Include PG debounce, OVP window, and ESD levels so procurement can verify against a clear acceptance table.

What acceptance windows enable safe A→A/A→B substitution?

Keep V_OVP 5.8–6.2 V, t_discharge ≤ budget, V_rev_thresh ≤ 20–30 mV, and ESD at ±8/±15 kV. Align PG/FAULT semantics and map telemetry (fault_code, t_discharge, i_rev) before release. Do not downgrade automotive grade or thermal resistance relative to the original device.

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