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Signal Model & Limits
Unify HDMI (TMDS/FRL) and DisplayPort (Main Link) into one chain: rate → bandwidth → S-parameters → eye → EQ margin. Quantify “allowable parasitics” so ESD/filter/layout has explicit headroom.
- Differential port: Zdiff=100 Ω, AC-coupled. Use Sdd21(f), Scc21(f), group delay τg, and eye to judge margin.
- Starter window: Cdiff ≤ 0.25–0.5 pF per pair; stub ≤ 0.5–1.0 mm from main path to ESD pin/pad.
- Suggested eye thresholds (tune per platform): 6/8/12/20 Gbps → width ≥ 0.60/0.55/0.50/0.45 UI; height ≥ 25%/22%/20%/18%.
Budget chain (rate → Sdd21/EQ → parasitics)
- Lock a ΔIL@Nyq (allocatable insertion loss at Nyquist) → back-solve Cdiff,max and Stubmax.
- Validate linearity with Sdd21/Scc21 + τg; ensure CTLE/DFE still has margin.
- Any EMI elements (CMC/RC/π) must pass the Sdd21 budget first, then eye. Don’t trade eye for EMI.
Cdiff / stub → ΔIL quick approximations
Cdiff_max ≤ [ 1 / (2π·f_Nyq·Zdiff) ] · √(10^(ΔIL_max/10) – 1)
Stub notch: f_notch ≈ v/(4L), v ≈ c/√ε_eff (FR-4 ε_eff≈3.4 → L=1.0 mm → ~40.7 GHz)
At 20 Gbps (Nyq≈10 GHz), long stubs push the notch into the useful band. Prefer 0.5 mm; cap at 1.0 mm.
Rate → Sdd21 budget → allocatable parasitics (Table A)
| Rate (Gbps) | Nyquist (GHz) | Channel Sdd21@Nyq (project target) | ΔIL@Nyq (allocatable) | Cdiff_max / pair (pF) | Stub_max (mm) | Notes |
|---|---|---|---|---|---|---|
| 6 | 3.0 | ≥ −Y dB | 0.5 dB | ≈ 0.185 | ≤ 1.0 (best 0.5) | Coarse check |
| 8 | 4.0 | ≥ −Y dB | 0.5 dB | ≈ 0.139 | ≤ 1.0 (best 0.5) | Tune with routing QoR |
| 12 | 6.0 | ≥ −Y dB | 0.5 dB | ≈ 0.093 | ≤ 0.8 (best 0.5) | High-rate sensitive |
| 20 | 10.0 | ≥ −Y dB | 0.5 dB | ≈ 0.056 | ≤ 0.5 | Control pads/array |
| — | — | enter value | enter value | auto back-solve | per spec | project record |
ESD Device Selection
A five-step, EQ-friendly path to choose low-capacitance ESD arrays that pass IEC 61000-4-2 and keep eye opening intact. Emphasis on channel symmetry and matched parasitics.
Five-step selection card
- Rate & ΔIL budget: Inherit Cdiff,max and Stubmax from the previous chapter’s table.
- VRWM window: VRWM ≥ the actual peak the pin may see (consider AC coupling bias and swing at each end).
- Clamp & Rdyna (TLP 8/16/30 A): Read VCL(I) and slope Rdyna=dV/dI; lower slope → lower residual stress to the PHY.
- Cdiff / Ccm & symmetry: Channel mismatch ≤ ±10% to avoid converting differential energy into common-mode leakage.
- Package & return: Prefer short-lead, center-GND, mirror-symmetric arrays; pair vias tightly to GND and keep paths length-matched.
Clamp behavior & dynamic resistance
Two landmarks on a TLP V–I curve explain most system outcomes:
- Trigger/break point: onset and speed of clamping.
- Linear slope: Rdyna governs residual stress. Arrays with lower Rdyna transfer less stress into the SERDES.
IEC 61000-4-2 (contact ±8 kV / air ±15 kV) is the qualification gate, but TLP slope often separates “pass with margin” from “just pass”.
Capacitance & symmetry
Asymmetry converts part of the differential signal into common-mode noise:
- When ΔC/C ≈ 10%, differential-to-common leakage can reach a few percent at FRL/UHBR bands, visibly shrinking eye height.
- Mitigation: internal array symmetry + external length-match + symmetric return vias.
Single-line TVS vs. multi-channel array
| Dimension | Multi-channel array | Single-line TVS |
|---|---|---|
| Routing complexity | Low (shared GND, compact) | Higher (more vias, longer stubs) |
| Channel matching | High (factory-matched) | Variable; hard to guarantee |
| Board area | Smaller for pairs/quads | Larger when scaled to pairs |
| Cost | Usually neutral/beneficial for pairs | Looks cheaper per line, not per pair |
| Mismatch risk | Low (±10% spec typical) | Higher; per-line variance adds up |
| Future replacement | Clean A→A / A→B with re-validation | Harder to maintain symmetry |
Placement & Layout
Convert the link budget into board-ready rules: ≤5 mm to connector, stub ≤0.5–1.0 mm, paired vias with tight return, continuous reference planes, and minimal pad parasitics.
- ESD-to-connector distance: ≤ 5 mm
- Differential stub length: ≤ 0.5–1.0 mm (target 0.5 mm)
- Vias: paired for each line + tight GND stitch (≤ 0.5–1.0 mm from signal via)
- Package: short body, center-GND arrays, mirrored pinout preferred
Ten Golden Rules (copy to BOM/fab notes)
- Order: Connector → ESD → main pair. No detours.
- Distance: place the array within ≤ 5 mm of the connector shell/pins.
- Stub: tap-in perpendicular; stub ≤ 0.5–1.0 mm; avoid jogs.
- Vias: pair signal vias; add adjacent GND stitch vias for each hop.
- Reference: no plane splits under the pair; fence with GND vias if crossing gaps.
- Length-match: equal pad-escape lengths and via stacks across the pair.
- Package choice: prefer center-GND arrays with symmetric pinout.
- Return path: place GND via within 0.5–1 mm of signal via and ESD GND pad.
- Pad parasitics: minimize pad stubs; use teardrops; avoid unused test pads.
- Change control: any A→B device change re-checks stub, symmetry, and S-parameters.
Why these rules protect the eye
Short distance and balanced geometry keep Sdd21 flat and group delay linear, so CTLE/DFE does less heavy lifting.
Paired signal+GND vias confine return current and reduce common-mode leakage. Continuous reference avoids mode conversion.
HPD & 5 V Protection
Glitch-proof HPD and a compact 5 V block with OVP (5.8–6.2 V), current limit (150–500 mA), and reverse-block (<1 µA)—kept at interface level (no system eFuse).
HPD debounce
- Sources of glitches: ESD re-coupling, connector wobble, contact bounce.
- Time constant: ≥ 100 µs (tune per host/OS).
- Options: RC + Schmitt or digital sampling (N-of-M + edge hold-off).
Do not over-filter; keep attach/wake timing within HDMI/DP expectations.
5 V OVP + ILIM + Reverse-Block
- OVP: 5.8–6.2 V clamp/disconnect.
- ILIM: 150–500 mA with soft-start to avoid nuisance trips.
- Reverse-Block: prevent back-power in either direction (< 1 µA leakage).
Logic & indicators
- Match IO thresholds to the SoC/bridge; add divider/level shift if needed.
- Optional PG/FAULT: PG=OK; FAULT on OVP trip / ILIM foldback (open-drain friendly).
- Counters: HPD glitches (100 ns–1 ms bins), OVP trips, ILIM events, RB occurrences.
Procurement notes (hard constraints)
- Implement HPD debounce ≥ 100 µs (Schmitt or RC + digital). Document polarity & thresholds.
- 5 V requires OVP 5.8–6.2 V + ILIM 150–500 mA + Reverse-Block (< 1 µA). Diode-only substitutions are not allowed.
- Any change to the block re-runs HPD/OVP/ILIM tests and updates telemetry counters.
EMI Filters & Chokes
Use common-mode chokes (CMC) and tiny RC/π filters only when needed. Keep EQ margin intact and respect the Sdd21 budget from the signal-model chapter.
- CMC selection: consider CM attenuation and DM insertion loss; avoid deep notches near/inside Nyquist.
- RC/π corner: f_c ≈ 1/(2πRC) — place outside data band, within EMI issue band, and within ΔIL allocation.
- Placement: after ESD, near the connector, symmetric to both lines, tight return to chassis/ground.
When a CMC helps vs. hurts
- Helps: EMI dominated by common-mode (confirmed by clamp or CM current probe), clear CM peaks on the cable/shield.
- Hurts: marginal eye at high FRL/UHBR or steep Sdd21 slope; CMC DM loss + package L/C can push a notch into the data band.
- Guardrail: verify ΔIL@Nyq and eye before/after.
RC/π sizing that stays EQ-friendly
- RC-light (per line → chassis/GND): tens of pF + small series R (≈0–2.2 Ω) for damping; keep DM impact negligible.
- π (C–R–C): use only if ΔIL headroom exists and stubs are extremely short; otherwise prefer CMC or RC-light.
- Return path: chassis caps need very low inductance (stitch vias); mirror parts to avoid DM imbalance.
Filter selection matrix
| EMI symptom | Acceptable ΔIL@Nyq | Candidate element | Placement tip | Risk flag |
|---|---|---|---|---|
| CM radiated peak @ 200–500 MHz | ≤ 0.3 dB | CMC with flat DM curve | Near connector; align choke orientation | Resonant notch with cable C |
| Broad CM noise to 100–300 MHz | ≤ 0.2 dB | RC-light to chassis (per line) | Very short stubs; symmetric parts | DM imbalance if asymmetrical |
| Narrowband spike (stubborn) | ≤ 0.5 dB | CMC + gentle RC | Validate eyes at all rates | Eye collapse at high data rate |
| DM loss already high | — | No extra filter | Fix layout/return/ESD first | — |
Validation Playbook
A single, repeatable gate: ESD → TLP → S-parameters → eyes → hot-plug/glitches → thermal → regression. One pass qualifies a device for A→B alternatives.
Test matrix & acceptance criteria
| Item | Equipment / Setup | Criteria (Pass threshold) | Result | Waveform # / Screenshot | Notes / Next action |
|---|---|---|---|---|---|
| IEC 61000-4-2 | Contact ±8 kV / Air ±15 kV; shell & TMDS shield points | No damage; no latched faults; HPD no false trigger | Pass/Fail | — | Hit count & recovery time |
| TLP 8/16/30 A | Record VCL(I) and Rdyna curves | Within vendor window; low Rdyna vs. peers | Pass/Fail | — | Attach curve IDs |
| S-parameters | Sdd21/Scc21 to ≥ 20 GHz | Sdd21 within budget; τg smooth; no deep notch near Nyquist | Pass/Fail | — | Fixture de-embed record |
| Eye diagrams | 6/8/12/20 Gbps with stressed patterns | Width ≥ 0.60/0.55/0.50/0.45 UI; Height ≥ 25%/22%/20%/18% | Pass/Fail | — | CTLE/DFE preset IDs |
| Hot-plug & glitches | 1000 insertions; inject 100 ns–1 ms HPD pulses | No false re-enumeration; 5 V spikes < OVP | Pass/Fail | — | Glitch counter logs |
| Thermal | Continuous high-bandwidth stream | ΔT keeps Tj margin; thresholds stable | Pass/Fail | — | Ambient & power logs |
| Regression A→B→A | Repeat S-params/eyes after swap back | Return-to-A matches baseline within tolerance | Pass/Fail | — | Device PN/lot trace |
Fixtures & setups (avoid false failures)
- De-embed fixtures with OSLT; keep cables matched.
- Coupons with continuous reference; stitch GND like the real board.
- Use identical CTLE/DFE presets when comparing parts; journal the IDs.
- HPD pulses: verify rise/fall & width at the harness.
- Thermal: steady ambient; thermocouple on device; log power.
Result logging template (fields)
- Test item | Equipment/Setup | Criteria | Result | Waveform # | Screenshot link | Comments
- Include: Sample ID, Board ID, Device PN/Lot, Ambient, CTLE/DFE preset.
Failure library → corrective actions
- Eye collapse @ high rate: move ESD closer, shorten stub, pick lower-C array; disable or retune CMC/RC.
- Notch near Nyquist: remove/retune CMC; shrink RC; reduce pad parasitics; re-symmetrize vias.
- HPD false triggers: debounce ≥ 100 µs; add Schmitt; improve shield/return stitching.
- 5 V nuisance trips: soft-start; adjust ILIM window; confirm OVP setpoint.
- Thermal drift: more copper/thermal vias; verify ILIM element dissipation.
Hand-off gate
One full pass admits the device into the A→B substitution list. Any BOM change triggers a targeted re-run and an A→B→A consistency check.
BOM Remarks
Hard constraints you can paste into the BOM, clear substitution gates (A→A / A→B / A→C), and a vendor-part library limited to seven major suppliers.
Answer Box — paste these into your BOM
• Low-cap ESD on TMDS/DP Main Link pairs is mandatory; Cdiff ≤ X pF/pair, channel matching ±10%.
• ESD array within ≤ 5 mm from connector; differential stub ≤ Z mm; symmetric return vias required.
• HPD must be debounce-filtered ≥ Y µs; document logic level and polarity.
• 5 V pin requires OVP + current-limit + reverse-block; diode-only substitutions are not allowed.
• Any A→B alternative must keep VRWM/VCL window and S-parameter/eye budget; re-run the full validation playbook.
• Telemetry/flags mapping (PG/FAULT/HPD status) must remain consistent; update edge/cloud mapping if changed.
Replacement paths & re-test scope
- A→A: Same vendor & family, pin-to-pin. Minor Cdiff/threshold deltas allowed. Quick regression (Sdd21 spot + eye).
- A→B: Cross-vendor equivalent capability. Run the full playbook (ESD/TLP/S-param/eyes/hot-plug/thermal).
- A→C: Capability downgrade or non-array. Temporary only, mark “EQ margin risk”; accelerate post-assembly regression.
Risk flags for purchasing & layout
- Red High-cap arrays (>~1 pF/line) on Main Link → eye collapse risk.
- Yellow Filters (CMC/π) placed where EQ margin is tight; ESD further than 5 mm (stub overrun).
- Red 5 V protected only by TVS/diode (no ILIM / no reverse-block).
- Yellow Cross-vendor swap without S-param/eye/hot-plug re-check; HPD debounce < 100 µs.
Part-number library (seven major vendors)
Grouped by use-case: (A) ultra-low-cap ESD arrays for high-speed differential pairs, (B) control/aux pins, (C) 5 V pin protection (OVP + ILIM + reverse-block). Validate against your target X/Y/Z and the Chapter-1 link budget.
A) High-speed differential ESD arrays (TMDS/DP Main Link)
| Vendor | Part number | Channels | Pkg / Notes | Typical low-C hint* | Suitable for |
|---|---|---|---|---|---|
| TI | TPD4E02B04 | 4 | USON-10; flow-through friendly | Sub-pF per I/O (array Cdiff low) | HDMI 2.0, DP HBR/HBR2 |
| TI | TPD4E05U06 | 4–6 (family) | QFN/USON; very low IO C | ~0.4–0.5 pF/IO class | HDMI/DP/USB3.x aux & lanes (budget-check) |
| ST | ECMF04-4HSM10 | 4 | CMC + ESD combo; low DM loss device | Low DM IL; strong CM attenuation | HDMI/DP (when CM peaks dominate) |
| NXP | IP4786CZ32 | Interface IC | HDMI protection/level features | Integrated approach | HDMI (verify lane loss vs. budget) |
| onsemi | ESD8004 | 4 | UQFN; routing-friendly | ~0.3–0.4 pF class | HDMI/DP/USB3.x lanes |
| onsemi | ESD8704 | 4 | Flow-through array | Ultra-low IO C | Higher-rate lanes (check Nyquist ΔIL) |
| Microchip | — | — | No native ultra-low-C arrays (prefer cross-vendor) | — | Use TI/ST/onsemi for lanes |
| Renesas | — | — | Recommend cross-vendor for ML lanes | — | Use TI/ST/onsemi for lanes |
| Melexis | — | — | No equivalent (not recommended) | — | — |
B) Control & auxiliary pins (HPD / DDC / CEC / sideband)
| Vendor | Part number | Lines | Pkg / Notes | ESD rating | Typical use |
|---|---|---|---|---|---|
| TI | TPD1E05U06 | 1 | Small DFN; low C | IEC 61000-4-2 ±8/±15 kV | HPD / DDC / CEC |
| TI | TPD2E2U06 | 2 | UDFN; paired lines | IEC ±8/±15 kV | DDC pair |
| ST | ESDALC6V1-5M6 | 5 | Multiline array | IEC ±8/±15 kV | Legacy HDMI control pins |
| NXP | PRTR5V0U2X | 2 | SOT-143B; low C | IEC ±8/±15 kV | DDC/HPD lines |
| onsemi | ESD9M5V | 1 | uDFN; very compact | IEC class | Aux/sideband GPIO |
| Microchip | — | — | Prefer TI/ST/NXP for these pins | — | — |
| Renesas | — | — | Use cross-vendor ESD arrays | — | — |
| Melexis | — | — | No equivalent (not recommended) | — | — |
C) 5 V pin protection (OVP + current-limit + reverse-block)
| Vendor | Part number | OVP window | ILIM range | Reverse-Block | Notes / Package |
|---|---|---|---|---|---|
| TI | TPS25947 | ~5.7–6.2 V (config) | Adj (hundreds of mA to A-class) | Yes (true RCB) | eFuse, soft-start, protections |
| TI | TPS25961 | Wide (2.7–19 V family) | Adj | Yes | eFuse, short-circuit / OVP |
| ST | STEF05S / STEF05SA | ~5.7 V typ clamp | Adj (small-current tier) | Yes (family-dependent) | Electronic fuse for 5 V feeds |
| ST | STEF512SRI | 5 V / 12 V dual-rail | Adj | Yes | Dual channel; RCB on 5 V rail |
| NXP | IP4786CZ32 | Integrated strategy | — | Device-dependent | HDMI interface IC (check datasheet) |
| Renesas | SLG59H1341C | Configurable | Adj | Yes | GreenFET power switch with OVP/OTP |
| onsemi | NIS6350 / NIV6350 | 5 V eFuse class | Adj | Yes | RCB, soft-start, protections |
| Microchip | MIC2545A / MIC2549A | — (use TVS/OVP ahead) | Up to ~3 A | Yes (reverse-blocking family) | High-side switches; combine with OVP TVS/eFuse |
| Microchip | MIC94165 | — (use TVS/OVP ahead) | ~3 A class | Yes (RB) | Ideal-diode-like high-side switch |
| Melexis | — | — | — | No equivalent | Not recommended for this block |
*“Typical low-C hint” is a qualitative budget cue. Always verify with the latest datasheet and your Chapter-1 S-parameter/eye budget.
Validation hand-off
Before release, tick the Chapter-6 checklist (ESD/TLP/S-param/Eyes/Hot-plug/Thermal/Regression) for any A→B or A→C change.
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FAQ
What ESD capacitance is safe for 6/8/12/20 Gbps HDMI/DP links?
Use a pair-level Cdiff ≤ X pF as the first gate (typical projects: ~0.50/0.40/0.30/0.25 pF for 6/8/12/20 Gbps). Then verify the choice with your Sdd21 ΔIL at Nyquist and stressed eye results. If either metric breaks budget, step down in capacitance or improve placement. See Signal Model & Limits.
Should I use single-line TVS or a multi-channel array for each differential pair?
Prefer a matched multi-channel array on each pair. Symmetry and channel matching reduce CM conversion and skew. Single-line TVS parts are fine for aux lines (HPD/DDC/CEC), not main links. Check pin inductance and flow-through routing. See ESD Device Selection.
How close must the ESD device be to the connector to avoid eye collapse?
Place the array ≤ 5 mm from the connector and keep the differential stub ≤ Z mm (target 0.5–1.0 mm). Order: connector → ESD → main pair. Use paired signal vias with a tight ground stitch to preserve return paths and minimize mode conversion. See Placement & Layout.
How do I verify that EQ margin is still adequate after adding an ESD array?
Measure Sdd21 and group delay to confirm ΔIL and smoothness, then run eyes at 6/8/12/20 Gbps with the same CTLE/DFE presets. Minimum pass guidance: width ≥ 0.60/0.55/0.50/0.45 UI; height ≥ 25/22/20/18 %. If close, improve placement or reduce capacitance. See Signal Model & Limits and Validation Playbook.
Do common-mode chokes always help, or can they worsen the eye at higher FRL rates?
They help when CM energy dominates (confirmed by CM probe) and the device’s DM insertion-loss is flat in-band. They can hurt by adding DM notches near Nyquist or increasing slope. Choose CMCs with flat DM curves, place near the connector, and re-check eyes/S-params. See EMI Filters & Chokes.
How do I debounce HPD to avoid false hot-plug events from ESD and cable wiggle?
Use ≥ Y µs debounce with either RC + Schmitt or digital sampling (N-of-M + edge hold-off). Count glitches (100 ns–1 ms) for diagnostics and ensure timing remains within platform/OS expectations. Keep routing short and reference the shield/ground properly. See HPD & 5 V Protection.
What OVP/ILIM settings protect the 5 V pin without tripping during inrush?
Set OVP ≈ 5.8–6.2 V and choose ILIM ≈ 150–500 mA with soft-start to tame inrush. Validate with hot-plug/worst-case loads and log trips. Keep the protection block at interface level; diode-only solutions are not acceptable for HDMI/DP 5 V pins. See HPD & 5 V Protection.
How do I prevent 5 V back-powering the source or sink during hot-plug?
Use a reverse-current-blocking switch/ideal-diode element, oriented for the actual power-flow direction, and target leakage < 1 µA. Reproduce attach/detach sequences on both ends and verify no unpowered device is back-biased through the cable. See HPD & 5 V Protection.
Can I reuse a USB-rated ESD device on HDMI/DP lines?
Only if its capacitance, dynamic resistance, and package inductance meet your S-parameter and eye budgets. Many USB3 parts work on aux pins; far fewer suit main-link data rates. Always confirm with ΔIL@Nyq, τg, and stressed eyes on your board. See ESD Device Selection and Signal Model & Limits.
How do I write BOM remarks so purchasing won’t pick a high-cap ESD part?
Use hard, copy-ready sentences: “Low-cap ESD on TMDS/DP pairs is mandatory; Cdiff ≤ X pF/pair, channel matching ±10%.” “ESD within ≤ 5 mm; stub ≤ Z mm; symmetric return vias required.” Add gates: any A→B swap must preserve VRWM/VCL and pass the validation playbook. See BOM Remarks.
What TLP/IEC tests should be in the qualification plan for this interface?
Include TLP 8/16/30 A (record VCL(I) and R_dyna) and IEC 61000-4-2 ±8 kV contact / ±15 kV air at the shell and shielded pins. The device must survive without latch-ups or HPD false triggers; attach curves, hit counts, and recovery logs. See Validation Playbook.
How do I document S-parameters and eye results for supplier alternatives?
Provide a traceable bundle: de-embedded Sdd21/Scc21 to ≥ 20 GHz, τg, overlays vs. budget; eyes at 6/8/12/20 Gbps with final CTLE/DFE presets; sample/board IDs, ambient, and screenshots/waveform links. Add hot-plug/thermal outcomes and an A→B→A regression page. See Validation Playbook.
