← Back to: eFuse / Hot-Swap / OR-ing Protection
Architecture & Signal Semantics
Front-end chain: Source → EMI/suppressor → eFuse → Cbulk/buffer → Motor Driver (VM/VS) → Motor. Signals: I_LIMIT (current limiting), dV/dt (soft-start), Fast-Trip (short/locked-rotor fast cut), PG/FAULT, UV/OV, OTP, and retry/backoff. Align PG so that VOUT ≥ UVLO × 1.10–1.15.
Inrush (approx.): I_inrush ≈ C_bulk × (dV/dt)
I²t / thermal: ∫ I(t)² dt ≤ I²t_eFuse@T (derated at temperature)
PG timing: t_PG = f(C_bulk, I_LIMIT, dV/dt, R_path)
- Separate Fast-Trip window from normal current limiting.
- PG filtering (RC) to avoid false “PG high” during ramp or ringing.
- Thermal headroom ≥ 15 °C at high ambient; verify ∫I²dt vs eFuse limits.
- Kelvin sensing for shunt/limit node; keep power loop short/straight.
Startup Inrush Shaping
Shape startup current to meet system limits and timing. Combine dV/dt control, I_LIMIT ramping, and optional pre-charge to keep I_inrush and thermal stress inside the safe window while aligning with driver UVLO and PG.
- Set I_peak_max from source/loom limits; estimate I_inrush via C_bulk × dV/dt.
- Back-calculate required dV/dt or I_LIMIT for target t_rise and t_PG.
- Verify t_PG while enforcing VOUT ≥ UVLO × margin (1.10–1.15).
- Check ∫I²dt and junction temperature at high ambient (e.g., 85 °C).
- Add PG filtering and damping to prevent false PG on ringing.
- I_peak ≤ design limit; t_rise meets system requirement; PG order correct.
- No spurious FAULT during ramp; thermal headroom ≥ 15 °C.
- Corners: C_bulk (small/medium/large) × temperature (−40/85 °C) stable.
Design formulas:
I_inrush ≈ C_bulk × (dV/dt)
t_rise ≈ ΔV / (dV/dt)
Condition for PG: VOUT ≥ UVLO × margin (margin = 1.10–1.15)
Locked-Rotor Fast-Trip vs Current Limiting
Separate the fast-trip action for hard faults and locked rotor from normal current limiting used for heavy-load startup. Use measured ILRA (typically 4–7× rated) as the reference, enforce an I²t limit with temperature derating, and keep the fast-trip window clearly separated from the limiting plateau to avoid edge chatter.
Design equations (ASCII)
I_FT = α · I_LRA (α = 1.2–1.8, start with 1.5)
∫₀→t_FT I(t)² dt ≤ I²t_abs@T (include temperature derating)
I_LIMIT_max ≤ β · I_FT (β ≈ 0.6–0.8 for clear separation)
Steps & tests
- Measure I_LRA with mechanical lock (3–5 samples); use P95 as design value.
- Pick I_FT = 1.5 × I_LRA; verify I²t and R_ON heating.
- Set t_FT so hard short always trips but heavy-load starts do not (50–200 µs baseline).
- Choose I_LIMIT ≤ 0.6–0.8 × I_FT; compensate loop to ignore spikes.
- Add RC filtering to sensing and PG/FAULT; qualify false/miss trip rates.
Test guidance
- Lock rotor for 1 s and log I(t), VOUT(t); verify t_FT and peak junction temperature.
- Inject noise/ringing to estimate nuisance trip (false) and miss trip (escape) rates.
Timed Restart Policy & Brown-Out Avoidance
After a fault, retry safely without thermal oscillation or brown-out chatter. Use a bounded N_max, a temperature-aware t_cool, and an exponential backoff. Align PG with the driver UVLO so restarts happen only when VOUT ≥ UVLO × margin.
N_max: maximum retries (typ. 3).
t_cool: 100–300 ms first interval; tune with thermal mass and ambient.
Backoff: 1× → 2× → 4× … to avoid oscillation.
Lockout: after N_max, require manual/system reset.
PG/UVLO align: VOUT ≥ UVLO × margin (1.10–1.15).
Recommended defaults
N_max = 3; t_cool₁ = 150 ms; backoff = 150/300/600 ms; lockout afterward. Log reason, retry index, T_J_peak.
Pseudocode (ASCII)
retry = 0
while (retry < N_max):
wait_until(fault_cleared and cool_ok and Tj < Tj_limit)
enable_output()
if PG_valid and Vout >= UVLO * margin:
break # normal run
else:
disable_output()
retry += 1
wait(backoff_ms(retry)) # 1x, 2x, 4x ...
if retry >= N_max:
lockout()
Rules of thumb
- Start with N_max = 3; smaller packages or weaker copper need longer t_cool.
- PG asserts only when VOUT ≥ UVLO × margin; add RC to avoid false PG.
- Record reason/temperature/retry index to aid field analysis and quality loops.
Reverse-EMF, Clamp & Re-Energization Safety
Goal
Handle reverse EMF during coast-down or back-drive so the front-end bus is not raised enough to re-energize the system. Prevent reverse charging of the upstream source and mask PG when reverse voltage is present.
Paths & Countermeasures
- Reverse path: Motor → driver body path → eFuse → upstream bus/loom.
- Near-node clamp: TVS/RC between driver and eFuse to cap VBUS rise.
- Reverse blocking: Use eFuse with reverse withstand or add ideal-diode stage to stop back-charge.
- Thermal check: TVS pulse power & dynamic resistance; eFuse reverse limits (V_REV/I_REV/t_REV).
- PG masking: PG_valid ⇔ (V_IN_fwd_ok ∧ V_REV < V_rev_th) with 5–20 ms debounce.
Design equations (ASCII)
V_EMF ≈ k_e · ω ; I_gen ≈ (V_EMF − V_BUS) / R_path
P_TVS ≈ (V_CLAMP − V_BUS) · I_gen ; E_TVS = ∫ P_TVS dt
Ensure V_CLAMP < absolute max of Driver/eFuse; satisfy derating with ≥ 15 °C thermal headroom.
Verification
- Back-drive at 2× rated speed for 3 s; capture V_peak, I_gen, E_TVS, T_J(TVS/eFuse).
- Step unload/abrupt stop: check V_BUS rebound, ringing, and RC damping effectiveness.
- With upstream open, confirm PG stays masked (no re-enable from reverse-raised bus).
- Log fields: reason=reverse-EMF, V_peak, E_TVS, T_J_peak, PG_masked_ms.
Layout & Thermal Integrity
Principles
- Kelvin sense: SS+ / SS− as a true pair from the shunt/limit node; no shared copper with power loop.
- Min loop area: VIN → eFuse → C_bulk → Driver → GND short/straight and close to connector/driver.
- Near-node parts: C_bulk and TVS at the protected node; PG/FAULT pull-ups & RC near pins.
- Partitioning: Separate sensitive analog vs power; define explicit return paths.
- Thermal spreading: Thicker copper, via-array under eFuse/TVS, couple to chassis if available.
- Crosstalk: Keep PG/FAULT away from SW/high-di/dt traces; add ground shielding when needed.
Checklist
- Hot-spot temperature meets derating curve (≥ 15 °C headroom).
- Sense integrity: differential/common-mode noise < comparator jitter threshold; RC at pins.
- Loop area minimized; PG/FAULT avoid long parallel runs over power region.
- Thermal path: via matrix to spreader/chassis; no isolated hot islands.
- Test pads reserved for Kelvin and thermocouples; fixtures can connect directly.
Cross-Brand Options (TI / ST / NXP / Renesas / onsemi / Microchip / Melexis)
Goal — Build a cross-brand option set for a motor/driver front-end eFuse so that small-batch substitutions preserve timing, semantics, and protection policy. Only list officially active, verifiable parts. Always verify PG/FAULT semantics, UVLO window, fast-trip family, and restart policy before release.
Comparison axes
- VIN rating & transient capability (12/24 V systems; cold crank, load dump, industrial surge)
- I_LIMIT and Fast-Trip ranges & curve families; I²t / thermal limits
- Soft-start programmability & pre-charge / pre-bias tolerance (dV/dt)
- Restart policy (auto / limited / latch; programmable backoff)
- Conduction & thermal: RDS(on) or external FET, package, θJA
- PG/FAULT semantics (polarity, level, open-drain vs push-pull, deglitch)
- Compliance & lifecycle: AEC-Q, ESD/surge levels, supply status
Texas Instruments
- LM5069 — 9–80 V hot-swap controller, external MOSFET, programmable current limit/timer, PGOOD, latch/auto-retry.
- TPS2663 — 4.5–60 V eFuse with integrated FET (~0.6–6 A), power-limit, dV/dt, fault reporting.
Use LM5069+external FET for higher LRA/energy; TPS2663 for mid-current integrated eFuse. Align PG window to driver UVLO.
STMicroelectronics
- STEF01 — 8–48 V programmable eFuse: UVLO/OV clamp, configurable dV/dt, thermal shutdown, latch/auto-retry, PG/FAULT.
- STEF48H28 / STEF12H60M — higher-current eFuse variants for 24 V / 12 V rails.
Rich feature set for timing alignment; confirm PG polarity and FAULT clear timing.
Renesas (Intersil)
- ISL6146 — 9–80 V hot-swap controller, external MOSFET, programmable limit/timers, PGOOD.
Peer to LM5069 for large VM bus; fast-trip via sense/timer network tuned to motor LRA.
onsemi
- NIS5420 — ~12 V eFuse (~4 A class), ISENSE, UVLO/thermal, latch.
- NIS5020 / NIS5021 — industrial eFuse family with ramp control & diagnostics; inductive/motor protection app notes.
Fit mid-current channels; review deglitch & FAULT hold times for restart alignment.
Microchip
- MIC2586 — 10–80 V hot-swap controller, external MOSFET, programmable limit, PGOOD.
Large bus with external FET; pair with logic for exponential backoff and event logging.
NXP
- MC10XS3535 / MC34HS family — automotive high-side smart switches with current limit, thermal, diagnostics.
Use when a channel-level high-side switch can assume eFuse duties; remap PG/FAULT semantics and restart policy.
Melexis (Companion)
- MLX91220 / MLX91221 — Hall current sensors for accurate LRA capture & I²t calibration.
Sensing companion only; not a front-end eFuse.
Procurement flags — paste into BOM remarks
- Match PG meaning and driver UVLO window (PG high only when VOUT ≥ UVLO × 1.10–1.15).
- Align fast-trip curves and restart policy (avoid ping-pong oscillation).
- Update test scripts, thresholds, I²t limits, and event codes whenever the brand changes.
Validation Scripts & Pass/Fail Criteria
Goal — Provide a reproducible test script set and pass/fail criteria for startup inrush, locked-rotor, cable short, timed restart, reverse-EMF, and immunity. Results are CSV-friendly and image-library-friendly for review and audits.
Startup Inrush
Cbulk (small/medium/large) × temperature (25/85 °C).
Record: I_peak, t_rise, PG_delay, UVLO_margin. Pass: I_peak ≤ limit; after PG, VOUT ≥ UVLO × 1.10.
Locked-Rotor
Mechanical lock × 10 repetitions.
Record: t_FT, I²t, T_J_peak. Pass: within fast-trip window; board shows no collateral damage.
Cable Short
Hard short at VOUT × 10 repetitions.
Pass: trip time < 50–200 µs (device-dependent), T_J controlled.
Timed Restart
N = 1/3/5; backoff 1×/2×/4×.
Pass: no thermal oscillation; retry statistics & event logs correct.
Reverse-EMF
Externally drive to 2× rated speed for 3 s.
Pass: V_clamp < absolute max; T_J controlled; no unintended re-energization.
Immunity (Surge/ESD/EFT)
IEC surge, contact/air ESD, EFT bursts.
Pass: no nuisance trip or miss trip; PG does not drift.
Scope/Logger CSV fields
time_s, VIN_V, VOUT_V, I_LOAD_A, PG, FAULT, TJ_C, EVENT_CODE, TEST_POINT_ID
Request a Quote
Small-Batch Procurement & BOM Notes
Goal — Provide copy-ready BOM sentences and strict red lines for small-batch substitutions in a motor/driver front-end eFuse design. This chapter links to the cross-brand options and validation scripts so purchasing and engineering use the same semantics, thresholds, and evidence.
- Front-end eFuse shall support programmable fast-trip and timed restart; attach scope evidence and a parameter file for the chosen settings.
- PG must assert only after VOUT ≥ Driver-UVLO × 1.10; provide the UVLO reference and measurement proof.
- Provide I²t derating at 85 °C; default retry N = 3 with 1×/2×/4× backoff unless otherwise justified.
- Reverse-EMF clamp is mandatory for coast-down; list the clamp rating and conduction path.
- Select parts only from TI / ST / NXP / Renesas / onsemi / Microchip / Melexis; update cross-brand mapping and test thresholds before use.
- Do not replace a design that requires fast-trip with a device that only provides current limiting.
- Do not substitute without verifying PG/FAULT semantics and driver UVLO alignment.
- Do not change to a device with a different restart policy (auto vs latch/backoff) without updating scripts—this causes field chatter/oscillation.
Any substitution must trigger: threshold/script updates, I²t limits, PG/FAULT polarity and de-glitch, event codes, and re-execution of Startup, Locked-Rotor, Timed Restart, and Reverse-EMF tests.
- Scope screenshots for PG/FAULT and startup waveforms with markers.
- CSV logs with fields: time_s, VIN_V, VOUT_V, I_LOAD_A, PG, FAULT, TJ_C, EVENT_CODE, TEST_POINT_ID.
- I²t vs temperature curves and thermal rise evidence.
- Reverse-EMF clamp path and rating proof.
FAQ
How do I pick I_LIMIT and dV/dt with heavy C_bulk and motor inductance?
Balance peak current and startup time: set I_LIMIT to keep I_peak within source and harness capability, then choose dV/dt so PG asserts after VOUT reliably clears UVLO × 1.10. Verify I²t and temperature rise at 85 °C. Pre-charge or staged ramp can reduce differential voltage and ringing on long harnesses.
What is the difference between Fast-Trip and current limiting in a locked-rotor case?
Fast-Trip uses a higher threshold and much shorter delay to guarantee interruption under hard surges or shorts. Current limiting produces a controlled plateau for heavy-load ramps. Keep a clear separation: I_LIMIT ≤ 0.6–0.8 × I_FT and tune the delay so hard shorts always trip while high-load starts proceed without nuisance triggers.
What is a safe number of timed restarts?
Three retries is a robust default. Use a temperature-aware cool-down window and exponential backoff (1×/2×/4×) to avoid oscillation. Smaller packages or limited copper need longer intervals. After N_max, latch off and require a supervised reset so repeated stalls do not accumulate thermal stress or field complaints.
How do I align PG with the driver UVLO?
Require PG to de-assert during faults and assert only when VOUT ≥ UVLO × 1.10. Add RC deglitch to PG and noise filtering on the sense network. The driver should enable only after PG is valid for a minimum time. Record the measured UVLO reference and the PG-assert margin in the parameter file and scope captures.
Can reverse EMF re-energize the path during coast-down?
Yes. A back-driven motor can lift VOUT and force current through body paths. Provide a defined clamp path with a rated TVS or snubber, confirm reverse-tolerance of the eFuse or external MOSFET, and measure peak voltage and absorbed energy at 2× rated speed. Ensure the clamp voltage stays below absolute maximums with thermal margin.
Which layout mistakes most often cause nuisance trips?
Non-Kelvin current sense routing, long or narrow high-current returns, remote TVS placement, and PG traces near noisy edges are typical causes. Keep the VIN→eFuse→C_bulk→Driver loop short and wide, bring sense leads out as Kelvin pairs, add ground-referenced shields where needed, and deglitch FAULT/PG at the controller and the MCU.
Is AEC-Q qualification mandatory for small-window motors?
It depends on the end-system standard. For automotive or harsh industrial profiles, AEC-Q and surge/ESD evidence are typically required. Where it is optional, provide temperature-rise and lifetime data and confirm emissions/immunity. If the product may later migrate to automotive platforms, prefer AEC-Q devices to avoid re-qualification cycles.
How do I validate Fast-Trip without damaging hardware?
Use a bounded load fixture and a step source to reproduce surge shapes within safe energy. Start with milder thresholds and shorter durations, then tighten toward the target curve. Log t_FT, I²t, and T_J for each run, and inspect for collateral damage. Maintain a cool-down interval between shots to prevent cumulative heating.
What is a good default cool-down time between restarts?
Start with 100–300 ms for the first retry and increase via exponential backoff. Packages with less copper or higher R_DS(on) need longer cool-downs. Monitor junction temperature or infer it from I²t and ambient. If the eFuse provides thermal status, gate retries on that flag and lock out after the configured maximum retry count.
How can telemetry differentiate a cable short from a locked rotor?
A cable short shows a rapid VOUT collapse with very steep current rise; a locked rotor rises fast but usually plateaus near the limit. Compare voltage slope, residual level, and I(t) contour, and correlate with mechanical sensors or a Hall current sensor. Use distinct event codes to aid field diagnosis and regression testing.
Will a larger bulk capacitor reduce audible chatter on restarts?
Sometimes, but it trades noise for stress. A larger C_bulk can smooth supply dips yet increases inrush, I²t, and startup time. Re-compute I_LIMIT and dV/dt, re-check PG timing versus UVLO, and verify thermal limits at 85 °C. If chatter persists, improve restart backoff and sense filtering rather than relying solely on capacitance.
For procurement, what must match across brands before substitution?
Match PG/FAULT semantics and timing, fast-trip curve family, restart policy, and the UVLO window. Then port thresholds and de-glitch settings into scripts and parameter files. Re-run startup, locked-rotor, restart, and reverse-EMF tests. Do not release substitutions that fail any of these alignments, even if electrical ratings look similar.
