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Multi-Rail Programmable Supervisor

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What It Solves

Slow ramps & chatter

At dV/dt → 0, simple UV trips chatter and reboots the system. Windowed thresholds with hysteresis and blanking suppress oscillations during bring-up or brown-out.

Cross-domain RESET compatibility

RESET/PG must fan out to 1.8/3.3/5 V logic. Open-drain outputs with per-domain pull-ups avoid level conflicts and timing skew.

Dependency order

Core → DDR → IO must be deterministic. PG aggregation with programmable delays enforces ordering even under noise and skew.

Temperature drift

Trip points shift across corners. Specify tolerance & tempco, then set VIT-/VIT+/Vhys with margins validated at −40~105 °C.

Glitches & EMI

Fast spikes create false trips. Combine small input RC, programmable blanking (tGLITCH), and adequate hysteresis.

Black-box bring-up

Failures without evidence waste days. Power-Fail Tagging logs which rail, when, how long—recoverable post-reset.

Per-rail window + hysteresis

Detect UV/OV and tame slow ramps. Start with 1–2% of nominal for Vhys, refine after slope & ripple tests.

Blanking / glitch filter

tGLITCH 5–50 µs filters spikes; coordinate with RC and comparator bandwidth.

PG aggregation & delay

OR/AND trees with tDELAY 2–20 ms encode Core→DDR→IO dependency.

Reset pulse width

tRST 10–50 ms aligns with slowest clock/PLL lock; one reset, clean boot.

Power-Fail Tagging

Structured event: rail_id, cause, t_start, t_duration, temp, cfg_crc. Log-before-reset.

I²C/PMBus configuration

Field-tune thresholds, hysteresis, blanking, and pulse widths. Lock map & checksum in production.

Engineering takeaways

  • Specify VIT−/VIT+/Vhys with tolerance & tempco; validate −40~105 °C.
  • Pick tGLITCH from noise profiling; start 5–50 µs, adjust with RC and routing.
  • Program tDELAY by dependency DAG; ensure PG skew doesn’t break order.
  • Set tRST to the slowest domain+PLL lock plus safety margin.
  • Always log-before-reset for post-mortem clarity.
Multi-rail window supervision with I²C/PMBus, PG aggregation, and power-fail tagging Left: rails (VCORE, VDDR, VIO, VANA) → window comparators with hysteresis → I²C/PMBus regmap → PG/fault aggregation → reset/fanout; top-right: power-fail tag with timestamp. VCORE VDDR VIO VANA Window UV/OV + Hysteresis V_IT− / V_IT+ V_hys t_GLITCH t_DELAY t_RST I²C / PMBus Thresholds · Blanking · Pulse PG Aggregation OR/AND · Delay chain System Reset Fanout to domains Power-Fail Tag rail · cause · tstamp Log-before-reset

Architecture & Signal Levels

Sensing → Window comparators

Divider/Buffer feeds dual comparators around a bandgap-based reference. Trip points are trimmed; combined with Vhys and tGLITCH to reject ripple and EMI.

Outputs: Open-drain vs Push-pull

Open-drain (recommended) for cross-domain fanout; each domain re-pulls to its own rail. Push-pull only if receivers share the same domain and timing.

Level shifting for I²C/PMBus

Place level shifters near the host. Keep SCL/SDA away from switching nodes; size pull-ups for rise time without overloading.

Pull-up selection & fanout

  • Start with 10–47 kΩ. Long traces/many loads: 10–22 kΩ; short/light loads: 22–47 kΩ.
  • Rise time must meet the slowest receiver’s sampling window; verify by scope, not estimation only.
  • For multi-domain fanout, keep source OD and re-pull in each destination domain (1.8/3.3/5 V).

Reference & drift budgeting

Total trip-point drift = bandgap tempco + divider tempco + comparator offset vs temp. Use worst-corner drift to size Vhys and tGLITCH margins.

  • Core rails (≤1.2 V): target ±1–2% trip accuracy; I/O rails: ±2–3%.
  • Document trim channel & production read-back; store cfg_crc for traceability.
Open-drain vs push-pull reset outputs, pull-ups to host rail, fanout across logic domains Left: supervisor outputs (OD/PP). Middle: OD with pull-up to host rail and RC rise. Right: fanout to 1.8 V, 3.3 V, 5 V domains with per-domain pull-ups and optional buffer. Supervisor Outputs Open-Drain (OD) Push-Pull (PP) OD → pull-up to Host I/O 10–47 kΩ RESET/PG node (rise RC) Host I/O rail Rise time must meet slowest receiver’s sampling window Fanout to Domains 1.8 V domain pull-up 3.3 V domain pull-up 5 V domain pull-up buffer

BOM anchors (paste-ready)

  • RESET/PG outputs must be open-drain; each destination domain shall re-pull to its own rail. Push-pull allowed only by explicit approval.
  • Pull-ups 10–47 kΩ; long traces/many loads 10–22 kΩ. Verify rise time by scope against slowest receiver.
  • I²C/PMBus register map (thresholds, hysteresis, blanking, pulse widths) shall be version-locked and production read-back checked.

Thresholds & Timing

Window & Hysteresis

VIT− (lower) and VIT+ (upper) define the window; Vhys = VIT+ − VIT− rejects ripple and slow dV/dt oscillation. Start with 1–2% of nominal and refine by slope/ripple tests.

Blanking / Glitch Filter

tGLITCH (5–50 µs typical) masks short spikes that the analog RC and comparator bandwidth cannot absorb. Tune with measured EMI spectrum and layout.

PG Delay & Reset Pulse

tDELAY enforces dependency order (Core→DDR→IO). tRST (10–50 ms typical) must cover the slowest clock domain + PLL lock with margin.

PFT Time Alignment

Power-Fail Tagging uses a monotonic time source (RTC or tick). Log-before-reset to preserve rail_id, cause, t_start, t_end, temp, cfg_crc.

Slow-slope immunity (dV/dt → 0)

  • Use ΔVwindow ≈ 2·Vhys when ramps are very slow; this distinguishes true crossing from jitter.
  • Pick tGLITCH = 5–50 µs so that ripple/µs spikes are filtered but genuine faults pass; verify with injected pulses at 1/5/10/50 µs.
  • Co-design RC at the sense node; RC handles ns–sub-µs content, tGLITCH covers the µs band.

Typical setup — Core

0.9–1.1 V rails: accuracy ±1–2%. Start with VIT−=0.93·Vnom, VIT+=1.07·Vnom, Vhys≈2%·Vnom; tGLITCH=10 µs; tDELAY=10 ms; tRST=30 ms.

Typical setup — DDR

1.2/1.35/1.5 V rails: Vhys 1.5–2%; tGLITCH=10–20 µs; tDELAY=8–12 ms; tRST=30–40 ms; confirm against DRAM training window.

Typical setup — IO

3.3/5 V rails: Vhys 1–1.5%; tGLITCH=5–10 µs; tDELAY=5–10 ms; tRST=20–30 ms; validate receivers’ VIH/VIL with pull-up strategy.

Reset pulse vs slow clock domains

tRST ≥ 3–5 cycles of the slowest clock domain (e.g., 32 kHz → 94–156 µs baseline) plus propagation and debounce. For complex bring-ups, 10–50 ms ensures one-shot recovery.

Upper/lower window thresholds, hysteresis, blanking, and reset pulse under slow ramps and jitter Rail waveform with slow ramp and jitter; horizontal lines for V_IT+ and V_IT−, V_hys arrow, shaded t_GLITCH windows, PG delay bar, and t_RST pulse marker with log-before-reset note. Voltage Time → V_IT+ V_IT− V_hys Jitter band t_GLITCH t_GLITCH t_DELAY (PG aggregation) t_RST Power-Fail Tag rail · cause · tstamp Log-before-reset

Integration & Sequencing

Model dependencies as a DAG

Encode Core → DDR → IO → Peripherals as a directed acyclic graph. Each edge is a “necessary condition”. Map the DAG to a programmable delay chain: upstream PG true → start downstream timer → release only if still true at timeout.

PG aggregation (AND/OR + delay)

All-good (AND) to release System_PG; Any-bad (OR) to revoke it. Use digital delays (registers) for determinism; add small RC or digital debounce at the final stage to absorb skew.

“Necessary gate” & clocks

Core-PG and CLK_OK compose the gate that allows DDR release. Avoid feedback that lets downstream nodes influence upstream PG—keep the graph acyclic.

Power-down & PFT

  • On brown-out: TAG first (rail/cause/tstamp), then assert System_RESET or revoke System_PG, then optional shutdown.
  • Provide retention for the last event (FRAM/MRAM/supercap) or a short buffered upload path.
  • On next boot, WDT/bootloader reads PFT and selects diagnostics vs normal path.

Verification checklist

  • Worst-case PG skew across rails does not violate order after delays.
  • Glitch-then-drop: upstream PG briefly true then false — downstream timer cancels properly.
  • Timeout branch: if a rail never stabilizes, system enters a safe path without thrashing resets.
Per-rail PG aggregation with delay chain; dependency DAG ensures deterministic order Left: per-rail PG waveforms with different arrival times and debouncing. Middle: AND/OR logic and programmable delay blocks. Right: System_PG and Reset release timing; DAG mini-map shows Core→DDR→IO. Per-rail PG PG_CORE PG_DDR PG_IO deb deb deb AND (all-good) PG_CORE · PG_DDR · PG_IO OR (any-bad) fault revoke Delay chain t_DELAY per stage System_PG & Reset System_PG Reset release Dependency DAG Core DDR IO

BOM & firmware anchors (paste-ready)

  • Programmable tDELAY is required; ship with a documented DAG-to-delay map and lock configuration version/CRC.
  • Log-before-reset for power-down; PFT visibility at first boot step is mandatory.
  • WDT/RTC interface order must remain PFT_read → WDT_kick → normal_boot across brand swaps.

Validation

Reproducible experiments

  • Ramp slope injection: 0.1 / 0.5 / 1 / 5 V/ms
  • Glitch injection: ±(Vhys/2) @ 1/5/10/50 µs
  • Temperature sweep: −40 / 25 / 85 / 105 °C
  • Load transients: light ↔ heavy to induce ripple

Pass/fail criteria

  • Threshold error within spec (% of VIT±) across temp
  • No false trips at specified slopes/glitches
  • PG order achieved with configured tDELAY
  • PFT (Power-Fail Tag) recorded before reset
Rail Slope (V/ms) Glitch ±(Vhys/2) Width (µs) Temp (°C) Load Result Recommendation
Core (1.0 V) 0.1 Yes 1 / 5 / 10 / 50 −40 / 25 / 105 Light→Heavy Pass/Borderline Increase Vhys to 2%·Vnom, set tGLITCH=10 µs
DDR (1.2/1.35/1.5 V) 0.5 / 1.0 Yes 5 / 10 −40 / 85 Heavy→Light Pass tDELAY ≥ DRAM training + margin
IO (3.3/5 V) 5.0 Yes 1 25 / 85 Light Fail Raise tGLITCH to 10 µs; add small RC at sense node

If borderline or fail, do this

  • ↑ Vhys (≥ ripple×3 + temp drift)
  • ↑ tGLITCH to 10–50 µs; co-design with input RC
  • ↑ tDELAY ≥ 3× power loop settling time
  • Check pull-ups and fanout buffering for PG/RESET nets
  • Ensure PFT is “log-before-reset” and readable on next boot
Pass/fail heatmap for slope, glitch, and temperature across rails Slope vs glitch width cells per temperature band; colors: green pass, yellow borderline, red fail. Right column lists corrective actions. Slope (V/ms) Recommendations Pass Borderline Fail 1 µs 5 µs 10 µs 50 µs 1 µs 5 µs 10 µs 50 µs 0.1 0.5 1.0 5.0 −40 / 25 °C 85 / 105 °C If yellow/red, try • ↑ V_hys (≥ ripple×3) • ↑ t_GLITCH to 10–50 µs • ↑ t_DELAY ≥ 3× settling • Add small RC at sense • Re-check pull-ups/fanout • Ensure log-before-reset Triangles inside cells (not shown): Core DDR IO

Cross-Brand IC Mapping

Bucketed by function with rails, accuracy, output type, interface, tempco, and AEC-Q100. Use this as a procurement guide; verify lifecycle/PCN before PO.

Multi-Rail Supervisor Windowed Supervisor µP Supervisor POR/BOD Reset Fanout PB-Debounce RTC-Switchover Simple WDT Windowed WDT
Brand Family / PN Bucket Rails Accuracy (%) Output IF Tempco AEC-Q100 Notes / Why this part
TI TPS386000 / TPS386000-Q1 Multi-Rail Supervisor 4 ±1–2 OD / PP OTP + GPIO Low Yes (-Q1) Quad rail with programmable delays/MR; easy PG fanout across domains.
TI UCD9090 / UCD9090-Q1 Multi-Rail Supervisor (PMBus) 10 ±1–2 (ADC-based) OD (config.) PMBus/I²C Low Yes (-Q1) Centralized thresholds, delays, sequencing, and event capture—ideal for complex rails.
ST STM6717 / STM6719 Windowed / µP Supervisor + PB 2–3 (var.) ±2–3 OD / PP (var.) OTP / I²C (family-dep.) Medium Some Good for IO/RTC domains; includes push-button reset debounce options.
ST STM1001 µP Supervisor / POR-BOD 1 ±2–3 PP (typ.) OTP Medium — Low-cost end-point reset; good as local fanout driver.
Renesas ISL88001 / ISL88002 / ISL88003 µP Supervisor + WDT/MR options 1 (per) ±2–3 OD / PP (var.) OTP / I²C (family-dep.) Low–Med. Some Small packages; easy to drop into far-end domains with local WDT.
onsemi NCP300 / NCP301 POR-BOD / µP Supervisor 1 (per) ±2–3 (var. by code) OD / PP (codes) OTP Medium — Classic end-rail detector; many threshold codes; great as fanout bricks.
Microchip MCP131x / MCP132x / MCP1316 / MCP1321 µP Supervisor / WDT / MR 1 (per) ±2–3 (sel.) OD / PP (sel.) OTP / I²C (few) Low–Med. Some (-E/-A) Reset width variants; complements RTC-switchover MCP7931x in subsystems.
NXP VR5510 PMIC / FS26/45/65 SBC PMIC/SBC (integrated supervisor) Multi (SoC-dep.) — (monitored ADC) OD + status pins SPI / PMIC regmap Low (A-grade) Yes (auto) Good for centralized SoC power trees with PG/FAULT signaling.
Melexis MLX8003x / MLX8005x LIN Node SBC (Reset + WDT) Node-centric — (SBC spec) OD + diag. LIN/SBC regs Automotive focus Yes (var.) Great for distributed automotive nodes needing Windowed WDT + Reset.

Migration checklist (pin/behavioral)

  • Match output type (OD/PP). If OD-only, re-pull in destination domain(s).
  • Translate threshold vector: VIT−, VIT+, Vhys, tGLITCH, tDELAY, tRST.
  • Ensure PG aggregation polarity and timing compatibility.
  • Replace PFT with PMIC/SBC event registers if supervisor lacks logging.
  • Re-run Chapter 5 matrix at −40/25/85/105 °C before release.

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BOM Remarks & Procurement Hooks

Outputs & Levels

  • RESET/PG outputs must be open-drain with ≥10 kΩ pull-ups to the host I/O rail unless explicitly approved for push-pull.
  • For cross-domain fanout, re-pull-up in each destination domain or buffer as needed.
  • If push-pull is mandated, all receivers must share the same logic rail and rise-time margins must be verified.
RESET/PG outputs: use OPEN-DRAIN with ≥10 kΩ pull-ups to Host I/O. For cross-domain fanout, re-pull-up in each target domain or buffer. Push-pull only if ALL receivers share the same rail and rise-time margins are validated.

Thresholds & Timing

  • Per-rail window thresholds (VIT−/VIT+) and Vhys must match table values.
  • Blanking (glitch filter) ≥ X µs; Reset pulse width ≥ Y ms.
  • PG aggregation requires a delay chain preserving the dependency order (Core → DDR → IO).
  • Recommended starting points: X=10–50 µs, Y=10–50 ms; refine using your validation matrix.
Per-rail thresholds (VIT-/VIT+) and Vhys: follow table. Glitch blanking ≥ X µs; Reset pulse ≥ Y ms. Start with X=10–50 µs, Y=10–50 ms; finalize per lab results. PG aggregation must preserve Core → DDR → IO dependency via programmable delay chain.

Logging & Cloud Mapper

  • Power-Fail tagging shall be logged before asserting global reset; keep event schema stable.
  • I²C/PMBus: document threshold/blanking/timing registers; version-lock in firmware images.
  • Cross-brand alternatives limited to TI/ST/NXP/Renesas/onsemi/Microchip/Melexis; update the cloud mapper before release.
Log Power-Fail Tag BEFORE global reset; keep event schema stable. I²C/PMBus: document/register-map + checksum; firmware image must be version-locked. Cross-brand alternatives limited to TI/ST/NXP/Renesas/onsemi/Microchip/Melexis; update cloud telemetry mapper and re-run validation before release.
Procurement-ready BOM remark cards Three cards summarizing outputs & levels, thresholds & timing, and logging & cloud-mapper requirements, with a release checklist. BOM Remarks — Summary Cards Outputs & Levels OD preferred; ≥10–47 kΩ pull-ups Re-pull-up / buffer per domain PP only with shared rail + margins Thresholds & Timing Match VIT−/VIT+ and Vhys Blanking ≥ X µs; Reset ≥ Y ms PG delay chain keeps order Logging & Cloud Log PFT before global reset PMBus/I²C regmap version-lock 7-brand only; update mapper Release Checklist • Output type matched (OD/PP) & fanout OK • Thresholds & Vhys per table • t_GLITCH / t_DELAY / t_RST validated • PFT log-before-reset, time-tag aligned • Cloud mapper updated & versioned • Re-run matrix at −40/25/85/105 °C

Frequently Asked Questions

Why use windowed thresholds instead of simple UV?

Windowed thresholds detect both under- and over-voltage while adding hysteresis to resist slow ramps and noise. In multi-rail systems, this prevents chatter that would otherwise ripple through the reset tree. It also lets you tune blanking separately from reset pulse width, improving startup determinism.

How much hysteresis is enough for slow ramps?

Start from 1–2% of the nominal rail, then test with the slowest ramp you expect. Increase hysteresis until you see no chatter at the chosen blanking time. Verify across temperature and load steps; too much hysteresis may mask genuine brown-outs.

Open-drain or push-pull resets?

Prefer open-drain for cross-domain fanout and level compatibility. Use 10–47 kΩ pull-ups to the host I/O rail and validate the rise time against your clock domain. Push-pull is fine only if all receivers share the same rail and timing margins.

How do I set blanking vs reset pulse width?

Blanking filters short disturbances before flagging a fault; reset pulse must be long enough for the slowest clock domain to re-start. Typical starting points: 5–50 µs blanking and 10–50 ms reset pulse, then tune with your slope and PLL lock time.

What is power-fail tagging and why log first?

Power-fail tagging records which rail violated and when. Logging before asserting global reset increases post-mortem visibility and shortens bring-up time. Time-tagging from RTC or a free-running counter avoids ambiguous sequences under cascading faults.

How to aggregate PG without race conditions?

Use an OR tree for “any-bad” with a programmable delay chain that respects dependencies. Add a small RC or digital debounce at the aggregation output. Validate worst-case skew between per-rail PG de-assertions to avoid false releases.

How tight should per-rail accuracy be?

±1–2% is typical for core rails; ±2–3% for I/O. Pick tighter accuracy if your DC/DC tolerance is narrow or if load steps inject ripple. Confirm across temperature; derate thresholds if your bandgap trim drifts near corners.

Can I trim thresholds by firmware only?

Yes, with I²C/PMBus. But lock versions: document register maps, checksum images, and require production tests to read-back the final values. OTP or resistor-set serves as a safe baseline if firmware is not yet ready.

How to avoid false trips from EMI spikes?

Combine small input RC, programmable blanking, and sufficient hysteresis. Route sense lines away from switching nodes and ground-reference the comparator. Validate with injected pulses at 1/5/10/50 µs to bracket your filter design.

What if reset needs to fan out across 1.8/3.3/5V domains?

Keep the source open-drain and re-pull-up in each domain. If receivers require push-pull levels, add a level-shifter or a small buffer. Verify that de-assertion edges meet the slowest domain’s setup time.

How do I test for temperature-driven drift?

Sweep −40 °C to 105 °C while stepping rails near the thresholds; record trip points and chatter. Use the worst-case drift to set final V_hys and blanking margins.

What must procurement check when swapping brands?

Match outputs (OD vs PP), rails count, thresholds accuracy, hysteresis range, blanking, reset width, I²C/PMBus support, temperature grade, and AEC-Q100 where applicable. Update the cloud mapper and re-run the validation matrix before release.

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