Windowed Voltage Supervisor: Hysteresis & Thresholds

Q: How much hysteresis is enough versus ripple and drift?

Use the rule of thumb V_hys_total ≥ α·V_ripple_pp with α≈0.4–0.6, then add drift and measurement margin. Verify with ripple-injection tests and report Trip P95 (mV). If ripple varies widely, keep a conservative floor on V_hys_total and complement with a glitch filter for short, bursty interference.

Q: How do I aggregate multiple PG/RESET lines safely?

Use an Active-OR stage that qualifies each source with a minimum-width filter, then apply per-rail t_DELAY to shape sequencing. Avoid passive wired-OR because it cannot enforce timing. For star fan-outs, list branch-specific delays and domains. Record the policy in the BOM and validation matrix.

Q: How can I migrate across brands without re-tuning the window?

Match the effective parameters: ΔV_window, V_hys_total, t_GLITCH, t_DELAY and keep Open-Drain semantics. Update the telemetry mapper and run a short regression: ripple worst-case, glitch burst, and hot/cold temperature points. Document any residual offset and add it to the P95 budget before release.

What it solves

Slow ramp → false resets

Enable an ignore-on-ramp window and a minimum t_GLITCH so that slow supply rise and short spikes do not trigger RESET.

Ripple/jitter near threshold → chatter

Use total hysteresis V_hys_total sized vs ripple: V_ripple(pp) ≤ α·V_hys_total with α≈0.4–0.6; extend t_GLITCH if needed.

Slow drift (temp/load coupling)

Upper/lower ΔV_window plus DAC fine-trim absorb ref, divider and temperature drift; compute error via RSS budget.

PG aggregation races

Open-Drain outputs with Active-OR and per-rail delay shape clean sequencing; avoid passive wired-OR without timing control.

Cross-domain level conflicts

Default to Open-Drain pulled up to the host domain; only use push-pull when levels are proven compatible.

BOM note (paste-ready): Use windowed supervisor with V_IT−=__V, V_IT+=__V, V_hys_total≥__mV; set t_GLITCH=__µs, t_DELAY=__ms; default RESET/PG as Open-Drain pulled up to host I/O; PG aggregation via Active-OR + per-rail delay.

Architecture & Signal Levels

Functional blocks

Reference → Upper/Lower comparators → Hysteresis network → Output stage (OD/PP)
Settings: Divider (R_top/R_bot) or DAC (I²C/PMBus or internal)
PG goes high only when voltage stays within window for ≥ t_GLITCH
MR (manual reset) requires debounce ≥ C ms (typ. ≥30 ms)

Levels and output policy

Logic domains: 1.8/3.3/5 V; pull Open-Drain up to target domain
Default to Open-Drain (10–100 kΩ pull-up) for cross-domain and fan-out
Use Push-Pull only if levels are 100% compatible (prove VIH/VIL margins)
Divider total resistance: 100–500 kΩ (power vs noise), 0.1% / 25 ppm/°C

Error/Drift budget (RSS)

Compute trip error with RSS: σ_V ≈ √(σ_ref² + σ_Rratio² + σ_temp² + σ_quant²). For divider mode: V_trip = V_ref · R_b/(R_t+R_b). For DAC mode, include LSB (≈0.5·LSB), INL/DNL and temperature of the reference.

Procurement hard rules

RESET/PG = Open-Drain by default; Push-Pull requires level-compatibility report
Record V_hys_total setting and validate across temperature and ripple
Lock DAC code & checksum in NVM; divider ratios meet 0.1%/25 ppm/°C

RESET/PG must be Open-Drain by default; Push-Pull requires a level-compatibility report.
Divider ratios ≥0.1%, ≤25 ppm/°C; DAC code & checksum locked in NVM.
Record and validate V_hys_total vs ripple and temperature; document t_GLITCH/t_DELAY.

Thresholds & Timing

Parameter dictionary

V_IT−, V_IT+: Lower/Upper trip thresholds
ΔV_window = V_IT+ − V_IT−: Window bandwidth
V_hys_total: Total hysteresis across window edges
t_GLITCH(min): Glitch filter time
t_DELAY: Reporting/RESET delay

Rules of thumb

Ripple immunity: V_ripple(pp) ≤ α · V_hys_total, with α≈0.4–0.6.
Slew immunity: t_GLITCH ≥ (t_spike_max + t_sync_err), start at 10/20/50 µs.

Divider path (A)

V_trip = V_ref · R_b/(R_t+R_b), total resistance 100–500 kΩ (power vs noise).
Error RSS: σ_V ≈ √(σ_ref² + σ_Rratio² + σ_temp²) with 0.1% resistors, 25 ppm/°C.

DAC path (B)

Mapping code → V_IT±; include LSB (≈0.5·LSB), INL/DNL and reference tempco.
Leave code steps for temperature trim; lock value & checksum in NVM.

Divider back-calc (example)

Target: 3.3 V rail → V_IT−=3.0 V, V_IT+=3.6 V, V_ref=1.2 V.
R_b/(R_t+R_b) = V_trip/V_ref → choose total 200 kΩ, derive 0.1% values, temp 25 ppm/°C.

DAC quantization impact

If LSB=2 mV, 1 code step shifts V_IT+ by 2 mV; check effect on ΔV_window and V_hys_total and reserve ±N codes for temp trim.

Estimate V_ripple(pp) → set V_hys_total ≥ 1.5×V_ripple(pp).
Back-calc ΔV_window from tolerance & temp (≥3σ budget).
Choose t_GLITCH = 10/20/50 µs based on spike spectrum.
Enable ignore-on-ramp if slow ramp/brown-in/out observed.
Close with slew + ripple + glitch + temperature validation.

Integration & Sequencing

PG/EN policy

Entering the valid window and staying for ≥ t_GLITCH raises PG. Aggregate PG via Active-OR, shape with per-rail delay, then enable downstream EN. On exit, pull PG low or latch fault; use back-off for auto-retry domains.

Cross-domain & fan-out

Default Open-Drain pulled up to the system-control domain; Push-Pull only for same-domain and proven VIH/VIL margins. For star fan-out, assign t_DELAY per branch; for tree fan-out, account for cumulative stage delays.

Edge cases

Ignore-on-ramp during power-up
Pre-biased starts require second confirmation
Brown-in/out handled by V_hys_total + t_GLITCH
Avoid over-wide window; prefer hysteresis + filtering + t_GLITCH

RESET/PG = Open-Drain pulled up to the control domain; Push-Pull requires level-compatibility report.
PG aggregation via Active-OR + Delay chain; no passive wired-OR.
Star fan-out: specify t_DELAY per branch; Tree: list cumulative stage delay.
Enable ignore-on-ramp; document t_GLITCH / t_DELAY / back-off in validation & BOM notes.

Validation

Coverage matrix

Slew scan: 0.05/0.5/5/10 V·ms⁻¹ → mis-trigger rate & trip-offset histograms
Ripple injection: 10/100/300/1000 kHz × 20–200 mVpp (sine + random jitter)
Glitch injection: 5/10/20/50 µs (single/burst) → false-pos/false-neg/PG jitter
Temperature: −40/25/85/125 °C → V_IT± drift, ΔV_window change, reset width
Edge cases: pre-bias start, brown-in/out, cross-domain load steps

Pass criteria

Chatter = 0 at worst-case ripple; single clean RESET/PG transitions
Trip offsets within the design 3σ budget across all temperature points
PG→EN ordering correct with configured t_DELAY (no cross/retrograde)
With ignore-on-ramp active, no decisions during power-up ramp

Validation Records (Template + Examples)

Trip offset = measured trip − target (mV), report P95。Chatter = unintended PG/RESET toggles。 All RESET/PG are Open-Drain to control domain unless stated.

Pass rule: Chatter=0；Trip P95 ≤ design 3σ；PG→EN order correct with configured t_DELAY；no decisions during ramp（ignore-on-ramp ON）。

Test ID	Scenario	Setup Vref / Divider-or-DAC / t_GLITCH / t_DELAY / V_hys_total / ΔV_window	Measured V_IT− / V_IT+ / PG delay / Reset width / Trip P95 (mV)	Events chatter / FP / FN	Result	Notes
VAL-001	Slew 0.5 V·ms⁻¹	Vref=1.2 V; Divider; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=60 mV; ΔV_window=600 mV	V_IT−=3.00 V; V_IT+=3.60 V; PG=8.1 ms; Reset=30 ms; Trip P95=7 mV	chatter=0; FP=0; FN=0	Pass	BW=100 kHz; 4-wire sense
VAL-012	Ripple 300 kHz @ 200 mVpp	Vref=1.2 V; DAC code=0x78; t_GLITCH=50 µs; t_DELAY=10 ms; V_hys_total=120 mV; ΔV_window=500 mV	V_IT−=4.50 V; V_IT+=5.00 V; PG=10.2 ms; Reset=28 ms; Trip P95=9 mV	chatter=0; FP=0; FN=0	Pass	V_ripple(pp) ≤ 0.6·V_hys_total satisfied
VAL-021	Glitch 10 µs (burst 5×)	Divider; t_GLITCH=20 µs; t_DELAY=6 ms; V_hys_total=80 mV; ΔV_window=400 mV	V_IT−=2.95 V; V_IT+=3.55 V; PG=6.2 ms; Reset=24 ms; Trip P95=6 mV	chatter=0; FP=0; FN=0	Pass	t_GLITCH ≥ spike+sync margin
VAL-033	Temp +125 °C	DAC 0x6E; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=70 mV; ΔV_window=520 mV	V_IT−=3.02 V; V_IT+=3.60 V; PG=8.0 ms; Reset=30 ms; Trip P95=10 mV	chatter=0; FP=0; FN=0	Pass	Thermal soak ≥20 min before run
VAL-034	Temp −40 °C	DAC 0x6E; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=70 mV; ΔV_window=520 mV	V_IT−=2.98 V; V_IT+=3.58 V; PG=8.3 ms; Reset=31 ms; Trip P95=11 mV	chatter=0; FP=0; FN=0	Pass	Tempco tracked by DAC trim reserve
VAL-041	Pre-bias start @ 0.8·V_nom	Divider; ignore-on-ramp=ON; t_GLITCH=20 µs; t_DELAY=10 ms; V_hys_total=90 mV; ΔV_window=450 mV	V_IT−=4.05 V; V_IT+=4.50 V; PG=10.1 ms; Reset=28 ms; Trip P95=8 mV	chatter=0; FP=0; FN=0	Pass	Two-phase confirm before PG raise
VAL-052	Brown-in/out + Cross-domain step	DAC 0x72; t_GLITCH=50 µs; t_DELAY=12 ms; V_hys_total=120 mV; ΔV_window=550 mV	V_IT−=11.0 V; V_IT+=11.8 V; PG=12.4 ms; Reset=35 ms; Trip P95=12 mV	chatter=0; FP=0; FN=0	Pass	Star fan-out: per-branch t_DELAY list; load step 20% @ 1 kHz

Copy as CSV

Test ID,Scenario,Setup (Vref/Divider/DAC, t_GLITCH, t_DELAY, V_hys_total, ΔV_window),Measured (V_IT−, V_IT+, PG delay, Reset width, Trip P95 mV),Events (chatter, FP, FN),Result,Notes
VAL-001,Slew 0.5 V·ms⁻¹,"Vref=1.2 V; Divider; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=60 mV; ΔV_window=600 mV","3.00 V; 3.60 V; 8.1 ms; 30 ms; 7",0;0;0,Pass,"BW=100 kHz; 4-wire"
VAL-012,Ripple 300 kHz @ 200 mVpp,"Vref=1.2 V; DAC=0x78; t_GLITCH=50 µs; t_DELAY=10 ms; V_hys_total=120 mV; ΔV_window=500 mV","4.50 V; 5.00 V; 10.2 ms; 28 ms; 9",0;0;0,Pass,"V_ripple ≤ 0.6·V_hys_total"
VAL-021,Glitch 10 µs (burst 5×),"Divider; t_GLITCH=20 µs; t_DELAY=6 ms; V_hys_total=80 mV; ΔV_window=400 mV","2.95 V; 3.55 V; 6.2 ms; 24 ms; 6",0;0;0,Pass,"t_GLITCH ≥ spike+sync"
VAL-033,Temp +125 °C,"DAC=0x6E; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=70 mV; ΔV_window=520 mV","3.02 V; 3.60 V; 8.0 ms; 30 ms; 10",0;0;0,Pass,"Thermal soak ≥20 min"
VAL-034,Temp −40 °C,"DAC=0x6E; t_GLITCH=20 µs; t_DELAY=8 ms; V_hys_total=70 mV; ΔV_window=520 mV","2.98 V; 3.58 V; 8.3 ms; 31 ms; 11",0;0;0,Pass,"DAC trim reserve"
VAL-041,Pre-bias start @ 0.8·V_nom,"Divider; ignore-on-ramp=ON; t_GLITCH=20 µs; t_DELAY=10 ms; V_hys_total=90 mV; ΔV_window=450 mV","4.05 V; 4.50 V; 10.1 ms; 28 ms; 8",0;0;0,Pass,"Two-phase confirm"
VAL-052,Brown-in/out + Cross-domain step,"DAC=0x72; t_GLITCH=50 µs; t_DELAY=12 ms; V_hys_total=120 mV; ΔV_window=550 mV","11.0 V; 11.8 V; 12.4 ms; 35 ms; 12",0;0;0,Pass,"Star fan-out; step 20%"

Cross-Brand IC Mapping

Priority: Functional equivalence (true window + hysteresis + glitch/delay) > timing/threshold tunability > Pin-to-Pin > AEC-Q100 availability. Use Open-Drain to the control domain by default; Push-Pull only with proven VIH/VIL margins documented in BOM notes.

TI

TPS3702: Native window OV/UV supervision, tight thresholds, internal hysteresis & glitch immunity for narrow-margin rails.
TPS3703 / TPS3703-Q1: Window + configurable reset delay; AEC-Q qualified variant for automotive multi-rail sequencing.
TPS3890 / TPS3895: Precision supervisors; pair two thresholds (or with resistor/DAC) to realize a tuned window when native window parts are constrained.

ST

STM706/707/708: PFI/PFO comparator path allows a practical “window” using external divider for the second edge; multiple reset widths.
STM813L / STM811 / STM100x: Multi-level reset thresholds; combine PFI for early-warning + window behavior.

NXP

MC33910 (SBC platform): Integrated multi-rail supervision with window/PG policies inside the system basis chip.
PCF8523 / PCF8563 (RTC): Use RTC domain supervision + timestamping for brown-in/out correlation alongside a divider/DAC window on main rails.

Renesas

ISL88001/002/003: Ultra-low Iq precision supervisors; implement a two-edge window using dual thresholds or an added comparator while keeping RESET semantics.
ISL88021/022: Wider threshold options and reset-delay selections for sequencing with aggregated PG.

onsemi

NCP300 / NCP301 (NCV for auto): High-accuracy single-threshold supervisors; realize a window with a companion threshold/divider and keep Open-Drain PG/RESET.
NCP308 / NCP31x family: Additional delay/hysteresis options useful for chatter-free sequencing.

Microchip

MCP1316/MCP1318: Precision reset supervisors with selectable delay; pair two thresholds (or use a small DAC) to form a controllable window.
MCP1321/MCP1322: Extended reset timing options; Open-Drain variants simplify cross-domain pull-up.

Melexis

For automotive ECUs built on Melexis platforms, use the platform’s supply/supervision path when available (within SBC/MCU subsystems), and implement the second edge via a divider/DAC to realize a window. If a standalone window supervisor is not present in the current catalog, select a cross-brand device above and maintain Open-Drain semantics to the control domain.

Keep PG/RESET as Open-Drain and pull up to the system-control domain (10–100 kΩ).
When migrating A→B, preserve ΔV_window / V_hys_total / t_GLITCH / t_DELAY equivalence and update the validation matrix.
Add BOM notes for ignore-on-ramp default-ON and per-branch t_DELAY in star fan-out.

BOM Remarks & Procurement Hooks

Use a windowed supervisor with V_IT−=__V, V_IT+=__V, total hysteresis ≥ __mV; validate under ±__mV ripple and __V/ms slew.
RESET output must be Open-Drain with ≥10 kΩ pull-up to host I/O; push-pull only if level-compatible.
t_GLITCH ≥ __µs; reporting delay t_DELAY=__ms; enable ramp-ignore during power-up.
If DAC-set thresholds, lock code & checksum in NVM; divider ratios ≥0.1% / 25 ppm/°C.
Cross-brand alternatives limited to TI/ST/NXP/Renesas/onsemi/Microchip/Melexis; update telemetry mapper before release.
PG aggregation must be Active-OR + per-rail delay; no wired-OR without timing control.

Thresholds & Hysteresis

☐ V_IT−=__V ☐ V_IT+=__V ☐ V_hys_total ≥ __mV ☐ Ripple ±__mV ☐ Slew __V/ms

Output & Levels

☐ RESET=Open-Drain ☐ Pull-up ≥10 kΩ to control domain ☐ Push-Pull only if VIH/VIL proven

Timing & Integration

☐ t_GLITCH ≥ __µs ☐ t_DELAY=__ms ☐ Ramp-ignore=ON ☐ Active-OR PG + per-rail delay

Copy as CSV / JSON

Window,VIT_minus_V,VIT_plus_V,Vhys_min_mV,Ripple_pp_mV,Slew_V_per_ms,tGLITCH_us,tDELAY_ms,Output,Pullup_ohms,SetMethod,Divider_ppm,Brands,PG_Aggregation
Windowed Supervisor,__ ,__ ,__ ,__ ,__ ,__ ,__ ,Open-Drain,10000,DAC-or-Divider,25000,"TI;ST;NXP;Renesas;onsemi;Microchip;Melexis","Active-OR + per-rail delay"

{
  "window": "Windowed Supervisor",
  "vit_minus_v": "__",
  "vit_plus_v": "__",
  "vhys_min_mv": "__",
  "ripple_pp_mv": "__",
  "slew_v_per_ms": "__",
  "t_glitch_us": "__",
  "t_delay_ms": "__",
  "output": "Open-Drain",
  "pullup_ohms": 10000,
  "set_method": "DAC-or-Divider",
  "divider_ppm": 25000,
  "brands": ["TI","ST","NXP","Renesas","onsemi","Microchip","Melexis"],
  "pg_aggregation": "Active-OR + per-rail delay"
}

Frequently Asked Questions

Why choose a windowed supervisor over a single UV trip?

A single undervoltage threshold can chatter when ripple or drift hovers near its trip point. A windowed supervisor monitors both lower and upper bounds and adds total hysteresis, filtering near-limit noise and slow drift. The result is fewer false resets and cleaner PG behavior on narrow-margin rails, especially during dynamic loads.

How much hysteresis is enough versus ripple and drift?

Use the rule of thumb V_hys_total ≥ α·V_ripple_pp with α≈0.4–0.6, then add drift and measurement margin. Verify with ripple-injection tests and report Trip P95 (mV). If ripple varies widely, keep a conservative floor on V_hys_total and complement with a glitch filter for short, bursty interference.

Wide window or longer glitch filter—how should I trade off?

Widening the window mainly protects against low-frequency ripple and slow drift but increases tolerance. Increasing t_GLITCH improves immunity to brief spikes but adds reporting latency. Map the disturbance spectrum: low-frequency noise → favor hysteresis; high-frequency spikes → favor t_GLITCH. Keep latency budgeted so PG→EN sequencing still meets timing.

How do I compute threshold error with divider tolerance and temp-co?

Model the actual threshold as V_ref × ratio ± RSS of contributors: reference error, resistor ratio tolerance, temperature coefficient, and DAC quantization if present. Use three-sigma assumptions, compute P95 trip offset in mV, and verify at −40/25/85/125 °C. Reserve a small DAC trim range to re-center across temperature.

When should I move from resistor-set to DAC-set thresholds?

Choose DAC-set thresholds when production trim, field re-centering, or multiple platform variants require programmable windows. Lock code and checksum in NVM and document allowed trim steps for service. For fixed builds with tight logistics, precision divider networks remain simpler—budget temp-co and validate at all operating temperatures.

Can push-pull RESET break level compatibility across domains?

Yes. Push-pull assumes matching VIH/VIL to the target logic domain. Crossing domains may violate margins or back-drive rails during brown-in/out. Default to Open-Drain and pull up to the control domain (10–100 kΩ). Use push-pull only when margins are proven and documented in the BOM, with regression validation.

How do I aggregate multiple PG/RESET lines safely?

Use an Active-OR stage that qualifies each source with a minimum-width filter, then apply per-rail t_DELAY to shape sequencing. Avoid passive wired-OR because it cannot enforce timing. For star fan-outs, list branch-specific delays and domains. Record the policy in the BOM and validation matrix.

How do I validate very slow ramps and pre-biased starts?

Enable ramp-ignore so no decisions occur during the rise. Sweep slew from 0.05 to 10 V/ms and include a pre-bias start around 0.8×V_nom. Acceptance is chatter=0, correct PG ordering with configured delays, and trip offsets within the three-sigma budget across temperature. Log scope bandwidth and sampling.

What proves immunity to burst noise and short spikes?

Run glitch tests with 5–50 µs single pulses and short bursts. Passing means chatter=0 and no false positives or negatives when t_GLITCH ≥ spike duration + synchronization error. Include worst-case ripple during testing to check interaction. Report results as Trip P95 and event counts per run.

How can I migrate across brands without re-tuning the window?

Match the effective parameters: ΔV_window, V_hys_total, t_GLITCH, t_DELAY and keep Open-Drain semantics. Update the telemetry mapper and run a short regression: ripple worst-case, glitch burst, and hot/cold temperature points. Document any residual offset and add it to the P95 budget before release.

Why does chatter sometimes occur only near the upper threshold?

Load-coupled ripple and a faster rising-edge slope can make the upper comparator more sensitive. If total hysteresis is marginal, the window edge may be revisited repeatedly. Increase hysteresis or shape t_GLITCH to match the disturbance spectrum. Check PG coupling and fan-out delays for feedback paths.

Which BOM notes prevent procurement from choosing the wrong part?

Lock Open-Drain RESET with pull-up to the control domain, state minimum t_GLITCH and fixed t_DELAY, and specify either DAC code with checksum or divider tolerances (≥0.1% / 25 ppm/°C). Restrict alternatives to the seven brands and require telemetry-mapper updates plus regression before approval.

Windowed Voltage Supervisor — Upper/Lower Windows & Hysteresis