Clock Monitor & Missing-Pulse: Drift & Backup Switch

Q: Missing-pulse vs frequency window — which avoids false alarms better?

Missing-pulse detection is strongest for Stop or gated clocks because it watches for absent edges. A frequency window is better for Slow/Fast/Runaway drift. Use both, each with its own debounce. Size the window with hysteresis H_f (ppm), and set the missing-pulse timeout t_mp = k·T_clk to cover 95% jitter plus margin.

Q: How do I set hysteresis and debounce to prevent flicker?

Combine frequency hysteresis and sample-based qualification. Start with H_f ≥ 2×(tolerance + temp drift + quantization). Require N consecutive in-range samples (typically 3–5) before declaring stable. Add a lockback window T_lockback after recovery to suppress rapid re-entry. Keep missing-pulse debounce independent so brief jitter bursts do not force a switchback.

Q: How do I control glitches and duty-cycle error during backup switchover?

Use a glitch-free MUX or a zero-delay device and measure peak glitch time t_glt. Limit t_glt with phase-aligned switching, then correct residual duty error δ_duty using a one-shot shaper or duty corrector. Define acceptance: t_glt ≤ Y ns and δ_duty ≤ Z%. For fast interfaces, buffer or divide after the MUX to relax downstream timing.

Q: How do I log who triggered the switch (Stop/Drift/Runaway) for service analysis?

Record a minimal, portable JSON entry: {event_id, tstamp_ms, mode, f_meas_ppm, action, switchover_count, stop_count, drift_count, fw_ver}. Add clk_src(active) if available. The mode encodes the trigger class; counters show history. Include lot, board_id, and tempC when present so field returns can be traced to production conditions and component lots.

Q: What peripherals are most sensitive when backup accuracy is weaker?

Protocols with tight timing or eye-diagram budgets—USB, Ethernet, video, high-speed ADC/DAC sampling—are most sensitive to ppm error and jitter. UART and many SPI links are more tolerant. If backup tolerance is limited, degrade first: reduce link rates, pause isochronous paths, or switch noncritical blocks to derived clocks until the primary reference returns stable.

Q: With the watchdog, should I degrade operation or reset immediately?

Gate watchdog feeds under FAULT_CLK to avoid “good-dog on bad clock.” Prefer staged response: degrade and switch to backup first, then reset only when stop_count exceeds N or frequency drops below f_min_safe. This preserves logs and telemetry for root cause while protecting the system when timing falls outside safe operating limits.

Q: How should thresholds adapt with temperature-induced slow drift?

Characterize enter/exit points across −40…125 °C, then apply temperature-aware limits. A simple model is f_low/high(T) = f_nom·(1 ± (α0 + kT)). During cold start, widen H_f and reduce N to avoid premature trips, then tighten after stability. For production, a two-segment LUT or linear slope per grade is often sufficient and robust.

Q: For gated-low/high lockups, how do I choose the timeout limit?

Identify the longest legitimate gate interval from power-save states and DMA bursts, then set the missing-pulse timeout above it with margin. A practical start is t_mp ≥ 1.2×t_gate_max_legit. Interlock with system mode so deep-sleep gating is whitelisted, while unexpected continuous low or high forces a fault path and optional switchover.

Q: How do I avoid false trips during slow crystal startup at power-on?

Use a cold-start blanking window t_blank = t_bak_start + margin to ignore early edges. During t_blank, relax frequency thresholds and hysteresis, then progressively tighten as amplitude and frequency settle. Qualify with N consecutive stable samples before allowing switchover or watchdog gating to resume normal enforcement in steady-state operation.

Q: What are the minimum factory probes and scripts for production test?

Provide probes on CLK_IN, CLK_BAK, MUX_OUT, PG/FAULT/IRQ, and WDT_GATE. Keep three reusable scripts: stop injection, ±Δf scan, and jitter-burst. Record the minimal JSON per unit with t_detect, t_sw, t_glt, δ_duty, and counters. Use AQL sampling across cold/room/hot to ensure drift margins and switching behavior remain within limits.

What It Solves

Map real failure modes to observable symptoms, then to detection capabilities and response policy. The closed loop is: monitor → qualify → degrade/switch → recutover. This page focuses on clock failures and intentionally avoids overlap with voltage supervisors, POR/BOD, and general watchdog topics.

Failure Modes

Stop (oscillation stops)
Slow (frequency drifts down)
Fast (frequency drifts up)
Runaway (M×, PLL lost lock)
Gated-Low / Gated-High (clock gating stuck)
Jitter-Burst (short bursts of large jitter)

Observable Symptoms

UART/SPI/I²C timeouts or framing errors
ADC/DSP sampling de-sync, video/audio artifacts
Ethernet/USB link timeouts or renegotiation
System timebase drift, watchdog false resets

Detection Capabilities

Missing-Pulse Window — sensitive to Stop/Gated
Frequency Window + Hysteresis — Slow/Fast/Runaway
Period Counter — high-resolution frequency error
Δφ Accumulator — distinguishes chronic drift vs. transient jitter

Response Policy

Degrade: limit peripherals / reduce frequency
Switch: auto switchover to backup clock
Reset only if f < f_min_safe or stop_count exceeds threshold
Recutover: return to main clock after N stable samples & low jitter score

Unified parameters: f_nom, α (ppm), H_f (ppm), t_mp (µs), N_samples, window (ms), jitter_95 (ns), t_sw (ms), t_glt (ns), f_min_safe.

Detection Methods

Provide executable thresholding with clear hysteresis and debounce/qualification. Balance resolution vs. response delay and govern false alarms vs. missed detections. Apply a cold-start blanking window to avoid spurious events during crystal startup.

Missing-Pulse Window

Threshold: t_mp = k × T_clk, where T_clk = 1 / f_nom. Choose k ≥ jitter_95_ratio + safety_margin. Highly sensitive to Stop and Gated.

Small window → false alarms on jitter spikes
Large window → miss slow-to-stop evolution
Recommend logging stop_count for service analytics

Frequency Window + Hysteresis

Limits: f_low = f_nom(1−α), f_high = f_nom(1+α); hysteresis H_f in ppm. Budget α from crystal tolerance, temp drift, jitter component, and measurement quantization.

Hysteresis separates enter/exit thresholds to suppress flicker
Window length sets resolution vs. response delay
Record f_meas_ppm for threshold regression

Period Counter

Resolution: Δf ≈ f_nom / N_cycles. Longer averaging (larger N_cycles) improves resolution but increases response delay. Validate the enter/exit symmetry, especially near window edges.

Choose N_cycles by the fastest fault you must catch
Use moving-average or median to suppress outliers

Δφ Accumulator (Phase Drift)

Robust to chronic drift: Δφ_accum = Σ(φ_meas − φ_ref); trigger when |Δφ| > φ_thr. Run in parallel with frequency windowing to separate slow drift from bursty jitter.

Choose φ_thr from system timing limits
Rate-limit events to avoid log storms

Debounce & Qualification

Require N consecutive samples to assert alarm/switch. Add cold-start blanking t_blank. Use moving average or median filters for jitter bursts.

Track “qualified/total samples” for threshold tuning
Document N_samples and window in the BOM remark

Key parameters: f_nom, α (ppm), H_f (ppm), t_mp (µs), N_samples, window (ms), jitter_95 (ns).

Backup Clock Switchover

Define Auto / Forced / Latched switchover modes, time budget, and glitch/duty correction; provide a robust recutover method. The total switchover time is t_sw = t_detect + t_qual + t_mux + t_dutyfix. Keep t_sw within peripheral tolerance; if not, degrade first.

Backup Sources

Internal RC — fast start (t_bak_start small), moderate tolerance (f_bak_tol large), higher jitter.
External XO2 — slower start, tighter f_bak_tol, best for protocol timing.
PLL ÷N — inherits upstream stability; ensure lock robustness and drift bounds.

Specify in BOM: f_bak_tol (ppm/%), t_bak_start (ms), jitter and duty specs, availability at cold start.

Switch Modes

Auto — on threshold violation; t_sw budget = detect + qualify + MUX + duty-fix.
Forced — MCU register forces MUX; log reason code, require privilege.
Latched — after switching, a manual clear is required before any recutover.

Gate external peripherals if t_sw cannot satisfy their tolerance window; degrade first, then switch.

Glitch & Duty Control

Glitch limit t_glt_max (ns); add one-shot shaper if MUX causes runt pulses.
Duty correction — maintain ~45–55%; cap δ_duty_max.
CDC — two-flop synchronizers / handshakes across clock domains.

Recutover Policy

N stable samples, jitter score < threshold, stop_count not increasing.
After recutover, enforce lockout t_lockout to prevent flicker.
On backup clock, limit or suspend timing-critical I/O.

Validation & Metrics

Log t_sw_total, t_glt_peak, duty error δ_duty, event counters.
Stress tests: temperature, vibration, injected jitter, frequency steps.
ATE scripts: stop/restore, ±Δf scan, burst jitter.

Unified parameters: t_detect, t_qual, t_mux, t_dutyfix, t_sw (ms), t_glt_max (ns), δ_duty_max (%), f_bak_tol (ppm/%), t_bak_start (ms), N_recutover, t_lockout.

Reset / IRQ / PG Semantics

Define signal semantics and interlocks so degrade/switch/reset are traceable without watchdog misuse under bad clocks. Keep clock PG semantics distinct from power PG. Prefer OD outputs to avoid back-power; allow polarity configuration.

Signals & Polarities

PG_CLK — clock health (OK/recutover-ready), active-high.
FAULT_CLK — latched clock fault, active-low recommended.
IRQ_CLK — maskable interrupt for Stop/Drift/Runaway/Gated.
Outputs: OD preferred (no back-power); PP optional; polarity configurable.

Interlocks

FAULT_CLK↓ → gate WDT_FEED (optional) to prevent false feeds.
PG_CLK↑ & N stable samples → allow recutover.
stop_count > N_stop → assert RESET_REQ to SoC.

Power PG semantics remain independent; combine via Reset Tree logic if needed.

State Machine

OK → DEGRADE → SWITCHED → RECUTOVER → OK; severe violations (f < f_min_safe or Stop bursts) assert RESET_REQ.

RECUTOVER imposes a lockout to avoid flicker.
SWITCHED implies limited I/O budgets under backup clock.

Event Classes & Logging

Stop / Drift / Runaway / Gated (severity + coalesced counts).
Min log set: {event_id, tstamp_ms, mode, f_meas_ppm, action, switchover_count, stop_count, drift_count}
Rate-limit and de-duplicate to avoid log storms.

Validation

Bad-clock injection + WDT gate check (no false feeds).
OD/PP & polarity regression on ATE; cross-brand consistency.
PG recovery → recutover → lockout stability verification.

Unified parameters: N_stop, N_stable, WDT_FEED_GATE, IRQ_polarity, Output_type (OD/PP), Log_depth.

Design & Validation

Provide executable timing/accuracy budgets and reusable test scripts, so the same method works from the lab to the factory line. Record a minimal, machine-readable event schema for drift/stop and switchover.

Timing & Accuracy Budgets

Detection delay (approx.): t_detect ≈ window_len × sample_period
Total switchover: t_sw_total = t_detect + t_qual + t_mux + t_dutyfix
Constraint: t_sw_total ≤ t_sw_max (derived from the most timing-sensitive peripheral)
Frequency window: f_low = f_nom(1−α), f_high = f_nom(1+α) with hysteresis H_f (ppm)
Budget α from: tolerance + temp drift + jitter + measurement quantization

Reliability: Temp / Vibration / Noise

Temp sweep −40…125 °C: record enter/exit thresholds & stop points; regress vs. temperature
Vibration/solder stress: reproduce intermittent stop via fixture and gated disconnects
Phase-noise & burst jitter injection: bound false-alarm rate under noisy references

Test Scripts (copy-ready)

Stop Injection: gate main clock low / crystal open; verify missing-pulse alarm & stop_count++
Δf Scan: inject ±Δf steps from a generator; record entry/exit vs. f_low/f_high
Jitter Burst: superimpose wideband noise + burst mode; collect qualified samples and false-alarm stats
Switchover: measure t_mux, peak glitch t_glt_peak, duty error δ_duty

Pass/Fail & Logging

Pass if t_sw_total ≤ t_sw_max, t_glt_peak ≤ t_glt_max, δ_duty ≤ δ_duty_max
Log minimal set: {event_id, tstamp_ms, mode, f_meas_ppm, action, t_detect, t_sw_total, t_glt_peak, δ_duty, stop_count, drift_count}
Factory sampling plan: AQL-driven, include cold/room/hot corners

Small-Batch Procurement Hooks

Put non-negotiable parameters into the BOM remarks, and provide a minimum cross-brand validation so small-batch builds stay safe under substitutions.

BOM Remarks (copy-paste)

“Clock supervisor must support missing-pulse & frequency-window with hysteresis; event counter & PG/FAULT/IRQ required; t_sw ≤ X ms, t_glt ≤ Y ns.
OD outputs preferred to avoid back-power; IRQ polarity configurable.
Only within TI / ST / NXP / Renesas / onsemi / Microchip / Melexis; cross-brand migration requires updating cloud mapping first.”

Electrical

IO polarity/level/output type (OD/PP)
Presence of event counters & fault latches
PG/FAULT/IRQ pin behavior under backup clock

Timing

t_detect, t_sw, t_glt, t_bak_start vs. limits
Duty error after switchover (δ_duty)
Recutover stability window & lockout

Environment

Temp regression (−40…125 °C)
Jitter tolerance with burst profile
Intermittent stop reproduction under vibration

Recording

Unify fields with Chapter 5 minimal JSON
Include build metadata: board_id, lot, tempC
Attach pass/fail bands per t_sw / t_glt / δ_duty

Concrete Parts (by brand) & Selection Rationale

Renesas (IDT): ICS580-01 / ICS581-01/02

Glitch-free clock MUX with clock-present detect; 02 variant supports auto-timed switchover. Use as the primary drop-in for systems needing detect → auto/forced switch with minimal retime work.

Microchip: ZL30252 / ZL30253 (DPLL-based jitter cleaners)

Monitor multiple references, provide auto/commanded reference switch with holdover; rich status/counters ease logging and cloud mapping. Preferred for comms/precision timing where drift+holdover matters.

Texas Instruments: LMK00304 (fanout/buffer, ref select)

Low-jitter fanout with flexible input selection. Combine with system-level missing-pulse/frequency windowing for robust switchover; good fit for high-speed domains (SerDes, ADC clocks).

onsemi: NB3N3020 / NB3N3002 / NB3N5573

Generators/multipliers at standard Ethernet/PCIe rates; pair with a glitch-free MUX and your supervisor logic to achieve detect-and-switch with defined jitter targets.

NXP: PCF8523 (RTC with supply switchover)

Supports main/backup supply switchover for timekeeping continuity. Use alongside clock MUX/supervisor to preserve timebase/logging during outages (system-level solution).

STMicroelectronics: System-level combo

Many designs rely on MCU CSS (clock security system) plus a glitch-free MUX/buffer. Record CSS thresholds and pair with external supervisor policy for consistent cross-brand behavior.

Melexis: (system integration note)

Typically integrated for automotive sensing/actuation; use in combination with above clock supervisors/MUXes. Note system-level validation for AEC-Q scenarios.

Selection Checklist (copy-paste)

Native clock-present/LOS detect? Auto/forced switchover? Glitch-free/zero-delay?
Document t_mux, t_glt_max, δ_duty_max; ensure application notes exist
EVM/driver availability; AEC-Q options if automotive
Pin/behavior compatibility for migration; cloud mapping updated before substitution

Cross-Brand Alternatives

Dimensional mapping to prevent mis-substitution (e.g., voltage supervisors vs. clock supervisors). Each card concludes with equivalence / threshold change / IO change. Do not mix in pure voltage supervisors.

Function Stack: Missing-Pulse / Freq-Window / Event Counter / Backup Ctrl / IRQ Interface: OD/PP · Polarity · PG/FAULT semantics Timing: t_detect · t_sw · t_glt · f_bak_tol · t_bak_start Reliability: AEC-Q100 · Temp grade · ESD Package/Pin: pin-compat · pull-ups · MUX/SEL pins

Renesas (IDT)

ICS580-01, ICS581-01/02 — glitch-free/zero-delay clock MUX with clock-present detect (581-02 adds auto-timed switchover).

Function: Backup Ctrl ✓ · Missing-Pulse (present detect) ✓ · Event Counter via MCU
Interface: OD/PP by variant; polarity configurable; PG/FAULT via GPIO mapping
Timing: low t_glt, short t_mux; verify t_sw vs. peripherals
Reliability: wide temp variants; check ESD class per package
Pin: MUX/SEL pins; pull-ups per mode

Conclusion: Equivalent (most cases). Add MCU counters if needed.

Microchip (Microsemi)

ZL30252 / ZL30253 (DPLL jitter cleaners), ZL30367 (timing w/ holdover) — multi-ref monitor, auto/commanded switchover, LOS/freq monitor.

Function: Missing-Pulse/Freq Window ✓ · Event/Status ✓ · Backup Ctrl ✓
Interface: rich status/IRQ; OD/PP and polarity options
Timing: hitless/low-glitch paths; check t_sw vs. profile
Reliability: telecom-grade; holdover stability
Pin: ref input matrix; care SEL/CTRL pins

Conclusion: Equivalent+ (often stronger). Usually only threshold tuning.

Texas Instruments

LMK00304 (low-jitter fanout/buffer, source select). Combine with system-level missing-pulse/freq window for robust switchover.

Function: Backup select ✓ · Use MCU for counters/windowing
Interface: OD/PP per output; polarity config via logic
Timing: excellent jitter; verify t_mux/t_glt
Reliability: ample temp/package options
Pin: fanout pins; SEL/pull mode

Conclusion: Threshold/IO changes (monitor in system layer).

onsemi

NB3N3020 / NB3N3002 / NB3N5573 (generators/multipliers). Pair with glitch-free MUX + supervisor logic.

Function: ref generation; system adds Missing-Pulse/Freq Window
Interface: verify logic levels & OD/PP needs
Timing: validate t_sw/t_glt at target rates
Reliability: common industry footprints
Pin: SEL/MODE; pull-ups

Conclusion: Threshold/IO changes (system-level monitor).

NXP

PCF8523 (RTC) for power-backup timekeeping; use with external MUX/supervisor to preserve timestamps through outages.

Function: not a clock MUX; complements logging/telemetry
Interface: I²C + alarm IRQ
Timing: backup switchover at supply domain
Reliability: consumer/industrial variants
Pin: battery pin; IRQ

Conclusion: System combo (keep time/logs, external MUX handles switch).

STMicroelectronics

Common practice: MCU CSS (Clock Security System) + external glitch-free MUX/buffer. CSS detects stop/runaway; MUX performs switch.

Function: Missing-Pulse via CSS; Backup Ctrl via MUX
Interface: map CSS flags to PG/FAULT/IRQ semantics
Timing: qualify N samples; verify t_sw
Reliability: grade per MCU/package
Pin: MUX SEL; pull-ups

Conclusion: Equivalent (system) · likely threshold/IO changes.

Melexis

No discrete clock-supervisor/MUX line; integrate with Renesas/Microchip/TI parts for automotive designs (AEC-Q target).

Function: via partner device
Interface: follow OD/PP & polarity rules from the chosen MUX/supervisor
Timing: test full t_detect/t_sw/t_glt path
Reliability: document AEC-Q flow
Pin: wiring per chosen supervisor

Conclusion: System combo; validate across temp/ESD.

Risk Notice: Do not treat voltage supervisors as clock supervisors. Only consider devices with clock presence/LOS, frequency windowing, or glitch-free switching in scope.

Telemetry & Test Points

Define a minimal, brand-agnostic event schema and throttling rules; list board-level test points that guarantee reproducible diagnostics from lab to line.

Minimal Event Schema

Use the same fields for all brands; add optional metadata only when needed.

{ "event_id": "clk.stop|clk.drift|clk.runaway|clk.gated",
  "tstamp_ms": 12345678,
  "mode": "stop|drift|runaway|gated",
  "f_meas_ppm": -145,
  "action": "degrade|switch|reset",
  "switchover_count": 3,
  "stop_count": 5,
  "drift_count": 14,
  "fw_ver": "1.2.7" }

Optional: board_id, lot, tempC, vdd, clk_src

Throttle & De-dup

Merge window T_merge: coalesce same-type events; report first/last only
Rate limit R_max: per-severity buckets; drop lowest priority on overflow
De-dup key: {mode, action, clk_src} + bucketed f_meas_ppm
Power-loss hardening: ring buffer + replay flag

Board Test Points

CLK_IN (main), CLK_BAK (backup), MUX_OUT (post-switch)
PG / FAULT / IRQ (clock health semantics)
WDT_GATE (watchdog feed gating)
Measure: t_detect, t_sw, t_glt, δ_duty, f_meas_ppm, counters

Factory Hooks

AQL sampling across cold/room/hot corners
Golden JSON snapshot per lot with pass-bands
Cloud upload retries + integrity tag

Frequently Asked Questions

Missing-pulse vs frequency window — which avoids false alarms better?

Missing-pulse detection is strongest for Stop or gated clocks because it watches for absent edges. A frequency window is better for Slow/Fast/Runaway drift. Use both, each with its own debounce. Size the window with hysteresis H_f (ppm), and set the missing-pulse timeout t_mp = k·T_clk to cover 95% jitter plus margin.

How do I set hysteresis and debounce to prevent flicker?

Combine frequency hysteresis and sample-based qualification. Start with H_f ≥ 2×(tolerance + temp drift + quantization). Require N consecutive in-range samples (typically 3–5) before declaring stable. Add a lockback window T_lockback after recovery to suppress rapid re-entry. Keep missing-pulse debounce independent so brief jitter bursts do not force a switchback.

How do I control glitches and duty-cycle error during backup switchover?

Use a glitch-free MUX or a zero-delay device and measure peak glitch time t_glt. Limit t_glt with phase-aligned switching, then correct residual duty error δ_duty using a one-shot shaper or duty corrector. Define acceptance: t_glt ≤ Y ns and δ_duty ≤ Z%. For fast interfaces, buffer or divide after the MUX to relax downstream timing.

How do I log who triggered the switch (Stop/Drift/Runaway) for service analysis?

Record a minimal, portable JSON entry: {event_id, tstamp_ms, mode, f_meas_ppm, action, switchover_count, stop_count, drift_count, fw_ver}. Add clk_src(active) if available. The mode encodes the trigger class; counters show history. Include lot, board_id, and tempC when present so field returns can be traced to production conditions and component lots.

What peripherals are most sensitive when backup accuracy is weaker?

Protocols with tight timing or eye-diagram budgets—USB, Ethernet, video, high-speed ADC/DAC sampling—are most sensitive to ppm error and jitter. UART and many SPI links are more tolerant. If backup tolerance is limited, degrade first: reduce link rates, pause isochronous paths, or switch noncritical blocks to derived clocks until the primary reference returns stable.

With the watchdog, should I degrade operation or reset immediately?

Gate watchdog feeds under FAULT_CLK to avoid “good-dog on bad clock.” Prefer staged response: degrade and switch to backup first, then reset only when stop_count exceeds N or frequency drops below f_min_safe. This preserves logs and telemetry for root cause while protecting the system when timing falls outside safe operating limits.

How should thresholds adapt with temperature-induced slow drift?

Characterize enter/exit points across −40…125 °C, then apply temperature-aware limits. A simple model is f_low/high(T) = f_nom·(1 ± (α0 + kT)). During cold start, widen H_f and reduce N to avoid premature trips, then tighten after stability. For production, a two-segment LUT or linear slope per grade is often sufficient and robust.

For gated-low/high lockups, how do I choose the timeout limit?

Identify the longest legitimate gate interval from power-save states and DMA bursts, then set the missing-pulse timeout above it with margin. A practical start is t_mp ≥ 1.2×t_gate_max_legit. Interlock with system mode so deep-sleep gating is whitelisted, while unexpected continuous low or high forces a fault path and optional switchover.

How do I avoid false trips during slow crystal startup at power-on?

Use a cold-start blanking window t_blank = t_bak_start + margin to ignore early edges. During t_blank, relax frequency thresholds and hysteresis, then progressively tighten as amplitude and frequency settle. Qualify with N consecutive stable samples before allowing switchover or watchdog gating to resume normal enforcement in steady-state operation.

What are the minimum factory probes and scripts for production test?

Provide probes on CLK_IN, CLK_BAK, MUX_OUT, PG/FAULT/IRQ, and WDT_GATE. Keep three reusable scripts: stop injection, ±Δf scan, and jitter-burst. Record the minimal JSON per unit with t_detect, t_sw, t_glt, δ_duty, and counters. Use AQL sampling across cold/room/hot to ensure drift margins and switching behavior remain within limits.

How do I verify event counters and signal polarity when substituting brands?

Follow a four-step check: Electrical (OD/PP, polarity, voltage levels), Timing (t_detect, t_sw, t_glt, t_bak_start), Environment (temp and jitter tolerance), and Recording (counter increments and JSON fields). Confirm stop_count and drift_count rise identically for the same stimuli. Update cloud mappings before release so dashboards remain consistent.

How should telemetry fields be designed for future cross-brand migration?

Keep neutral names and a fixed minimal set: {event_id, tstamp_ms, mode, f_meas_ppm, action, switchover_count, stop_count, drift_count, fw_ver}. Add optional board_id, lot, tempC, and vdd. Apply T_merge, R_max, and a de-dup key {mode, action, clk_src} with f_ppm bucketing to prevent storms while preserving auditability.

Clock Monitor / Missing-Pulse Supervisor

Clock Monitor / Missing-Pulse Supervisor

What It Solves

Failure Modes

Observable Symptoms

Detection Capabilities

Response Policy

Detection Methods

Missing-Pulse Window

Frequency Window + Hysteresis

Period Counter

Δφ Accumulator (Phase Drift)

Debounce & Qualification

Backup Clock Switchover

Backup Sources

Switch Modes

Glitch & Duty Control

Recutover Policy

Validation & Metrics

Reset / IRQ / PG Semantics

Signals & Polarities

Interlocks

State Machine

Event Classes & Logging

Validation

Design & Validation

Timing & Accuracy Budgets

Reliability: Temp / Vibration / Noise

Test Scripts (copy-ready)

Pass/Fail & Logging

Small-Batch Procurement Hooks

BOM Remarks (copy-paste)

Electrical

Timing

Environment

Recording

Concrete Parts (by brand) & Selection Rationale

Selection Checklist (copy-paste)

Cross-Brand Alternatives

Renesas (IDT)

Microchip (Microsemi)

Texas Instruments

onsemi

NXP

STMicroelectronics

Melexis

Telemetry & Test Points

Minimal Event Schema

Throttle & De-dup

Board Test Points

Factory Hooks

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