← Back to: Supervisors & Reset
What It Solves
Long harnesses and remote loads make source-side single-point sensing misread the true voltage at the load. The drop is dominated by I·R and L·dI/dt, while shared returns inject ground bounce. Remote-sense supervision places the trip threshold at the remote pad, adding hysteresis and deglitching to stop false resets.
Typical symptoms
- Chatter during slow ramps (toggle/reset oscillation)
- Short false UV trips on load steps (high di/dt)
- Threshold drift between A/B harness lots (AWG/length variance)
Key KPIs
- False-reset rate (#/1000 starts)
- Reset margin at remote pad (mV)
- Repeatability across harness lots (σ / range)
- Temp drift at −40/25/85 °C
Principle: Differential Remote-Sense Supervision
Kelvin the sense pair (+VSNS/−VSNS) to the remote load pad and decouple them from power traces. Define UV/OV at the remote point, then map the trip back to the source by budgeting cable I·R and L·dI/dt, plus layout-dependent damping. Add hysteresis and deglitching to suppress slow-ramp chatter while keeping 10–50 µs real faults visible.
Equations (remote-centric)
Vload = Vsrc − I·Rpath − L·dI/dt
Vtrip,src ≈ Vtrip,remote + ImaxRpath + k·dI/dt
Design levers
- Hysteresis ≥ (dV/dt)ramp·treset + noise margin
- Deglitch tG/delay tD to reject bursts yet pass 10–50 µs faults
- Sense RC vs input bias: avoid error from high source impedance
- Check CMR window & input clamps/ESD positioning
Cable-Drop Compensation Models
For long harnesses, static (R-dominated) and dynamic (R+L) drops must both be budgeted. Define the threshold at the remote pad, then map back to the source with I·R and L·dI/dt headroom; avoid over-compensation that hides real undervoltage.
Static (R-dominated)
- Use Imax·Rpath with harness specs (AWG/length).
- Conservative margin M ≈ 3–5% @ 1–2 m · 18–22 AWG.
- Define Vtrip,remote=Vspec−M; verify across lots.
Dynamic (R+L)
- Add L·dI/dt headroom or digital deglitch tG.
- Do not hide true UV; 10–50 µs faults must remain visible.
- Finalize with measured k (layout/RC damping) and Leff.
1) Estimate Rpath (AWG, length, loop) · 2) Estimate max(dI/dt) · 3) Set Vtrip,remote=Vspec−M
4) Vtrip,src≈Vtrip,remote+ImaxRpath+k·dI/dt · 5) Tune Hys / tG / tD / RC, then measure k, Leff
| Item | Assumption / Data | Result / Note |
|---|---|---|
| Supply & Load | 5 V, Imax=3 A; step 1.5 A/µs | Fast step worst-case |
| Harness | 1.5 m, 20 AWG (loop ≈ 3.0 m) | Use loop length |
| Rpath estimate | ≈33 mΩ/m → 0.033×3.0≈0.10 Ω | I·R≈0.30 V @ 3 A |
| Leff (step) | 0.15–0.30 µH | L·dI/dt≈0.23–0.45 V |
| Remote margin M | Start 5%, verify vs I·R | 0.25 V is insufficient here |
| Vtrip,remote | Consider 4.55–4.65 V | Headroom vs dips |
| Vtrip,src back-map | ≈ Vtrip,remote + 0.30 + (0.23–0.45) | ≈ 5.08–5.40 V → prefer tG |
| Hys / tG / tD | Hys 80–120 mV; tG 20–40 µs; tD 80–150 µs | Reject spikes; pass 10–50 µs faults |
Thresholds, Hysteresis & Filters
Threshold accuracy
±0.5–1% class referenced to the remote pad; publish drift at −40/25/85 °C; map to source for debug only.
Hysteresis design
Hys ≥ (dV/dt)ramp · treset + ΔVnoise. Provide bands for slow/typical/noisy ramps; verify chatter count = 0 across lots.
Deglitch & delay
tG 20–40 µs rejects spikes; tD 80–150 µs avoids premature fan-out. Guarantee 10–50 µs true faults are visible.
RC input filter
Match RC corner to harness ringing; check input bias × source impedance error; cap leakage across temp.
I/O Styles & Reset Semantics
OD vs PP
OD (open-drain) is preferred for mixed voltage domains and wired-OR trees; edge rate set by RPU / CBUS.
PP (push-pull) gives crisp edges and accurate pulse width but is risky for cross-domain OR. Use clear polarity: *_RST_L / *_RST_H.
PG vs RST
PG (Power-Good) signals supply validity and should not directly force resets. RST (Reset) is authoritative and must meet minimum pulse width and level compatibility; avoid PG→RST direct wiring.
Wired-OR aggregation
With multiple OD sources, select RPU against the total bus capacitance to meet rise-time target. Edge quality impacts remote effective pulse width on long harnesses.
Pulse-width guarantee
Guarantee the MCU cold-start / clock-domain requirement (e.g. ≥10 ms; see datasheet). Validate at the remote pin with harness capacitance and load attached.
Pull-up sizing (rise-time target): RPU ≤ tr,target / (2.2 · CBUS) · Remote effective width: tRST,remote ≈ tRST,src − tfall − trise
| CBUS (incl. cable) | tr,target | RPU (max) | Note |
|---|---|---|---|
| 10 nF | 1.0 ms | ≈45 kΩ | Low cable C, gentle edges |
| 47 nF | 1.0 ms | ≈9.7 kΩ | Typical long harness |
| 100 nF | 1.0 ms | ≈4.5 kΩ | Faster RST rise to keep width |
Layout & Harness Practices
Kelvin & return
Take Kelvin at the load pad end; keep +VSNS/−VSNS paired/twisted; avoid crossing high-current returns or ground slots.
Return topology
High-frequency power returns favor the shortest loop; system grounds converge via star point. Sense return must not share power return.
ESD/EMI placement
Put TVS/RC near the connector; add common-mode choke before entering the board; avoid small sense loops that can self-oscillate.
Production consistency
Fix AWG/length tolerance, crimp pull strength, and termination resistance limits. Re-validate when switching harness vendors.
Validation Playbook
Fixtures & Sources
- Adjustable R/L harness emulator（R by AWG/length, L by lay/twist）
- Programmable load & step current source（≥1.5 A/µs dI/dt）
- Programmable ramp supply（0.1–5 V/ms）
- ESD/EFT/Surge injection (coupled), record mis-trips & recovery
- Remote Kelvin probes at load pads（dual-sense capture）
Test Matrix
- Temperature：−40 / +25 / +85 °C
- Harness：18/20/22 AWG × 1 / 1.5 / 2 m
- Load：static（0.2/0.5/1.0·Imax）/ dynamic（±ΔI, set dI/dt）
- Ramp：0.1 / 0.5 / 1 / 2 V/ms
- EMI：none / typical injected profiles
Observables
- False decisions per 1000 power-ons; chatter count
- Vtrip deviation (remote-defined vs measured)
- Remote RST width (wired-OR bus RC considered)
- EMI pass ratio & recovery time
Release Criteria
- Cpk ≥ 1.33 on key metrics
- “Minimal re-verification set” for cross-brand migration（top-risk quadrants in heatmap）
- Document compensation knobs（hysteresis/debounce/RPU）
Cross-Brand Shortlist
Selection focuses on accuracy, controllable hysteresis/delay, OD/PP output, wide supply and temperature ranges, and suitability for remote-sense (Kelvin at load pads). Notes include migration/re-validation points.
| Brand | Part Number | Accuracy (%) | Hysteresis (mV/%) | Delay (ms) | Output | VDD Range (V) | Iq (typ) | Temp | AEC-Q | Package | Notes (remote-sense fit & re-validation) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| TI | TPS3890-Q1 | ≈1 | config via ext RC (windowing by design) | prog. (cap) | OD/PP options* | 1.8–6.5 | low | −40~125 °C | Yes | SOT-23/DFN | Has separate SENSE pin—define Vtrip,remote at load; re-verify RPU/RC with harness C. |
| TI | TPS3702-Q1 (window) | ≈0.5–1 | small, fixed window | fixed / cap-set tD | OD/PP variants* | 1.8–5.5 | low | −40~125 °C | Yes | SOT-23/DFN | UV/OV window suits long-harness drift; map thresholds to remote pads. |
| TI | TPS3840-Q1 (low Iq) | ≈1.5 | — | prog. (cap) | PP/OD* | 1.6–6.5 | ultra-low | −40~125 °C | Yes | SOT-23/DFN | Best for low-power remote nodes; pair with external window if needed. |
| Renesas | ISL88014 (adj/fixed) | ≈1 | ext RC settable | cap-delayed POR | OD/PP families | 1.5–6 | low | −40~125 °C | Options | SOT-23/DFN | Use adjustable channel to encode remote Vtrip; verify output polarity vs reset tree. |
| NXP | FS65xx PMIC (UV/OV supervisors) | tight (PMIC) | config via registers | prog./fixed per rail | PP + status pins | VBAT | — | −40~125 °C | Yes | QFN/BGA | Layer with external differential supervisor for the longest harness lines. |
| ST | STM706/708, STM813L | ≈1–2 | fixed / RC options | fixed / cap-set | PP/OD families | 1.2–5.5 | low | −40~105/125 °C | Options | SOT-23/SOIC | Pair with external window/diff-sense; good for reset timing & watchdog combo. |
| onsemi | NCV809 / MAX809-Q variants | ≈1.5–2.5 | — (fixed) | fixed pulse width | PP (active-low) | 0.8–6.0 | very low | −40~125 °C | Yes | SOT-23 | Use to re-shape remote RST width; not a differential window—combine upstream. |
| onsemi | NCV33164 (UV detector) | ~2 | — | fast detect | Open drain* | 2.0–40 | low | −40~125 °C | Legacy/Auto | TO-92/SOIC | Secondary UV gate; verify thresholds vs remote mapping. |
| Microchip | MCP1316/18/19 family | ≈1–2 | fixed / variant-dependent | fixed / cap-set | PP/OD options* | 1.8–5.5 | low | −40~125 °C | Options | SOT-23/SOIC | Good as local reset conditioner after remote differential supervisor. |
| Melexis | (no standalone high-precision supervisor) | — | — | — | — | — | — | — | — | — | Use external diff/window supervisor (e.g., TI TPS3890-Q1) alongside Melexis PMIC/MCU rails; re-verify polarity & timing. |
* Check exact suffix for OD/PP and polarity variants. Always define thresholds at the remote pads; back-propagate source thresholds with I·R + k·dI/dt budget; re-compute RPU for total bus C.
Request a Quote
Small-Batch Procurement Hooks
Use these cards and checklists to submit a clean, verifiable BOM and to migrate across brands with minimum re-validation.
Required BOM Notes
- Rail name; remote sense pads (photo or coordinates).
- Harness AWG & length; rail Imax.
- Thresholds @ remote pads: UV / OV targets; accuracy goal.
- Hysteresis target (mV / %); debounce tG; output delay tD.
- Output style & polarity: OD/PP, _L/_H; minimum MCU reset width.
- Operating temperature; AEC-Q level; package preference.
Optional (Helpful)
- RC input filter corner; intended EMI profile / test level.
- Harness style: twisted pair, shielding, connector PN.
- Reset bus pull-up value and estimated bus capacitance.
- Waveforms: slow ramp, worst dI/dt step and recovery.
- Board photos marking remote pads and return paths.
Quality & Traceability
- Substitution window: Accuracy ±(0.5–1)%, Hysteresis ±(10–20) mV, Delay ±(2–5) ms.
- Primary / backup shortlist; acceptable packages; lifecycle status.
- Harness supplier & crimp policy; sample vs mass-production parity clause.
- Measurement method: remote vs source reference; equipment list.
- Re-map thresholds: remote → source (I·R + k·dI/dt allowance).
- Confirm Hysteresis ≥ (dV/dt)ramp × treset + margin.
- Unify polarity and OD for wire-OR trees; verify pull-up.
- Guarantee reset width at MCU after bus RC; log measured value.
- RC corner within EMI plan; keep 10–50 µs genuine sags visible.
- Match temperature & harness corners to the validation matrix.
- Temps: −40 / 25 / 85 °C
- Harness: 1 m · 22 AWG; 1.5 m · 20 AWG; 2 m · 18 AWG
- Load: static + one worst dI/dt step; one slow ramp
Record: false-reset count, Vtrip bias vs remote target, effective reset width, pass rate after EMI injection. Target Cpk ≥ 1.33.
FAQs
How far from the load should the remote sense land to avoid ground bounce?
Place the sense pair at the pad edge of the target load, not across a high-current return. Keep +VSNS/−VSNS tightly coupled or twisted so common-mode tracks out. Avoid vias that jump into shared returns. A 2–5 mm distance from the actual load pad is typically stable on dense boards.
How much hysteresis is needed to suppress slow-ramp chatter?
Size hysteresis to exceed ramp(dV/dt) × reset-settle time plus a guard band. As a rule, choose Hys ≥ (dV/dt)ramp × treset + 10–20 mV. This kills repeated crossings on very slow ramps while keeping thresholds tight enough to flag real brownouts.
How do RC input filters and digital debounce work together without hiding real faults?
Use RC to tame ringing from harness L and layout parasitics, then apply a short digital window tG. Keep the RC corner above the energy of EMI you intend to ignore, and choose tG so 10–50 µs genuine sags still pass. Always tune while probing the remote pads.
Is a 1 m harness required to be twisted? Does shielding help noticeably?
Twisted sense lines are strongly recommended to improve noise immunity and common-mode tracking. Shielding helps in harsh EMI environments but gives less benefit than tight coupling and a clean return path. Start with twisted pair; add shielding only if injected-EMI tests show residual susceptibility.
How do I budget a remote threshold including I·R drop at Imax?
Define the target Vtrip,remote from the load spec, then back-propagate to the source: Vtrip,src ≈ Vtrip,remote + Imax·Rpath + k·dI/dt. Use worst-case AWG/length for Rpath and a measured k from your RC and layout. Verify at temperature to catch copper and connector drift.
When mixing voltage domains, when should I prefer open-drain instead of push-pull?
Choose OD for wire-OR trees, mixed-voltage compatibility, and safe fan-in across level domains. It tolerates different VIO as long as the pull-up is correct. Use PP only when you need a clean edge and a guaranteed pulse width into a single domain without bus sharing.
How do I validate threshold repeatability across −40~+85 °C, AWG and length?
Use a three-by-three corner matrix: temps (−40/25/85 °C) × harness (22/20/18 AWG at 1/1.5/2 m). Sweep slow ramps and one worst dI/dt step. Record Vtrip at the remote pads and compute bias vs target. Aim for Cpk ≥ 1.33 for production release.
How do I separate EMI bursts from genuine 10–50 µs brownouts?
Set RC to desensitize high-frequency ringing, then pick tG just below the shortest brownout you must catch. Inject bursts while monitoring the remote pads and the reset output. A pass condition is “no reset on burst, reset on 10–50 µs injected sag.”
How do I avoid races when paralleling a supervisor with PMIC PG lines?
Prefer OD for all contributors and pull up once at the receiving domain. Ensure each source meets the minimum low-level sink current. If any PP is unavoidable, isolate through a transistor or a wired-OR diode so it cannot fight the bus or shorten the reset pulse.
How do I prevent false resets when dI/dt > 1 A/µs during load steps?
Budget the inductive term L·dI/dt into the back-propagated threshold and add short tG debounce. Keep the sense pair tight to the load pads and avoid loops. Verify with a programmable step source; measure remote V and reset width to confirm no chatter.
Star ground or shortest loop—what is the better choice here?
Choose by return topology. For heavy power planes, shortest loop reduces loop area and noise pickup. For many narrow returns, a disciplined star keeps the sense reference clean. In both cases, never route the sense reference across shared high-current returns.
How do I keep reset polarity and width consistent when migrating brands?
Normalize to OD active-low where possible and enforce a bus-level minimum width at the receiver. Re-map thresholds and hysteresis, then confirm pulse width after bus RC and fan-in. Run the minimal re-validation script to sign off at temperature and harness corners.
