PMBus/SMBus Power Monitor: Telemetry, Alerts and Scripts

Cross-brand differences → Unified semantics

Normalize Bits/LSB/Default/Polarity into a single schema for V/I/P/T and status.

False triggers → Mask + Debounce + N-of-M

Order matters: filter first, then route. Suppress ripple without missing real faults.

Field trim → Safe minimal write set

Only write thresholds, hysteresis, debounce, masks, N-of-M. Verify with read-back (PEC if available).

Quick start (minimal set)

• Define unified units & LSB mapping for V/I/P/T + status bits.
• Set UV/OV/OC/OT with Hys + Debounce + N-of-M combination.
• Apply route priority: critical → ALERT#, secondary → aggregated PG.
• Write → read-back verify → log change set with timestamp/sequence.

Block	Register	R/W	Bits	Resolution	LSB (unit)	Range	Default	AVG/PEAK	Note
VOUTn	V_MEAS	R	12–16	mV-level	LSB_V	0…FS_V	device	AVG/PEAK opt.	Kelvin if avail.
IOUTn	I_MEAS	R	12–16	mA-level	LSB_I	0…FS_I	device	AVG/PEAK opt.	Shunt calib.
PIN	P_MEAS	R	16	mW-level	LSB_P	0…FS_P	device	AVG/PEAK opt.	Calc(V*I)
TEMP	T_MEAS	R	12–16	°C-level	LSB_T	-40…+125	device	AVG/PEAK opt.	Sensor offset

Scale & LSB

LSB = smallest step. code = round(value/LSB)

Full-scale

Upper bound before saturation; exceeding clips.

Saturation

Reading at limit; treat as warning for scaling.

Clip

Capped value after FS; keep logs for post analysis.

Event	Mask Bit	Latch/Auto-clr	Debounce (ms)	N-of-M	Priority	Route	Comment
UV/OV	MASK_UVOV	Latch	3–10	3/5	High	ALERT#	Slow ramps → larger Hys
OC/OP	MASK_OCOP	Latch	1–5	2/4	High	ALERT#	Short spikes → debounce
OT/UT	MASK_OTUT	Auto	10–50	3/5	Med	GPIO/IRQ	Prefer pre-alarm + delay
ΔV/ΔI	MASK_DVDI	Auto	1–5	3/5	Med	GPIO	Ripple heavy rails

Slow Ramp

Use larger Hys + medium Debounce to avoid chatter near the boundary.

Heavy Ripple

Use medium Hys + N-of-M; Debounce moderate. Suppress bursts while keeping real faults.

Temp Drift

Bin thresholds by temperature (cold/room/hot) with table lookup; keep release point consistent.

Rail	UV / OV	OC / OP	OT / UT	Hys	Debounce (ms)	N-of-M	Comment
VOUT0	UV=… / OV=…	OC=… / OP=…	OT=… / UT=…	Hys=…	5	3/5	Slow ramp template
VOUT1	UV=… / OV=…	OC=… / OP=…	OT=… / UT=…	Hys=…	3	4/7	Heavy ripple template
TEMP	—	—	OT/UT (binned)	Hys=…	10	3/5	Temp-binned thresholds

Conversion & saturation guard

# value: engineering unit; LSB: quantization step; FS: full-scale
code = round(value / LSB)
code = max(0, min(code, FS))  # saturation guard
# Write → Read-back → Compare (expect == code)
      

SMBus script skeleton (write → verify → log)

# file: pmbus-thresholds--.txt
# phases: Identify → Baseline → Measure → Trim → Verify → Commit → Log

# Identify
READ_WORD  DEV, ID_REG         ; expect known device ID
READ_WORD  DEV, REV_REG        ; capture silicon/rom rev
# Baseline
LOAD_BASELINE profile=minimal-thresholds
SNAPSHOT_SAVE before.json

# Trim (minimal write set — thresholds/hys/debounce/mask/n-of-m)
WRITE_WORD DEV, UV_THR,  code_uv
WRITE_WORD DEV, OV_THR,  code_ov
WRITE_WORD DEV, HYS_CFG, code_hys
WRITE_WORD DEV, DB_MS,   code_db
WRITE_WORD DEV, NOFM,    code_n_m
WRITE_WORD DEV, MASK,    code_mask

# Verify (read-back + PEC if available)
READ_WORD  DEV, UV_THR  -> expect code_uv   [PEC=ON]
READ_WORD  DEV, OV_THR  -> expect code_ov   [PEC=ON]
READ_WORD  DEV, HYS_CFG -> expect code_hys  [PEC=ON]
READ_WORD  DEV, DB_MS   -> expect code_db   [PEC=ON]
READ_WORD  DEV, NOFM    -> expect code_n_m  [PEC=ON]
READ_WORD  DEV, MASK    -> expect code_mask [PEC=ON]

# Commit (if device supports non-volatile commit)
IF HAS_COMMIT:
  UNLOCK_NVM
  COMMIT_NVM
  LOCK_NVM

# Log (for rollback and traceability)
LOG_JSON  after.json, diff=auto, ts=now()

# Retry & timeout policy (pseudo)
# retry up to 3 times with exponential backoff (50ms, 100ms, 200ms); on mismatch → rollback
      

Do not write (blacklist)

• Control-loop / compensation parameters, soft-start/soft-stop, power-path enables.
• Sequencing / reset / watchdog configuration (handled on sibling pages).
• Any undocumented, vendor-specific “test” or “factory” registers.

Slow Ramp

Use larger Hys + medium Debounce to avoid chatter near the boundary.

Heavy Ripple

Use medium Hys + N-of-M; Debounce moderate. Suppress bursts while keeping real faults.

Temp Drift

Bin thresholds by temperature (cold/room/hot) with table lookup; keep release point consistent.

Rail	UV / OV	OC / OP	OT / UT	Hys	Debounce (ms)	N-of-M	Comment
VOUT0	UV=… / OV=…	OC=… / OP=…	OT=… / UT=…	Hys=…	5	3/5	Slow ramp template
VOUT1	UV=… / OV=…	OC=… / OP=…	OT=… / UT=…	Hys=…	3	4/7	Heavy ripple template
TEMP	—	—	OT/UT (binned)	Hys=…	10	3/5	Temp-binned thresholds

Conversion & saturation guard

# value: engineering unit; LSB: quantization step; FS: full-scale
code = round(value / LSB)
code = max(0, min(code, FS))  # saturation guard
# Write → Read-back → Compare (expect == code)
      

SMBus script skeleton (write → verify → log)

# file: pmbus-thresholds--.txt
# phases: Identify → Baseline → Measure → Trim → Verify → Commit → Log

# Identify
READ_WORD  DEV, ID_REG         ; expect known device ID
READ_WORD  DEV, REV_REG        ; capture silicon/rom rev
# Baseline
LOAD_BASELINE profile=minimal-thresholds
SNAPSHOT_SAVE before.json

# Trim (minimal write set — thresholds/hys/debounce/mask/n-of-m)
WRITE_WORD DEV, UV_THR,  code_uv
WRITE_WORD DEV, OV_THR,  code_ov
WRITE_WORD DEV, HYS_CFG, code_hys
WRITE_WORD DEV, DB_MS,   code_db
WRITE_WORD DEV, NOFM,    code_n_m
WRITE_WORD DEV, MASK,    code_mask

# Verify (read-back + PEC if available)
READ_WORD  DEV, UV_THR  -> expect code_uv   [PEC=ON]
READ_WORD  DEV, OV_THR  -> expect code_ov   [PEC=ON]
READ_WORD  DEV, HYS_CFG -> expect code_hys  [PEC=ON]
READ_WORD  DEV, DB_MS   -> expect code_db   [PEC=ON]
READ_WORD  DEV, NOFM    -> expect code_n_m  [PEC=ON]
READ_WORD  DEV, MASK    -> expect code_mask [PEC=ON]

# Commit (if device supports non-volatile commit)
IF HAS_COMMIT:
  UNLOCK_NVM
  COMMIT_NVM
  LOCK_NVM

# Log (for rollback and traceability)
LOG_JSON  after.json, diff=auto, ts=now()

# Retry & timeout policy (pseudo)
# retry up to 3 times with exponential backoff (50ms, 100ms, 200ms); on mismatch → rollback
      

Do not write (blacklist)

• Control-loop / compensation parameters, soft-start/soft-stop, power-path enables.
• Sequencing / reset / watchdog configuration (handled on sibling pages).
• Any undocumented, vendor-specific “test” or “factory” registers.

Submit your BOM (48h)

Scope: local telemetry logging only. No cloud/security chain, no reset tree, no power-path policy here.

Field	Type	Length / Range	Example	Note
ts_rel	uint32 (ms)	0…4 294 967 295	15342	Relative since boot; use with seq & boot_cnt
seq	uint16	0…65535 (wrap)	27	Monotonic event index
boot_cnt	uint16	0…65535 (wrap)	102	Incremented on each power-up
rail	ascii[8]	label / index	VOUT0	Channel or alias
event	enum8	UV/OV/OC/OT/UT/ΔV/ΔI/PG	UV	Event class only
raw_code	uint16	0…FS (device)	1023	Unscaled register code
scaled_value	float32	engineering unit	0.97 V	Using current LSB mapping
mask_state	bitfield16	mask/latch/debounce/n-of-m	0x2134	Snapshot of filter config
route	enum8	ALERT#/GPIO/IRQ	ALERT#	Output path
sync_flag	enum8	UNSYNCED → COMMITTED	UNSYNCED	Flip after bulk commit

Write Amplification Control

• Band counters: accumulate in-band fluctuations (e.g., UV ± 2 mV) and write a single summary event.
• Change-only: log only when thresholds / hysteresis / debounce / N-of-M / mask actually change.
• Bulk commit: mark new entries as UNSYNCED; flush in a low-write window and flip to COMMITTED.
• Tri-key order: sort by (boot_cnt, seq, ts_rel) to remain RTC-agnostic.

Write order: Mask → Hys/Debounce/N-of-M → Thresholds → Route → Read-back. No control-loop, sequencing or power-path writes on this page.

Brand	Family / Device	Example Register / Bit	Bits	LSB (unit)	Reset	Note
TI	UCD9090A / UCD90120A	VOUTn_UV / VOUTn_OV	12–16	mV (device)	device	Kelvin sense if available
Renesas	ISL28022/23 (monitor)	UV/OV code fields	12–16	mV / mA derived	device	Saturation guard recommended
Microchip	PAC1934 (monitor)	Threshold code fields	16	mV / mW	device	AVG window affects trips

Brand	Family / Device	Example Register / Bit	Bits / Range	Coupling	Reset	Note
TI	UCD9090A	NOFM_CFG (per rail)	N:0…7 / M:1…8	Debounce separate	device	Prefer N=3/M=5 as baseline
onsemi	NCP420x (digital)	Filter/Vote bits	N/M device-defined	Debounce coupled	device	Mind coupling semantics
Microchip	PAC1934	Vote window config	N:0…7 / M:1…8	Averaging affects vote	device	Tune with AVG window

Brand	Family / Device	Route / Polarity	Pull-up Domain	Reset	Note
NXP	PF5020 / PF8100 PMIC	ALERT#/GPIO / active-low	1.8–3.3 V	device	Aggregate secondary rails
ST	STPMIC1A PMIC	ALERT#/IRQ / polarity cfg.	1.8–3.3 V	device	Keep IRQ for non-critical
Melexis	External monitor with MLX systems	ROUTE → host GPIO	per host	—	Use TI INA226/Renesas ISL28022 etc.

Usage (Semantics Layer → Vendor Map)

1. Define a vendor-agnostic schema: UV/OV/OC/OT, Hys, Debounce, N-of-M, Mask, Route.
2. Bind schema fields to registers per brand; keep a read-back verifier (with PEC if supported).
3. Apply baseline → write minimal set → verify → log diffs (timestamp/seq/boot_cnt).

Item	Objective	Method	Instrument / Script	Pass Criteria	Log Fields	Notes
Avg Window × Debounce latency	Confirm total propagation stays within budget.	Set AVG & Debounce; inject steps; measure ALERT#/PG delay.	Scope ≥100 MHz; SMBus script (PEC)	P95 delay ≤ budget; log vs scope Δ ≤10%.	ts_rel, event, route, mask_state	Record settings with snapshot.
50/60 Hz false trips with N-of-M	Bound false-positive rate under mains ripple.	Superimpose 50/60 Hz ripple near thresholds; sweep N/M.	Ripple source; SMBus vote config	< 1e-5 over 10⁶ samples at both 50/60 Hz.	event, NOFM, scaled_value	Prefer N=3/M=5 baseline.
Slow ramp impact on UV/PG	Ensure no chatter across ramp slopes.	Sweep 0.1/1/10 V/s; observe UV trip/release & PG.	Prog. PSU; scope; script log	Single trip; release within Hys±tol.	event, raw_code, scaled_value	Keep Debounce medium.
ALERT# polarity & pull-up compatibility	Meet rise/fall and bus timing with given capacitance.	Test 1.8/3.3 V pull-ups & cable lengths; capture edges.	Scope; GPIO monitor	tr/tf within spec; no I²C timing violations.	route, mask_state	Prefer OD with defined domain.
Cold/Hot start repeatability (frozen cfg.)	Consistency across −40~+85 °C power cycles.	Temp chamber; cycle power; compare sequences.	Temp chamber; PSU; logger	Event order identical; PG Δ < 10%.	boot_cnt, seq, ts_rel	Commit NVM if supported.
Batch trim script + CRC/PEC read-back	Zero mismatches after minimal writes.	Apply minimal set; verify read-back=written.	SMBus host (PEC on)	30/30 pass; auto-rollback on error.	diff, error_code	Name files by rail/rev.
RTC-less ordering stability	Logs sort identically to external trigger.	Trigger known sequence; compare ordering.	Scope trigger; logger	(boot_cnt, seq, ts_rel) fully consistent.	boot_cnt, seq, ts_rel, sync_flag	Flip UNSYNCED→COMMITTED in bulk.
Quantization rounding margin (±T)	Guarantee margin after code rounding.	Compute → write → read-back → validate at temp corners.	Calculator; SMBus host; chamber	Worst-case margin ≥ target; no FS clamp.	raw_code, scaled_value	Keep release monotonic.
PG aggregation vs secondary routes	Ensure no masking between classes.	Disturb secondary rails; observe PG and IRQ paths.	Stimulus; GPIO logger	Primary PG stable; AUX only affects AUX.	route, mask_state, event	Document routing map.
Log write amplification & lifetime	Model writes/day and endurance years.	Storm simulation + bulk commits; count writes.	Script; counter; estimator	Life > target×1.5 safety factor.	count_in_band, sync_flag	Store rate & window size.
Mixed-family script idempotence	Repeat runs cause no drift across brands.	Run twice on ≥3 brands; ensure second diff=Ø.	SMBus host; mapper layer	Zero unexpected changes.	diff, error_code	Freeze blacklist.
Guard against mismatch/out-of-range writes	Reject non-whitelisted commands and values.	Inject blacklisted commands / OOR codes and observe behavior.	SMBus fuzz script	Rejected with error; original values intact.	error_code, raw_code	Enforce whitelist at host.

Copy-Ready Checklist (Plain Text)

- [ ] Avg window × Debounce latency within budget; P95 delay ≤ target; log vs scope Δ ≤ 10%.
- [ ] N-of-M false trips under 50/60 Hz < 1e-5 over 10^6 samples at both frequencies.
- [ ] Slow ramp (0.1/1/10 V/s): single UV trip; release within Hys±tol; PG stable.
- [ ] ALERT# polarity & pull-up domain meet rise/fall and I²C timing with bus capacitance.
- [ ] Cold/Hot start (−40~+85 °C): event order identical; PG delta < 10%.
- [ ] Minimal-write script: 0 mismatches on read-back with PEC; auto-rollback on error.
- [ ] RTC-less ordering matches external trigger using (boot_cnt, seq, ts_rel).
- [ ] Quantization rounding still leaves required margin over temperature; no FS clamp.
- [ ] PG aggregation does not mask secondary routes; AUX paths isolated.
- [ ] Log write amplification within lifetime budget (life > target×1.5).
- [ ] Mixed-family idempotence: second run produces empty diff on ≥3 brands.
- [ ] Whitelist enforcement rejects mismatched/out-of-range writes; error logged.
      

How do I choose UV/OV thresholds and hysteresis for slow-ramping supplies to avoid chatter?

Use larger hysteresis and a moderate debounce so trip and release are separated and boundary oscillation is suppressed. Sweep multiple ramp slopes with a programmable supply to verify a stable release point. Round to the LSB before coding and read back to confirm. If chatter remains, increase hysteresis first, then fine-tune debounce.

How should N-of-M and debounce be combined to avoid missing real faults?

For heavy ripple, prefer a higher M with moderate debounce so voting filters high-frequency false hits first; for low-frequency interference, bias toward longer debounce. A common baseline is N=3, M=5, debounce 5 ms. After bring-up, inject mixed step and sine stimuli, then tune using pass rate for true faults and false-alarm rate.

Why does ALERT# fire in “storms,” and how do I reduce noise with a masking order?

Multiple event classes crossing limits with the same route can cause storm-like triggers. First mask secondary events while keeping latch policy, then enable the primary fault; route the primary rail to ALERT# and aggregate secondary rails to PG/IRQ. Write in the order “mask → thresholds → route,” and read back to confirm status bits match.

Which thresholds are suitable for pre-warning plus delay rather than immediate shutdown?

Mild OV/OT is better used as a pre-warning with an added delay, giving the system time to log and derate; severe UV/OC usually triggers protection immediately. For pre-warning events, set smaller hysteresis with an explicit delay and log both the trip value and duration. During validation, check delay error and release consistency.

In multi-rail systems, how do I aggregate secondary-rail alerts into PG without masking the primary?

Connect the primary rail PG directly to critical routing, and aggregate secondary alerts to an AUX PG or IRQ to avoid sharing the same path. Configure independent masks and polarity for secondary rails so they cannot clear or pull down the primary PG. Validate no masking by injecting faults one by one and recording routes and status bits.

How can a threshold script avoid side effects from full register overwrites?

Use a safe minimal write set: only modify thresholds, hysteresis, debounce, voting, and masks—do not touch control-loop and timing bits. Enable PEC and verify with read-back; on failure, auto-rollback. Enforce a whitelist check in the script, and include channel and revision in the filename to guarantee traceability and reversibility.

With cross-brand LSB/scaling differences, how do I convert safely and verify readback?

Compute engineering values in a unified semantic, then apply each device’s LSB using code = round(value/LSB) with saturation clipping before and after the write. Read back immediately and compare with the expected code; verify margins at temperature extremes. If bit polarity differs, align polarity and reset values first to avoid logic inversion.

On the production line, how do I trim per-unit offsets and keep audit trails?

Follow Identify → Baseline → Trim → Verify → Commit → Log. Write only the minimal field set and enable PEC. Log device ID, old/new values, timestamp, and verification result; if verification fails, roll back to the baseline. Batch scripts should support retries with exponential backoff to avoid transient bus errors.

For intermittent faults, what is the minimum log field set to reproduce issues?

A minimal set includes ts_rel, seq, boot_cnt, rail, event, raw_code, scaled_value, mask_state, route, and sync_flag. It preserves order without an RTC and reconstructs the filtering and routing state at the time. Also log temperature band or product batch to support cross-analysis.

Without an RTC, how do I reconstruct event timing?

Use a three-key ordering (boot_cnt, seq, ts_rel) to ensure total ordering within one power-cycle, and separate cycles by boot_cnt. Mark events during power loss as UNSYNCED; after power-up, commit them in bulk during a low-write window. Use an external scope trigger as a reference to verify ordering correctness.

Under automotive temperature drift, how should the averaging window and thresholds work together?

Grade the averaging window and thresholds by temperature band: relax the window slightly or raise M at high temperature, and keep tighter hysteresis on the low-temperature side to counter offsets. For each band, verify release point and minimum margin, and record a table of configuration versus temperature for small on-site tweaks with read-back.

Is there a generic threshold template that can be validated on hardware within 48 hours?

Yes. Start with one of three baselines (slow ramp, heavy ripple, temperature drift) that best matches the scenario, and write only fields in the threshold domain. Run mixed step and sine tests, measure false-negative and false-positive rates, and confirm coding and polarity by read-back. Re-test both temperature endpoints within 48 hours and create a rollbackable snapshot.