← Back to: Supervisors & Reset
What It Solves
Upstream/Downstream PG interlock coordinates supervisors with eFuse / Ideal-Diode / Power-Mux so cascaded rails isolate fast and shut down safely—without false trips or thermal shock. Define PG polarity, domain, logic level, and valid window. Route PG → EN downstream and feed downstream FAULT ↑ upstream to ILIM/EN. OR-ing ΔV priority must arbitrate cleanly with eFuse fast-trip (SC/OV).
Typical Failures
- PG chatter → false shutdown
- OR-ing and eFuse act together → ping-pong
- Slow downstream off → thermal shock
Interlock Paths
- Upstream PG_valid → downstream EN
- Downstream FAULT ↑ → upstream ILIM/EN
- Arbitrate ΔV (OR-ing) vs fast-trip (eFuse)
Starter Values
- PG deglitch 1–10 ms; stretch 5–20 ms
- eFuse fast-trip 2–8 µs
- ΔV_trip 15–30 mV; ΔV_hyst ≥ 2×(I_share×R_path)
- ILIM_init = 1.2×Ipeak; ILIM_fb = 0.7×Irated
Validate with slow/fast ramps, brief brownout (5–10 ms), source switchover, harness drop, load step, and −40~+85 °C sweep.
Log t_PG-valid↑/↓, t_OFF(eFuse), ΔV_bus_min, I_rev_peak, Peak-Thermal.
PG Semantics & Wiring Rules
Prefer open-drain/OC PG/FAULT with a single pull-up to the target logic domain; use proper level shifting/isolators across domains. Apply input deglitch (1–10 ms) plus output stretch (5–20 ms). For long runs >10 cm add RC or Schmitt buffering. Avoid push-pull cross-domain direct ties and any multi-pull-up networks that create back-power paths.
Copy-and-Use Values
- Pull-up: 10–47 kΩ to target domain
- Input RC: 1–3 ms; deglitch: 1–10 ms
- Stretch: 5–20 ms; line >10 cm → RC/Schmitt
- Across domains → level shift/isolator
Sanity Checks
- Power off downstream → PG/FAULT fall naturally
- Measure reverse leakage (no back-power)
- EFT/ESD injection → no false toggles
Interlock Patterns
Three reusable interlock topologies coordinate start/stop chains and fault back-feed between upstream supervisors/eFuses and downstream ideal-diode/OR-ing stages. Use A for clean enable sequencing, B for fast protection via fold-back/cut, and C for arbitration between ΔV window (OR-ing priority) and fast-trip (eFuse SC/OV).
Parameters (Starters)
- Back-feed ILIM_fb: 0.6–0.8× Irated (limit, not cut)
- EN release delay: 0.5–2 ms
- PG stretch ≥ EN release + τdischarge(load)
Risks
- Both sides act together → ping-pong
- FAULT chatter → repeated fold-back
- ΔV window too narrow → frequent re-priority
Exercise injected events: pulse FAULT, sustained short, source switchover. Record
t_PG_valid, t_EN_release, t_fast-trip, ΔV_bus_min, I_rev_peak, ILIM_profile.
Timing & Threshold Cookbook
Core Recipes
ILIM_init = 1.2 × I_peak(load)ILIM_fb = 0.7 × I_ratedΔV_trip = 15–30 mV(by path Z & priority)ΔV_hyst ≥ 2 × (I_share,max × R_path,max)PG_deglitch ≥ 5 × t_ripple(PG)PG_stretch ≥ t_EN_release + τ_discharge(load)
Drift & Tolerance
- Comp/amp offset ±1–3 mV → budget into
ΔV_hyst - Resistor tempco 50–100 ppm/°C matters for high-R sense
- Keep ≥20% margin for environmental spread
Measurement Set
Log t_PG↑, t_EN↓, t_fast-trip, ΔV_bus_min, I_rev_peak.
Add thermal imaging to confirm hotspot migration and peak rise.
Common Fixes
- ΔV_trip too low → raise to reduce false re-priority
- Insufficient stretch → increase to complete discharge
- ILIM_fb too low/high → retune for heat vs uptime
Layout & Back-Power Hygiene
Route PG/FAULT away from high-dV/dt FET gates/drains and keep sensing tracks isolated from power loops. For ideal-diode/OR-ing sensing, preserve Vsense & Kelvin-R symmetry (matched length/return). Pull PG up to the downstream logic domain and ground there to avoid back-power. Pre-place small RC or series-R to tame long-line coupling.
Routing Rules
- Separate PG/FAULT from FET gate/drain planes
- Orthogonal crossing vs. parallel runs
- Symmetric Vsense/Kelvin, matched length
- Single pull-up in target domain, local decoupling
Starter Values
- Series-R (long lines): 22–100 Ω
- Input RC (PG/FAULT): 1–3 ms
- Pull-up: 10–47 kΩ to target domain
- Differential gap (Kelvin): ≤ 0.5–1 mm
Typical Risks
- Parallel run with power loop → coupled spikes
- Shared pull-up across domains → back-power
- Kelvin tied to high current node → ΔV distortion
Bench Sanity
- Near-field probe for spikes on PG/FAULT
- Measure reverse leakage during power-off
- Check false toggles under EFT/ESD stress
Validation Matrix
A minimal, repeatable bench matrix for small-batch validation. Exercise slow/fast ramps, source switchover, brief brownouts, load steps, harness drop, and temperature sweep. Record unified fields to compare builds and vendors consistently.
Use Cases
- Slow ramp: 2 s rise → PG stability & stretch
- Fast ramp: <1 ms → EN release order
- Source switchover: OR-ing primary/backup → ΔVbus valley & Irev peak
- Brownout: 5–10 ms dip & recover → tOFF(eFuse) & log
- Load step: 0→Ipeak → ILIM trigger & thermal
- Harness drop: series R to emulate distance → false priority?
- Temp sweep: −40~+85 °C → remeasure thresholds/windows
Record Fields
t_PG_valid↑/↓, t_EN↓, t_fast-trip, ΔV_bus_min, I_rev_peak, T_hotspot_max, log_tag(reason)
| ≥5–10 repeats: mean, σ, worst-case.
Decision Hints
- Overlap → raise ΔVhyst
- False toggles → add RC/series-R or more deglitch
- Excess thermal → reduce ILIM_fb before hard cut
Shortlist & Cross-Brand Slots
Slots for seven brands across two device groups. Final PNs should be re-verified against official datasheets (automotive first). Keep interlock semantics consistent: PG polarity/shape, EN/ILIM pin roles, and domain levels.
Supervisors / Reset IC (PG / Reset)
TPS37xx-Q1 / TPS38xx-Q1 / TPS3702-Q1
- Wide VIN, low Iq, programmable delay/hysteresis
- Open-drain or push-pull options; clean PG→EN sequencing; AEC-Q100
STM6717 / STM6719, STM706 / STM811
- Multiple thresholds and polarities; OD/PP variants
- Easy deglitch + stretch in the periphery; good for single pull-up
FS84 / FS85 Family (SBC/PMIC)
- Integrated PG/WD/FCCU; SPI-configurable timing
- Unifies system-level PG; easy routing to EN/ILIM upstream
ISL880xx / ISL803x
- Low Iq, programmable delay; clean PG→EN chain
- Pairs well with brand-mate OR-ing (ISL614x)
NCP303 / NCV303
- Ultra-low power, programmable delay; open-drain variants
- Good for cold reset and PG stretching
MCP1316 (AEC-Q100) / MCP12x / MCP13xx
- Push-pull, low Iq, broad threshold options
- Reliable “cold reset” of MCU clock domain
MLX8111x / 8114x (platform slot)
- Platform PG/reset/diagnostic pins for body/gateway domains
- Specific PNs depend on domain and network stack
eFuse / Hot-Swap / Ideal-Diode / Power-Mux (Interlock Counterparts)
LM74700-Q1 (Ideal-Diode), TPS212x (Power-Mux), TPS2598x-Q1 / TPS249x (eFuse/HS)
- Fast reverse-current block; ΔV window friendly
- MUX with priority control; eFuse with ILIM and FAULT
STEF12 / STEF12S / STEF12H60M (eFuse), ST PMIC w/ ID control
- Programmable ILIM/OV/UV; thermal/current telemetry (H60M)
- Pairs cleanly with supervisor families for FAULT back-feed
FS84 / FS85 SBC Power-path & gating pins
- SPI-configurable current limits and status flags
- System PG aggregation with back-feed control
ISL614x (Ideal-Diode/OR-ing)
- Low-drop OR-ing, reverse-current control
- Works well with ΔV priority + eFuse fast-trip arbitration
NIS5420 / NIS5421 (eFuse), NCV**** variants
- Fold-back/thermal shutdown; FAULT flag for upstream actions
- Automotive variants available for wider temp range
MIC20xx (load switch) / MIC94xxx (hot-swap/Mux)
- Soft-start, current-limit, thermal protection
- Good “gentle” downstream power layer to reduce upstream stress
SBC / gateway power-path pins (platform slot)
- EN/VSUP/FAULT resources for body/gateway domains
- Use as slots; exact PNs per platform definition
Notes: Prefer AEC-Q100, appropriate temp range, package pinout compatibility, PG polarity/OD vs PP option, EN/ILIM tie-in, and cross-brand migration feasibility. For small batches: check stock, cut-tape MOQ, and lead time.
Procurement Notes & BOM
Decision Order
- Interface compatibility first: PG polarity/shape (OD vs PP), EN/ILIM pins, domain levels
- Then programmability: deglitch, stretch, ΔVtrip, ΔVhyst, ILIM
- Then package & thermal: RθJA, external FET SOA
Validation Bundle
- Copy-ready interlock table:
deglitch,stretch,ΔV_trip,ΔV_hyst,ILIM_init,ILIM_fb - Three scripts: source-switchover → short → recovery
- Probing/marking:
t_PG↑/↓,t_EN↓,t_fast-trip,ΔV_bus_min,I_rev_peak,T_hotspot_max
Migration & Substitutes
- Prefer same PG polarity, OD shape, and similar ΔV/hysteresis capability
- Maintain PG→EN and FAULT→ILIM chains; use small adapter boards if needed
- Re-run timing matrix after swap; log
reasontags consistently
Request a Quote
Frequently Asked Questions
How long should PG deglitch and stretch be to avoid chatter across cascaded rails?
Start with 1–10 ms deglitch at the supervisor input to suppress ripple and comparator bounce, then stretch PG for 5–20 ms at the output so EN lines drop cleanly and loads discharge. Size stretch ≥ EN-release plus the dominant load RC. Validate at slow/fast ramps and brownouts to confirm no re-assertion.
Should PG be open-drain or push-pull when domains differ?
Prefer open-drain (or open-collector) with a single pull-up to the destination logic domain. This avoids back-power and simplifies level compatibility. Push-pull across domains risks latch-up or leakage when one rail is unpowered. Add series-R or RC at long traces and ensure only one pull-up resistor exists on the shared net.
How do I arbitrate OR-ing ΔV priority with eFuse short-circuit fast-trip?
Use ΔVtrip (15–30 mV typical) and ΔVhyst sized to expected sharing error so only one path is preferred. In a downstream short, give eFuse fast-trip (≈2–8 µs) precedence; the ideal-diode should block reverse current while the eFuse isolates. Avoid changing OR-ing priority simultaneously with the trip action.
What’s a safe ILIM fold-back when downstream faults propagate upstream?
Begin with ILIMfb ≈ 0.6–0.8× rated current, which limits thermal stress while maintaining telemetry and control. Keep the fold-back above the upstream converter’s minimum load to avoid instability. If thermal hotspots remain, step lower in small increments and verify recovery time and voltage sag on adjacent rails.
How to prevent back-power via PG pull-ups across domains?
Route PG as open-drain with the only pull-up resistor tied to the destination domain’s supply and ground. Do not share pull-ups between rails. Avoid push-pull outputs across domains. Where long harnesses exist, insert series-R (≈22–100 Ω) or RC at the receiver, and confirm no leakage when the source rail is off.
How to guarantee a “cold” reset of the MCU clock domain after interlocked shutdown?
Stretch RESET long enough to discharge VDD and internal state: hold for the MCU’s datasheet minimum plus the load discharge constant. Use supervisors with deterministic delay and known polarity. If domains differ, prefer open-drain reset with level translation or single pull-up in the MCU domain to avoid partial-power back-bias paths.
Which probes/logs prove the interlock under slow ramps and cable drops?
Probe PG, EN, ILIM, Vbus, and Irev simultaneously. Log t_PG_valid↑/↓, t_EN↓, t_fast-trip, ΔV_bus_min, I_rev_peak, and hotspot temperature. Exercise: slow 2 s ramp, <1 ms ramp, brownout 5–10 ms, source switchover, and series-R harness drop. Keep plots and numeric tables with worst-case tags.
When to gate EN vs reduce ILIM for thermal safety and recovery speed?
Use ILIM reduction when the fault is likely transient or recoverable and you want continuity with bounded power. Gate EN for hard faults, unsafe temperatures, or repeated trips where rapid, deterministic isolation is safer. Record recovery time, peak temperature, and voltage sag for both strategies, then pick per load criticality.
How to size ΔV hysteresis to stop ping-pong during source switchover?
Choose ΔVhyst ≥ 2× the worst-case sharing error: ΔVhyst ≥ 2·(Ishare,max · Rpath,max). Include comparator offset (≈±1–3 mV) and temperature drift. Validate by sweeping load and line; ensure only one path has priority and no oscillation occurs when a short or recovery is happening downstream.
What layout rules keep PG quiet near ideal-diode sense lines?
Route PG/FAULT orthogonally to power loops, avoid long parallel runs, and keep them away from FET gate/drain nodes. Use tightly coupled Kelvin/Vsense pairs of equal length. Terminate long PG lines with series-R or RC. Place the only pull-up in the destination domain and return to the same ground island to avoid loops.
How to make interlock timing robust over −40~+85 °C and tolerance stack-ups?
Budget temperature coefficients and comparator offsets into ΔV and delay settings. Re-measure deglitch, stretch, and ILIM at corners. Keep margins so PG stretch ≥ EN-release + discharge at cold (slow RC) and hot (faster trip). Use components with specified drift and include worst-case logging across supplies, loads, and ambient conditions.
What are quick cross-brand substitutes if one supervisor family is EOL?
Match interface first: same PG polarity, open-drain shape, and compatible EN/RESET pins. Then match timing (delay, deglitch, stretch) and thresholds. Keep package and pinout alike where possible; otherwise use an adapter board. After swap, rerun the validation matrix and confirm PG→EN and FAULT→ILIM chains behave identically.
