← Back to: Supervisors & Reset
Why Co-Design Supervisors
Cascaded: Buck → LDO
Use upstream PG as admission for downstream EN/SS. Mismatched UV/OV windows or soft-start slopes cause chatter and false resets.
Parallel / Branch Loads
Aggregate multiple PG sources and define policy to suppress nuisance resets across the same voltage domain.
Procurement Triggers
If you observe slow ramps + jitter, load-step droops, or temperature drift mis-trips, prefer multi-rail / windowed / programmable supervisors.
Rules: If RC delay cannot tolerate load-step × temperature, switch to windowed + asymmetric debounce. Set td(PG→EN) from SS_90%(downstream) − SS_90%(upstream) and add worst-case temperature slack.
Threshold Matching Rules
DC (steady-state):
σ_total ≈ √(σ_LDO² + σ_BUCK² + σ_sense²) ;
V_UV(assert) ≤ V_OUT(min) − 3σ_total − Δmargin ;
V_UV(release) ≥ V_OUT(nom) − σ_total (hysteresis ≥ 2–5%).
AC (transient):
t_blank ≥ max(t_settle95%_LDO, t_settle95%_BUCK) + Δring ;
V_OV − V_UV ≥ 2×V_ripple_pk + V_ring_pk + ΔT_drift.
Inputs → Outputs
Tolerance (LDO, BUCK, sense), ripple peak, ring peak, ΔT drift → V_UV(assert/release), V_OV, t_blank(assert/release), hysteresis %.
Temperature Re-check
Recompute at −40/25/+85 °C. Keep window margin ≥ worst-case temperature point.
Pre-Bias & Soft-Start Alignment
In pre-bias starts (Vout ≠ 0), non-zero initial voltage and brief ringing can cross UV/OV windows and trigger nuisance resets. Adopt a windowed supervisor with delayed release, ignore the early unstable segment with a grace window, and align Buck PG → LDO EN timing so downstream soft-start does not chase upstream settling.
Pre-Bias Immunity
Use window + release delay so a short ramp from a non-zero start or minor dip does not assert UV/OV prematurely during the first 10–50 ms.
Slope Matching
Buck first; once PG is valid, add delay td before enabling the LDO. Align SS_90% points and re-check across temperature.
Over/Undershoot Handling
For soft-start overshoot, delay OV assert. For pre-bias relaxation, lengthen UV release to avoid double-trigger near the window.
Grace window: t_grace ≥ max(t_settle95%_BUCK, t_settle95%_LDO) + Δring.
PG→EN delay: td ≈ SS_90%(LDO) − SS_90%(BUCK) + ΔTmax.
Asymmetry: t_UV_release > t_UV_assert (1.5×–3×).
OV in pre-bias: t_OV_assert ≥ t_grace.
Verify at −40/25/+85 °C with two SS settings (fast/slow) and two initial states (0 V / residual charge).
Acceptance: nuisance-reset = 0; measured td within ±10% (or ≤5 ms) of estimate.
Transient Windowing & Nuisance-Reset Immunity
Build amplitude–time compatible windows with asymmetric debounce so line dips, load steps, and ringing do not trip RESET unnecessarily. Spikes get short window + higher thresholds; slow sags get long window + lower thresholds. Always keep release longer than assert to ensure robust recovery.
Window + Hysteresis
Use upper/lower bounds with 2–5% hysteresis to reject ripple and thermal drift across production variance.
Asymmetric Debounce
t_assert short to catch real faults; t_release long (1.5×–3×) to prevent flapping during recovery.
PG vs RESET Semantics
PG reflects supply capability; RESET means system-ready. Treat them non-equivalently. Use event counters before escalating to RESET.
Window width: V_OV − V_UV ≥ 2×V_ripple_pk + V_ring_pk + ΔT_drift.
Spike immunity: t_blank(assert) ≥ 0.5×τ_ring.
Release guard: t_blank(release) ≥ max(t_settle95%_rail, T_dip×α), α∈[0.5,1].
Inject line dips (5/10/15% @ 50/200/500 µs), load steps (±20/50/80% Iload), and ring (1–3× ripple, τ = 20/50/100 µs). Track nuisance-reset count, PG flap, and recovery to 95–98%. Pass when nuisance-reset = 0 at worst corner.
Reset Tree & PG Aggregation
Unify PG and RESET semantics and build a stable reset tree across domains. Prefer OD (open-drain) for cross-domain / multi-source aggregation with pull-up to the safest I/O domain; use PP (push-pull) only in single-domain simplified paths. Add buffers when fanout or long runs degrade edges, and protect against back-power at aggregation nodes.
OD vs PP
Cross-domain / multi-source → OD + pull-up to MCU domain. Single-domain & simple → PP allowed with level compatibility and one-direction drive.
Fanout & Edge Budget
RESET fanout > 4 or net length > ~25 cm → add buffer/transceiver. Rise-time rule:
t_rise ≈ 2.2·R_PU·C_BUS ≤ 0.2×(shortest valid pulse).
Back-Power Protection
Add series resistors (47–220 Ω) at aggregation, use Schottky or dedicated fanout IC to block reverse current into unpowered domains.
Semantic split: PG = supply capability; RESET = system-ready gating. PG events first aggregate & filter; RESET is driven by policy (see #policy).
Polarity: unify PG lines as low-true OD (wired-OR), invert once at aggregator to MCU.
Propagation budget: Σt_pd + t_rise ≤ 0.5 × t_RESET_min.
KPI: nuisance-reset = 0 over −40/25/+85 °C; PG_AGG flap ≤ 1 per 10 power cycles; after ESD/IEC pulses, RESET not asserted spuriously. Measured t_rise and Σt_pd meet the budget.
Policy: Brown-Out, Fault & Start-Retry
Define graded actions for dips/faults and ensure RESET pulse width matches the MCU’s cold clock domain. Use counts and backoff to avoid oscillatory behavior. PG flaps should map to limited-function or counters first; only policy thresholds can escalate to RESET.
Light dips
Small/short dip → count only or limit functions; do not assert RESET.
Moderate
Single RESET and longer soft-start for the next attempt.
Severe
Enter retry with backoff up to N attempts; if still failing, degrade mode and set fault flag.
RESET width: t_RESET_min ≥ t_MCU_coldclk + t_periph_init + t_safety (use 20–30% safety).
Escalation: dips within T_window counted to threshold before RESET. Backoff: backoff_k = base × 2^k, k∈[0, N−1].
| Parameter | Meaning | Guideline |
|---|---|---|
| ΔV_guard | Dip amplitude threshold | Above ripple + ring envelope |
| t_assert / t_release | Asymmetric debounce | release = 1.5×–3× assert |
| N, base | Retry count & backoff base | N = 2–5; base per slowest peripheral |
| t_RESET_min | Cold domain alignment | ≥ 1.2–1.3 × (t_MCU_coldclk + t_periph_init) |
Measurement & Validation Plan
Define a minimal reproducible experiment and sign-off KPIs for the co-designed supervisor. Use scripted load/line transients, three-temperature sweeps, and boundary sampling at the UV/OV window edges. Capture CH1: Vout (LDO), CH2: RESET (to MCU), CH3: PG_AGG (aggregated PG), CH4: V_BUCK (upstream); optional CH5: Iload, CH6: EN(LDO), CH7/8: board temps.
Instruments & Channels
- Oscilloscope ≥200 MHz, ≥1 GSa/s; logic decode for RESET/PG edges
- Temperature chamber: −40 / +25 / +85 °C
- Electronic load & programmable supply with synchronized trigger
Scripted Stimuli
- Load steps: {20%, 50%, 80% of Imax} × slew options (e.g., 2 A/µs)
- VIN dips: {5%, 10%, 15%} × duration {50, 200, 500 µs}
- Ripple/ring envelopes: 1–3× Vripple,pk, τ = 20/50/100 µs
- Startup: 0 V and pre-bias (0.2–0.5× Vout)
- Boundary scan: at VUV/VOV ± Δ (Δ ≈ 0.5–1× σtotal), ≥30 repeats per point
KPIs (sign-off): Nuisance-reset rate (events/hour or per 100 power-ups) = 0; recovery time T95%/T98% within spec; minimal RESET passing width
t_RESET_min ≥ 1.2–1.3 × (t_MCU_coldclk + t_periph_init); threshold drift over temperature ≤ design tolerance; PG_AGG flap ≤ 1 per 10 power cycles; fanout budget
Σt_pd + t_rise ≤ 0.5 × t_RESET_min.
Deliverables: Stimuli CSV/JSON → automated capture & edge parsing → KPI summary table plus failed case waveforms. Log fields: temperature, lot, ΔV, Tdip, Iload, startup mode (0 V/pre-bias), and policy action (count/limit/RESET/retry-k).
Cross-Brand Shortlist
Priority types: Multi-rail programmable supervisors (I²C/PMBus/OTP) with window & debounce → Windowed supervisors (upper/lower + hysteresis) → PG aggregation / reset fanout buffers (OD/PP). Families below are in-production and procurement-friendly. External links use rel="nofollow".
| Brand | Family / Series (Rep. PNs) | Rails | Accuracy (±%) | Hysteresis (%) | I/F | Outputs | Iq | Notes (Why / Use-case) |
|---|---|---|---|---|---|---|---|---|
| TI | TPS3702-Q1 / TPS3703-Q1 (windowed) | 1–2 | ~0.5–1 | 2–5 typ. | Fixed / OTP | OD / PP | Low | Window + hysteresis for ripple/ring immunity; ideal for Buck→LDO chaining. |
| TI | TPS3890-Q1 / TPS3851-Q1 | 1 | ~0.5–1 | Built-in / options | Fixed / OTP | OD / PP | Ultra-low | Precise thresholds + programmable delay; align RESET width to cold clock domain. |
| TI | TPS386000/600x (multi-rail) | 3–4+ | ~1 | Prog./built-in | I²C / Fixed | OD / PP | Medium | Centralized multi-rail supervision; unify PG and timing before fanout. |
| ST | STM809/811 family (µP supervisors) | 1 | ~1–2 | Built-in | Fixed | OD / PP | Ultra-low | Baseline reset generation and light PG→RESET policy; cost-effective. |
| ST | L99xx / SBC (overview) | Integrated | — | — | SPI / I²C | OD and others | Medium | Domain controller/gateway; policy and supervision in one device. |
| NXP | FS65xx / SBC | Integrated | — | — | SPI / I²C / OTP | OD and others | Medium | Automotive-grade with reset/watchdog; fits unified policy designs. |
| Renesas | ISL8803x (rep. page) | 1–2 | ~1 | Built-in / options | Fixed / OTP | OD / PP | Low | Good threshold accuracy; consistent t_RESET_min implementation. |
| onsemi | NCV809/810 · NCV301/302 (category) | 1 | 1–2+ | Built-in | Fixed | OD / PP | Ultra-low / Low | Cost-effective anchors around a window chain or light policy path. |
| Microchip | MCP1316/1318/132x · MCP809/811 | 1 | ~1–2+ | Built-in / options | Fixed / OTP | OD / PP | Ultra-low / Low | Rich variants; easy to match polarity and RESET width; small footprint. |
| Microchip | MIC2779 / MIC2790 (dual/multi-rail) | 2–3 | ~1–2 | Options | Fixed / I²C (var.) | OD / PP | Low / Medium | Dual/multi-rail sync supervision for SoC + I/O split domains. |
| Melexis | MLX81116 (LIN lighting/driver w/ supervisor) | Integrated | — | — | LIN / I²C / SPI (per SBC) | OD and others | Medium | Body/lighting/motor domains with closed-loop supervision inside the SBC. |
Quick matching: Buck→LDO with ripple/ring → prefer windowed families (e.g., TPS3702-Q1); multi-rail or cross-domain with unified policy → choose multi-rail/programmable (e.g., TI TPS386000/600x, NXP FS series, Renesas/Microchip multi-rail); PG consolidation/fanout → OD aggregation + buffer plus low-Iq µP reset for t_RESET_min.
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FAQs
How do I choose UV/OV windows so soft-start overshoot won’t trip resets?
Set V_OV above worst case soft start overshoot and V_UV below minimum steady state minus 3 sigma of combined errors. Use asymmetric debounce so release is longer than assert. Validate with cold, room, and hot starts; pass if RESET never asserts and Vout reaches 95 percent within the target recovery time.
What debounce and release delays prevent nuisance resets during load steps?
Use asymmetric timing: choose t_assert near the fastest realistic dip but set t_release at or above the dominant loop settling time plus ring margin. Start with t_release ≥ T_95 of the slowest rail. Sweep step amplitude and slew; pass if nuisance reset count equals zero and recovery meets T_95 and T_98 limits.
How should PG-to-EN delays be set when a DC-DC feeds an LDO?
Set the delay approximately equal to SS_90 of the LDO minus SS_90 of the buck, then add temperature margin. Ensure the buck PG is true under the worst input ramp. Verify by tracing PG, EN, and Vout; pass if the LDO reaches 90 percent without chatter and no precharge back feeds the buck path.
What changes if the DC-DC must start into a pre-biased output?
Enable pre bias safe start on the converter and reduce soft start slope so inductor current builds without sinking the bias. Use a windowed supervisor with delayed release to ignore the initial transient window. Validate with 20 to 50 percent pre bias; pass if no UV or OV trips and output remains monotonic.
When is a windowed supervisor better than discrete UVLO + RC delay?
Prefer a windowed supervisor when ripple or ring exceeds about one percent of Vout, when multiple rails interact, or when temperature drift matters. Windows give precise hysteresis and independent assert and release timing. Validate with boundary scans around thresholds; pass if false resets drop below measurable levels versus an RC baseline.
How do I size RESET pulse width for a truly cold MCU clock domain?
Choose t_RESET_min at least one point two to one point three times the sum of cold start clock stabilization and peripheral initialization times, including any built in self tests or calibration. Validate by cold starting with the slowest oscillator; pass if firmware never re enters brown conditions and all peripherals enumerate correctly.
Open-drain vs push-pull RESET—what’s safer across mixed-voltage domains?
Use open drain for cross domain safety and wired OR aggregation, and pull up to the safest logic rail. Choose push pull only for single domain, short fanout, and matched levels. Validate by powering target domains off while the source is on; pass if no back power occurs and thresholds remain within spec.
How do I aggregate multiple PG signals without back-power or chatter?
Aggregate open drain PG pins, add small series resistors per source, and buffer at the hub with a Schmitt or dedicated aggregator. Use an RC at the hub for asymmetric filtering and ensure no reverse conduction path. Validate by injecting chatter on one source; pass if the hub output remains monotonic and clean.
What transient tests prove immunity—line dip, load step, or both, and at what rates?
Test both line dips and load steps across a grid of amplitudes and time constants, and include ripple and ring envelopes. Example set: dips of five, ten, and fifteen percent at fifty, two hundred, and five hundred microseconds; steps of twenty, fifty, and eighty percent at two amps per microsecond. Pass if nuisance resets equal zero.
How do temperature and drift affect thresholds and hysteresis across −40~+85 °C?
Budget hysteresis at or above ripple plus three sigma of drift from datasheet tempco and sense chain errors. Re characterise trip points at cold, room, and hot and compare against design margins. Pass if assert and release thresholds stay within tolerance and the release delay consistently exceeds the chosen settling time margin.
When should I use I²C/PMBus programmable supervisors vs fixed-threshold parts?
Use programmable supervisors for multi SKU platforms, field tuning, asymmetric windows, and coordinated timing across rails. Choose fixed threshold parts for lowest quiescent current, cost, and simplicity when variation is small. Validate by locking configuration or OTP and scripting register reads; pass if programmed values match the bill of materials targets.
What’s the minimal lab script to validate windows, delays, and reset timing?
Use a single JSON or CSV stimulus deck covering 0 volt and pre bias startups, the step and dip grid, and boundary points around UV and OV. Capture Vout, RESET, PG aggregate, and V buck. Auto parse edges into a KPI table. Pass if thresholds, delays, and reset width meet sign off gates.
